EP3495839A1 - Système de transmission d'un signal électrique - Google Patents

Système de transmission d'un signal électrique Download PDF

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Publication number
EP3495839A1
EP3495839A1 EP18210231.9A EP18210231A EP3495839A1 EP 3495839 A1 EP3495839 A1 EP 3495839A1 EP 18210231 A EP18210231 A EP 18210231A EP 3495839 A1 EP3495839 A1 EP 3495839A1
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EP
European Patent Office
Prior art keywords
signal
noise compensation
line
electronic device
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18210231.9A
Other languages
German (de)
English (en)
Other versions
EP3495839B1 (fr
Inventor
Alessandro BRISOTTO
Giancarlo Codutti
Andrea Englaro
Matteo Iellina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marelli Automotive Lighting Italy SpA
Original Assignee
Automotive Lighting Italia SpA
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Publication date
Application filed by Automotive Lighting Italia SpA filed Critical Automotive Lighting Italia SpA
Priority to EP22213073.4A priority Critical patent/EP4184876A1/fr
Publication of EP3495839A1 publication Critical patent/EP3495839A1/fr
Application granted granted Critical
Publication of EP3495839B1 publication Critical patent/EP3495839B1/fr
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/20—Arrangements affording multiple use of the transmission path using different combinations of lines, e.g. phantom working
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier

Definitions

  • the present invention relates to a transmission system of an electrical signal to be transmitted between two electronic devices, where the electrical signal has a frequency spectrum which comprises a noise component formed by harmonics suitable to generate electromagnetic disturbances.
  • the electrical signal to be transmitted is a signal having at least one variable component over time.
  • the electrical signal is a data signal of a digital bus.
  • a digital communication bus is formed of several cables, or wires, of a certain length, which can assume two different voltage values corresponding to two logic states, for example "0" and "1".
  • the logic state “0” is represented by a voltage of 0V
  • the logic state “1” is represented by a voltage of 5V.
  • a digital communication bus comprises a power cable, which assumes a constant voltage, an earth cable, which is also constant voltage, at least one data line, the voltage signal of which is a wave, such as a square wave, variable depending on the information to be transmitted.
  • Some digital communication buses also include a clock line, the voltage signal of which is a constant square wave.
  • the square waves of the clock line and the data line switch between a positive voltage, for example 5V, and the earth voltage, which serves as a common reference for the voltages of the electronic devices.
  • signals varying over time have a spectrum that contains high frequency harmonics capable of generating electromagnetic noise that can interfere with the operation of nearby electronic devices.
  • Another known solution is to divide the signal to be transmitted into two opposing components, which correspond to the respective transmission conductors, so that the emissions generated by each component compensate the emissions generated by the other component.
  • the two signal components must be recombined at the receiver device in order to obtain the original signal.
  • the object of the present invention is to propose a transmission system of an electrical signal having a limited amplitude spectrum at the frequencies or ranges of frequencies that generate electromagnetic disturbances, and which at the same time does not have the disadvantages spoken of in relation to the prior solutions.
  • Claim 1 refers to a transmission system of at least one electrical signal to be transmitted by a transmitting electronic device to at least a receiving electronic device, where each electrical signal contains all the information utilisable by the receiving electronic device and has a frequency spectrum which comprises a noise component formed by harmonics suitable to generate electromagnetic disturbances.
  • the transmission system comprises at least a signal line that connects the transmitting electronic device to the at least one receiving electronic device and which is suitable to transmit the respective electrical signal to be transmitted, and a signal generation unit, configured to generate the electrical signal to be transmitted on each signal line.
  • the transmission system further comprises at least a noise compensation line, and a noise compensation circuit configured to generate on each noise compensation line a noise compensation signal having at least one variable component that corresponds, setting aside a multiplication factor, to the inverted of at least a portion of the electrical signal or of the sum of the electrical signals to be transmitted.
  • the noise compensation signal thus generated emits an electromagnetic radiation around the noise compensation line that cancels or compensates at least in part, the electromagnetic radiation produced by the electrical signal/s to be transmitted.
  • the transmission system comprises, in addition to the signal lines, at least one noise compensation line.
  • noise compensation line does not carry any signal useful for composing the information content utilisable by the receiving device/s. All the information content, in fact, is contained in the signal line/s.
  • the noise compensation line is not necessarily connected to the receiving electronic device and may even extend only partially along the at least one signal line.
  • the noise compensation line may be a shorter length than the signal line.
  • the noise compensation signal has an amplitude greater than the electrical signal or the sum of the electrical signals to be transmitted.
  • the at least one noise compensation line is a line in high impedance disconnected from each receiving electronic device.
  • the at least one noise compensation line is composed of an antenna, for example confined in said transmitter device.
  • the noise compensation circuit may be positioned externally both to the transmitting electronic device and to the at least one receiving electronic device.
  • the noise compensation signal includes a positive constant component the value of which is chosen in such a way that the noise compensation signal never assumes a negative value. This way, the realization of the noise compensation circuit is greatly simplified.
  • the noise compensation circuit comprises at least one transistor inverter circuit which receives in input the electrical signal to be transmitted and supplies in output an electrical output signal and an inverter circuit noise compensation signal corresponding to the inverted of the electrical output signal. This way, there is no delay, or there is an insignificant delay between the transmission of the electrical signal to be transmitted and its inverted which is transmitted on the noise compensation line.
  • the transmission system comprises at least two signal lines to transmit respective electric signals to be transmitted, and a noise compensation circuit comprising a transistor inverter circuit for each electrical signal to be transmitted, wherein the noise compensation signal is given by the sum of the inverter circuit noise compensation signals present in output of the respective inverter circuits.
  • a single noise compensation line cancels or compensates at least partially the noise generated by two or more signal lines.
  • such a noise compensation circuit is connected to a voltage amplifying device suitable to generate an amplified supply voltage able to polarize in linear zone the transistors of the transistor inverter circuits even when the electrical signals to be transmitted simultaneously assume their highest level.
  • the voltage amplifying device is implemented with a charge pump.
  • the signal line is a data line of a digital bus, the signal generation unit being a bus control unit.
  • a clock line of the digital bus is also used, the bus control unit being configured to generate on the data line a data signal that switches between a low logic level and a high logic level as a function of the data to be transmitted and to generate on the clock line a clock signal that switches with constant frequency between the low logic level and the high logic level.
  • the noise compensation circuit receives the data signal and the clock signal generated by the bus control unit and provides the data line of the digital bus with a data output signal and the clock line of the digital bus with a clock output signal, said data and clock output signals having a logic level corresponding to the logic level of the respective data signal and clock signal.
  • the noise compensation circuit is powered by a constant power supply voltage and comprises:
  • the compensation signal being given by the sum of the noise compensation signal of the clock line with the noise compensation signal of the data line.
  • transmitting electronic device and “receiving electronic device” have been used to indicate that the transmission of a signal is carried out by a device (transmitter) to another (receiver) (or several receiving devices). This does not imply, however, that an electronic device is configured only to transmit or only to receive a signal; on the contrary, in some embodiments described below a transmission line may be two-way, in the sense that a device indicated as a receiver can in turn transmit a signal to the device specified as a transmitter (as in the case of a data signal digital communication bus).
  • Figure 1 represents a variable square wave signal, for example as a function of information to be transmitted, which may be for example an SDA data line of a digital communication bus, such as the "IC2" bus or "Lyn” bus, or a PWM ("Pulse Width Modulation" signal).
  • a variable square wave signal for example as a function of information to be transmitted, which may be for example an SDA data line of a digital communication bus, such as the "IC2" bus or "Lyn” bus, or a PWM (“Pulse Width Modulation" signal).
  • Figure 1a shows instead a constant square wave signal, for example, the SCL clock or carrier signal of a digital communication bus.
  • the power supply line and the earth line do not generate any variable electromagnetic field over time, do not contribute to the formation of disturbances and will therefore not be taken into consideration.
  • the bus can be modelled by a circuit which comprises an antenna 10 connected by means of a parasitic capacitance C1; C2 to each of the SDA and SCL lines.
  • noise sources VSDA and VSCL represented by variable voltage generators, with respect to earth, different from each other.
  • the noise sources VSDA and VSCL generate noise during voltage variations, i.e. of the logic states, on the SDA and SCL lines, respectively.
  • the SDA and SCL lines end with two respective impedances Z1 and Z2, which represent, for each frequency of the noise spectrum, the impedances heard from the circuit to which the digital bus is connected.
  • the antenna can be modelled as an R impedance of the resistive type, typically normalized to 50 ⁇ , connected to earth.
  • the noise voltages VSDA and VSCL vary, for example, between 0 and 5 volts, while the impedances Z1 and Z2 can be identified as an open circuit, given that the frequencies involved are low, the currents on the SDA and SCL lines are very low (in the order of ⁇ A) and the input circuits to which the SDA and SCL lines are connected, for example, the input circuits of operational amplifiers, normally have a high impedance at low frequency.
  • the digital bus noise generator circuit can be modelled with the electrical circuit in Figure 3 .
  • the SDA and SCL lines are also connected to the antenna through an inductive component, in addition to the capacitive C; however, at low frequencies, the component of the electric field is far greater than that of the magnetic field and the inductive component can therefore be ignored.
  • the idea underlying the present invention is to make the voltage VA felt by the antenna equal to 0, so as to cancel the current flowing in the antenna.
  • VOUT ⁇ VSDA + VSCL + VBATT
  • the noise compensation line which is introduced has the sole purpose of compensating the effect of one or more signal lines responsible for the noise and does not carry therefore any useful signal for the purposes of the information content to be transmitted to the receiving device.
  • the signal or signals that generate noise carry all the information which must be transmitted to the receiving electronic device.
  • the noise compensation line need not be connected to both the transmitting and receiving devices, but may be shorter than the signal lines that generate noise or even be in the form of an antenna.
  • the transmission system according to the invention can be designed to operate only with voltages greater than or equal to zero.
  • the transmission system transmits, together with the signal or signals to be transmitted which generate noise, at least one noise compensation signal having at least one variable component that corresponds, setting aside a multiplication factor, to the inverted of at least a portion of the signal or sum of signals to be transmitted, to which a constant voltage is added.
  • noise compensation signal having at least one variable component which corresponds, setting aside a multiplication factor, to the inverted of the entire signal or sum of signals to be transmitted.
  • the noise compensation signal is obtained by the inversion of a portion of the signal or of the sum of the signals to be transmitted.
  • the transmission system limits itself to elaborating the signal or the sum of the signals to be transmitted within a temporal portion of the time interval in which such signals to be transmitted are generated.
  • the microprocessor may perform a sampling of the signals to be transmitted, for example randomly, so as to obtain a portion thereof from which to obtain the inverted signal.
  • the circuit implementation of the idea underlying the invention requires solving the problem, by no means easy, of generating the VOUT signal in a perfectly synchronous manner to the signal to be transmitted, for example V SDA+ VSCL.
  • the signals to be transmitted and the noise compensation signal/s must be transmitted in the transmission system in a synchronous manner, i.e. without the compensation signal having even a minimal delay with respect to the noise generation signals.
  • a one-way signal compensation circuit 20 is used, known as a "phase-shifter", able to generate an inverted signal without any delay with respect to the non-inverted input signal.
  • V SCL Volt
  • V BE Volt
  • V SCL_OUT Volt
  • Transistor Q 0 0 0 Cut-out 5 0.7 4.3 Polarised in linear zone
  • V SCL_OUT V SCL - V BE , having considered V Rb negligible.
  • VOUT is the inverted of VSCL_OUT, setting aside the constant voltage VBATT.
  • the signal VSCL_OUT has a value of 4.3 V, but this approximation is within the tolerances set for the digital bus.
  • phase-shifter circuit described above is not, however, suitable to transmit a signal in the opposite direction too, so it cannot be used for example for the signal VSDA of a data line to a digital communications bus.
  • V SDA 5 V
  • VOUT is the inverted of VSDA, setting aside a constant voltage VBATT.
  • FIG. 6 is a circuit diagram of a transmission system according to the invention, in one embodiment.
  • the signal to be transmitted on the SDA signal line is generated by a signal generation unit 50, for example a microcontroller, inside the transmitting device 60, for example a control unit of a digital communication bus.
  • a signal generation unit 50 for example a microcontroller
  • the transmitting device 60 for example a control unit of a digital communication bus.
  • the electrical signal to be transmitted is transmitted through the SDA signal line which is connected to one or more receiving devices 70, in the example illustrated a plurality of LED lighting sources and relative LED drivers 70'.
  • the SDA signal line for the signal to be transmitted is a two-way line and the noise compensation circuit of the two-way signal 30, described above and illustrated in Figure 5 is therefore used.
  • the transmission system thus comprises, in addition to the SDA signal line, a two-way signal noise compensation line 302, connected to the output OUT of the noise compensation circuit of the two-way signal 30.
  • this two-way signal noise compensation line 302 is a high impedance line.
  • such noise compensation line 302 discharges to earth through a large impedance R6, R7, R8.
  • the noise compensation signal present on the output terminal OUT of the noise compensation circuit of the two-way signal 30 is a voltage signal which generates an electromagnetic radiation in the surrounding space that cancels or compensates for the electromagnetic interference generated by the SDA signal line.
  • the noise compensation line 302 is not connected to the receiving devices 70, such a line may have a different extension, and in particular lesser, than the signal line.
  • the noise compensation signal amplitude can be multiplied by a factor which depends on the length of the noise compensation line.
  • the noise compensation line is composed of an antenna 304, which may for example even be confined to the transmitting device 60 (if the distance of the receiving devices from the transmitting device is limited).
  • the transmission system is a digital bus 80, for example the bus "I2C", comprising an SDA data line and an SCL clock line.
  • the electrical signals to be transmitted on such lines are generated by signal generation unit 50, for example a microcontroller, inside the control unit 60 of the digital communication bus.
  • the control unit 60 controls the peripheral electronic devices 70 or the receiving devices, connected to the digital communication bus, in the example illustrated a plurality of LED lighting sources and related LED drivers 70'.
  • the SDA data line is a two-way line.
  • the SCL clock line is a one-way line, and thus to compensate for the noise generated by such line the one-way signal noise compensation circuit 20 is used.
  • the digital transmission bus 80 comprises, in addition to the SDA data line and the SCL clock line, two noise compensation lines 202; 302, each connected to the output terminal OUT1; OUT2 of the respective noise compensation circuit 20; 30.
  • each noise compensation line 202, 302 is a high impedance line not connected to the receiving devices 70 and therefore of variable length as needed.
  • each noise compensation line may also be constituted by an antenna, for example confined to the transmitting device 60 (if the distance of the receiving devices from the transmitting device is limited).
  • the one-way signal noise compensation circuit 20 and the two-way signal data compensation circuit 30 are combined so as to form a single combined noise compensation circuit 40 capable of generating the compensation voltage suitable to compensate for the overall noise given by the two SDA and SCL signals.
  • Such combined noise compensation circuit 40 is shown in Figure 9 and in the circuit diagrams of Figures 10-13 .
  • the table in Figure 14 shows the values of the SCL_OUT clock signals and SDA_OUT data signals transmitted on the bus, along with the noise compensation signal VOUT able to compensate the noise sources associated with the SCL_OUT and SDA_OUT signals.
  • the compensation of the bus noise is thus given by the sum of the contributions of the noise sources VSDA_OUT + VSCL_OUT with the compensation voltage VOUT, setting aside a constant voltage VBATT.
  • the voltage on node A at the ends of the antenna does not vary substantially (setting aside the polarisation voltages of the semiconductor components). In other words, the voltage at node A is substantially equal to 0.
  • the digital transmission bus 80a illustrated in the circuit diagram of Figure 10 shows the use of a combined noise compensation circuit 40 in place of the two compensation circuits 20, 30 described above.
  • the digital communication bus 80a comprises the data output line SDA_OUT (which coincides with the SDA data line in output from the signal generation unit 50), the clock output line SCL_OUT, and a single noise compensation line 404, connected to the output terminal OUT of the combined noise compensation circuit 40.
  • the combined noise compensation circuit 40 resides in the electronic control unit 60.
  • said noise compensation circuit 40 could also be implemented indifferently in one of the peripheral devices 70 controlled by the electronic control unit 60 via the digital communication bus, or along the bus itself, in a position between the transmitting device and the receiving devices.
  • the noise compensation circuit 40 is made externally to both the electronic transmitting device 60 (the control unit) and to the receiving electronic devices (the peripheral devices 70).
  • the noise compensation circuit 40 is made inside one of the peripheral devices 70.
  • the compensation circuit 40 described above operates correctly when the nominal voltage VBATT which powers the circuit and provides the offset value for the compensation signal is of a level sufficient to polarise the transistors Q1 and Q2 in the linear zone.
  • the power supply voltage VBATT must be at least 13.5V, in order to still have 3.5V for polarising the transistors.
  • a voltage amplifying device 80 should be introduced suitable to maintain the power supply voltage VBATT at a value such as to polarise the transistors Q1 and Q2 of the compensation circuit.
  • such amplification device can be made with a DC/DC converter or, more preferably, with a charge pump, of the type illustrated in the circuit diagram in Figure 15 .
  • the charge pump would be preferable with respect to the DC/DC, since the latter in turn introduces noise.
  • the charge pump substantially doubles the input voltage.
  • the charge pump comprises a MOS-FET transistor Q2 which doubles the input voltage on its source terminal S.
  • the gate G of the MOS-FET is connected to the source via a resistor R and to the drain through an energy storage capacitor C.
  • the MOS-FET is driven by a PWM signal, for example through a driver transistor Q1, the collector of which is connected to the gate G of the MOS-FET.
  • the driver transistor Q1 When the driver transistor Q1 is in saturation, the collector C is brought to earth and then the MOS-FET Q2 is brought into saturation and the capacitor C is charged by a diode D, at the input voltage, for example 5V.
  • the digital communication bus in Figure 10 uses a compensation circuit 40 equipped with an amplification block 90 of the supply voltage VBATT , able for example to raise the voltage from 13.5V to 15V.
  • the noise compensation circuit can be implemented with a microcontroller 50' configured to generate, in addition to the signals to be transmitted, for example, the SCL clock and SDA data signals, also the noise compensation signal/s.
  • phase-shifter integrated in the microcontroller can be used.
  • a further object of the present invention relates to a lighting device, such as a vehicle light 100, comprising an electronic control unit 60, one or more peripheral circuits 70 that each comprise a plurality of LED lighting sources driven by a respective LED driver, for example, but not necessarily, resident on the respective electronic circuit boards, where the electronic control unit 60 controls the peripheral circuits by means of a digital communication bus 80; 80a made according to one of the possible embodiments described above.
  • a lighting device such as a vehicle light 100, comprising an electronic control unit 60, one or more peripheral circuits 70 that each comprise a plurality of LED lighting sources driven by a respective LED driver, for example, but not necessarily, resident on the respective electronic circuit boards, where the electronic control unit 60 controls the peripheral circuits by means of a digital communication bus 80; 80a made according to one of the possible embodiments described above.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Nonlinear Science (AREA)
  • Dc Digital Transmission (AREA)
EP18210231.9A 2017-12-07 2018-12-04 Système de transmission d'un signal électrique Active EP3495839B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22213073.4A EP4184876A1 (fr) 2017-12-07 2018-12-04 Système de transmission d'un signal électrique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT201700141773 2017-12-07

Related Child Applications (2)

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EP22213073.4A Division EP4184876A1 (fr) 2017-12-07 2018-12-04 Système de transmission d'un signal électrique
EP22213073.4A Division-Into EP4184876A1 (fr) 2017-12-07 2018-12-04 Système de transmission d'un signal électrique

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EP3495839A1 true EP3495839A1 (fr) 2019-06-12
EP3495839B1 EP3495839B1 (fr) 2023-10-18

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US (1) US10623210B2 (fr)
EP (2) EP3495839B1 (fr)
CN (1) CN109905304B (fr)
ES (1) ES2964859T3 (fr)
PL (1) PL3495839T3 (fr)

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US11177856B2 (en) * 2020-02-03 2021-11-16 Qualcomm Incorporated Crosstalk amelioration systems and methods in a radio frequency front end (RFFE) communication system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5915989A (en) * 1997-05-19 1999-06-29 Lucent Technologies Inc. Connector with counter-balanced crosswalk compensation scheme
US20010004558A1 (en) * 1999-12-15 2001-06-21 Pace Micro Technology Plc Reduction of noise on cable

Family Cites Families (5)

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KR101559501B1 (ko) * 2009-04-08 2015-10-15 삼성전자주식회사 지터를 보상하는 반도체 집적 회로 및 지터 보상 방법
US20120299480A1 (en) * 2009-11-06 2012-11-29 Neofocal Systems, Inc. System And Method For Current Modulated Data Transmission
KR101678413B1 (ko) * 2009-12-29 2016-11-23 삼성전자주식회사 반도체 장치 및 이의 트레이닝 방법
KR102098248B1 (ko) * 2013-06-03 2020-04-07 삼성전자 주식회사 온도에 따라 완화된 타이밍 요건으로 사용되는 메모리 장치 및 이를 이용하는 메모리 콘트롤러
TWI569185B (zh) * 2015-11-06 2017-02-01 財團法人工業技術研究院 觸控裝置及其雜訊補償電路及雜訊補償方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5915989A (en) * 1997-05-19 1999-06-29 Lucent Technologies Inc. Connector with counter-balanced crosswalk compensation scheme
US20010004558A1 (en) * 1999-12-15 2001-06-21 Pace Micro Technology Plc Reduction of noise on cable

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CN109905304A (zh) 2019-06-18
ES2964859T3 (es) 2024-04-09
CN109905304B (zh) 2022-12-09
EP4184876A1 (fr) 2023-05-24
PL3495839T3 (pl) 2024-03-25
EP3495839B1 (fr) 2023-10-18
US10623210B2 (en) 2020-04-14
US20190182078A1 (en) 2019-06-13

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