EP3420560B1 - Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs - Google Patents

Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs Download PDF

Info

Publication number
EP3420560B1
EP3420560B1 EP16891038.8A EP16891038A EP3420560B1 EP 3420560 B1 EP3420560 B1 EP 3420560B1 EP 16891038 A EP16891038 A EP 16891038A EP 3420560 B1 EP3420560 B1 EP 3420560B1
Authority
EP
European Patent Office
Prior art keywords
memory
electronics system
signal
ray
electronics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP16891038.8A
Other languages
German (de)
English (en)
Other versions
EP3420560A1 (fr
EP3420560A4 (fr
Inventor
Peiyan CAO
Huabin CHENG
Yurun LIU
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Xpectvision Technology Co Ltd
Original Assignee
Shenzhen Xpectvision Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Xpectvision Technology Co Ltd filed Critical Shenzhen Xpectvision Technology Co Ltd
Publication of EP3420560A1 publication Critical patent/EP3420560A1/fr
Publication of EP3420560A4 publication Critical patent/EP3420560A4/fr
Application granted granted Critical
Publication of EP3420560B1 publication Critical patent/EP3420560B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/32—Transforming X-rays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/30—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from X-rays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells

Definitions

  • the disclosure herein relates to methods of reading data from a semiconductor image detector, particularly a semiconductor X-ray image detector.
  • X-ray detectors may be devices used to measure the flux, spatial distribution, spectrum or other properties of X-rays.
  • X-ray detectors may be used for many applications. One important application is imaging. An X-ray detector that is configured to detect an X-ray image may be called an X-ray imaging detector. X-ray imaging is a radiography technique and can be used to reveal the internal structure of a non-uniformly composed and opaque object such as the human body.
  • a photographic plate may be a glass plate with a coating of light-sensitive emulsion. Although photographic plates were replaced by photographic films, they may still be used in special situations due to the superior quality they offer and their extreme stability.
  • a photographic film may be a plastic film (e.g., a strip or sheet) with a coating of light-sensitive emulsion.
  • PSP plates photostimulable phosphor plates
  • a PSP plate may contain a phosphor material with color centers in its lattice.
  • electrons excited by X-ray are trapped in the color centers until they are stimulated by a laser beam scanning over the plate surface.
  • trapped excited electrons give off light, which is collected by a photomultiplier tube. The collected light is converted into a digital image.
  • PSP plates can be reused.
  • X-ray image intensifiers Components of anX-ray image intensifier are usually sealed in a vacuum. In contrast to photographic plates, photographic films, and PSP plates, X-ray image intensifiers may produce real-time images, i.e., do not require post-exposure processing to produce images.
  • X-ray first hits an input phosphor (e.g., cesium iodide) and is converted to visible light. The visible light then hits a photocathode (e.g., a thin metal layer containing cesium and antimony compounds) and causes emission of electrons. The number of emitted electrons is proportional to the intensity of the incident X-ray. The emitted electrons are projected, through electron optics, onto an output phosphor and cause the output phosphor to produce a visible-light image.
  • an input phosphor e.g., cesium iodide
  • a photocathode e.g., a thin metal layer containing cesium and antimony compounds
  • Scintillators operate somewhat similarly to X-ray image intensifiers in that scintillators (e.g., sodium iodide) absorb X-ray and emit visible light, which can then be detected by a suitable image sensor for visible light.
  • scintillators e.g., sodium iodide
  • the visible light spreads and scatters in all directions and thus reduces spatial resolution. Reducing the scintillator thickness helps to improve the spatial resolution but also reduces absorption of X-ray. A scintillator thus has to strike a compromise between absorption efficiency and resolution.
  • a semiconductor X-ray detector may include a semiconductor layer that absorbs X-ray in wavelengths of interest. When an X-ray photon is absorbed in the semiconductor layer, multiple charge carriers (e.g., electrons and holes) are generated and swept under an electric field towards electrical contacts on the semiconductor layer. Cumbersome heat management required in currently available semiconductor X-ray detectors (e.g., Medipix) can make a detector with a large area and a large number of pixels difficult or impossible to produce.
  • semiconductor X-ray detectors e.g., Medipix
  • an image sensor may include an array of image pixels arranged in rows and columns. Image pixels are coupled to pixel column lines which have column memory circuitry including a spare column memory circuit. If one of the column memory circuits is defective, the spare column memory circuit is engaged to bypass the defective column memory circuit to provide column-wise memory repair capabilities.
  • US 4,254,477 discloses a device comprising an interconnect switch for the selective coupling of serial memory elements in series with other memory elements.
  • a control unit may test elements, designate some of the elements as operable for use and designate other elements as spares.
  • an apparatus suitable for detecting an image comprising: a plurality of pixels configured to generate an electric signal upon exposure to a radiation; an electronics system associated with each of the pixels, wherein the electronics system is configured to receive electric signals shifted from an electronics system of an upstream pixel and to shift out electric signals to an electronic system of a downstream pixel; wherein the electronics system comprises a first memory on a first signal path and a second memory on a second signal path, both signal paths being between an input terminal and an output terminal of the electronics system; wherein each of the first memory and the second memory is configured to: store an electric signal generated by the pixel the electronics system is associated with; store an electric signal shifted from the electronics system of an upstream pixel; and transmit an electric signal to the electronics system of a downstream pixel; and wherein the electronics system comprises a first switch arranged at the input terminal and a second switch arranged at the output terminal, the first and second switches being configured to select one of the signal paths, wherein the first signal path is selected
  • the input terminal is configured to receive signal into the electronics system and the output terminal is configured to transmit signal stored in the electronics system to downstream circuitry.
  • the second signal path is selected when the first memory is defective.
  • the apparatus is configured to detect an X-ray image.
  • the electronics system comprises a memory configured to store a code representing a defectiveness state and a selection of the signal path.
  • the memory may have redundancy.
  • the memory is a non-volatile memory.
  • the apparatus further comprises a memory configured to store codes representing defectiveness states and selection of signal paths of the plurality of electronics systems.
  • the memory is a non-volatile memory.
  • the apparatus further comprises a controller configured to select the signal paths in the plurality of electronics systems based on the codes representing a defectiveness state and a selection of the signal path.
  • the codes representing a defectiveness state and a selection of the signal path may be stored in the memory configured to store these codes.
  • the apparatus may be configured to select between the redundant memories, collectively for a group of electronics systems.
  • the memory is a removable dongle.
  • the apparatus is disabled unless the removable dongle is present.
  • the electronics system comprises a bypass path that connects the input terminal and the output terminal, without a memory on the bypass path; wherein the electronics system comprises a switch configured to select the first signal path, the second signal path or the bypass path.
  • an apparatus suitable for detecting an image comprising: a plurality of pixels configured to generate an electric signal upon exposure to a radiation; an electronics system associated with each of the pixels, wherein the electronics system is configured to receive electric signals shifted from an electronics system of an upstream pixel and to shift out electric signals to an electronic system of a downstream pixel; wherein the electronics system comprises a first memory on a signal path between an input terminal and an output terminal of the electronics system wherein the first memory is configured to: store an electric signal generated by the pixel the electronics system is associated with; store an electric signal shifted from the electronics system of an upstream pixel; and transmit an electric signal to the electronics system of a downstream pixel; wherein the electronics system comprises a bypass path that connects the input terminal and the output terminal, without a memory on the bypass path; and wherein the electronics system comprises a first switch arranged at the input terminal and a second switch arranged at the output terminal, the first and second switches being configured to select the signal path or the bypass path
  • the input terminal is configured to receive signal into the electronics system and the output terminal is configured to transmit signal stored in the electronics system to downstream circuitry.
  • the apparatus is configured to detect an X-ray image.
  • the electronics system comprises a memory configured to store a code representing a defectiveness state and a selection of the signal path or the bypass path.
  • the memory is a non-volatile memory.
  • the apparatus further comprises a memory configured to store codes representing defectiveness states and selection of signal paths or the bypass paths of the plurality of electronics systems.
  • the memory is a non-volatile memory.
  • the apparatus further comprises a controller configured to select the signal paths or the bypass paths in the plurality of electronics systems based on the codes.
  • Fig. 1A schematically shows a cross-sectional view of an X-ray image detector 100, according to an embodiment.
  • the detector 100 may include an X-ray absorption layer 110 and an electronics layer 120 (e.g., an ASIC) for processing or analyzing electrical signals incident X-ray generates in the X-ray absorption layer 110.
  • the detector 100 does not comprise a scintillator.
  • the X-ray absorption layer 110 may include a semiconductor material such as, silicon, germanium, GaAs, CdTe, CdZnTe, or a combination thereof.
  • the semiconductor may have a high mass attenuation coefficient for the X-ray energy of interest.
  • the X-ray absorption layer 110 may include one or more diodes (e.g., p-i-n or p-n) formed by a first doped region 111, one or more discrete regions 114 of a second doped region 113.
  • the second doped region 113 may be separated from the first doped region 111 by an optional the intrinsic region 112.
  • the discrete portions 114 are separated from one another by the first doped region 111 or the intrinsic region 112.
  • the first doped region 111 and the second doped region 113 have opposite types of doping (e.g., region 111 is p-type and region 113 is n-type, or region 111 is n-type and region 113 is p-type).
  • each of the discrete regions 114 of the second doped region 113 forms a diode with the first doped region 111 and the optional intrinsic region 112.
  • the X-ray absorption layer 110 has a plurality of diodes having the first doped region 111 as a shared electrode.
  • the first doped region 111 may also have discrete portions.
  • the X-ray photon When an X-ray photon hits the X-ray absorption layer 110 including diodes, the X-ray photon may be absorbed and generate one or more charge carriers by a number of mechanisms.
  • An X-ray photon may generate 10 to 100000 charge carriers.
  • the charge carriers may drift to the electrodes of one of the diodes under an electric field.
  • the field may be an external electric field.
  • the electrical contact 119B may include discrete portions each of which is in electrical contact with the discrete regions 114.
  • the charge carriers may drift in directions such that the charge carriers generated by a single X-ray photon are not substantially shared by two different discrete regions 114 ("not substantially shared” here means less than 2%, less than 0.5%, less than 0.1%, or less than 0.01% of these charge carriers flow to a different one of the discrete regions 114 than the rest of the charge carriers).
  • Charge carriers generated by an X-ray photon incident around the footprint of one of these discrete regions 114 are not substantially shared with another of these discrete regions 114.
  • a pixel 150 associated with a discrete region 114 may be an area around the discrete region 114 in which substantially all (more than 98%, more than 99.5%, more than 99.9%, or more than 99.99% of) charge carriers generated by an X-ray photon incident therein flow to the discrete region 114. Namely, less than 2%, less than 1%, less than 0.1%, or less than 0.01% of these charge carriers flow beyond the pixel.
  • the X-ray absorption layer 110 may include a resistor of a semiconductor material such as, silicon, germanium, GaAs, CdTe, CdZnTe, or a combination thereof, but does not include a diode.
  • the semiconductor may have a high mass attenuation coefficient for the X-ray energy of interest.
  • an X-ray photon When an X-ray photon hits the X-ray absorption layer 110 including a resistor but not diodes, it may be absorbed and generate one or more charge carriers by a number of mechanisms.
  • An X-ray photon may generate 10 to 100000 charge carriers.
  • the charge carriers may drift to the electrical contacts 119A and 119B under an electric field.
  • the field may be an external electric field.
  • the electrical contact 119B includes discrete portions.
  • the charge carriers may drift in directions such that the charge carriers generated by a single X-ray photon are not substantially shared by two different discrete portions of the electrical contact 119B ("not substantially shared” here means less than 2%, less than 0.5%, less than 0.1%, or less than 0.01% of these charge carriers flow to a different one of the discrete portions than the rest of the charge carriers).
  • Charge carriers generated by an X-ray photon incident around the footprint of one of these discrete portions of the electrical contact 119B are not substantially shared with another of these discrete portions of the electrical contact 119B.
  • a pixel 150 associated with a discrete portion of the electrical contact 119B may be an area around the discrete portion in which substantially all (more than 98%, more than 99.5%, more than 99.9% or more than 99.99% of) charge carriers generated by an X-ray photon incident therein flow to the discrete portion of the electrical contact 119B. Namely, less than 2%, less than 0.5%, less than 0.1%, or less than 0.01% of these charge carriers flow beyond the pixel associated with the one discrete portion of the electrical contact 119B.
  • the electronics layer 120 may include an electronic system 121 suitable for processing or interpreting signals generated by X-ray photons incident on the X-ray absorption layer 110.
  • the electronic system 121 may include an analog circuitry such as a filter network, amplifiers, integrators, and comparators, or a digital circuitry such as a microprocessors, and memory.
  • the electronic system 121 may include components shared by the pixels or components dedicated to a single pixel.
  • the electronic system 121 may include an amplifier dedicated to each pixel and a microprocessor shared among all the pixels.
  • the electronic system 121 may be electrically connected to the pixels by vias 131.
  • Space among the vias may be filled with a filler material 130, which may increase the mechanical stability of the connection of the electronics layer 120 to the X-ray absorption layer 110.
  • Other bonding techniques are possible to connect the electronic system 121 to the pixels without using vias.
  • the an electronic system 121 may be configured to count X-ray photons by the pixels or configured to measure the amounts of charge carriers accumulated at the pixels (e.g., by using an analog-to-digital converter (ADC) shared by the pixels).
  • ADC analog-to-digital converter
  • Fig. 2 schematically shows that the detector 100 may have an array of pixels 150.
  • the array may be a rectangular array, a honeycomb array, a hexagonal array or any other suitable array.
  • Each pixel 150 may be configured to detect an X-ray photon incident thereon, measure the energy of the X-ray photon, or both.
  • each pixel 150 may be configured to count numbers of X-ray photons incident thereon whose energy falls in a plurality of bins, within a period of time. All the pixels 150 may be configured to count the numbers of X-ray photons incident thereon within a plurality of bins of energy within the same period of time.
  • Each pixel 150 may have its own analog-to-digital converter (ADC) configured to digitize an analog signal representing the energy of an incident X-ray photon into a digital signal.
  • the ADC may have a resolution of 10 bits or higher.
  • Each pixel 150 may be configured to measure its dark current, such as before or concurrently with each X-ray photon incident thereon.
  • Each pixel 150 may be configured to deduct the contribution of the dark current from the energy of the X-ray photon incident thereon.
  • the pixels 150 may be configured to operate in parallel. For example, when one pixel 150 measures an incident X-ray photon, another pixel 150 may be waiting for an X-ray photon to arrive.
  • the pixels 150 may be but do not have to be individually addressable.
  • Fig. 3A schematically shows the electronics layer 120 according to an embodiment.
  • the electronic layer 120 comprises a substrate 122 having a first surface 124 and a second surface 128.
  • a "surface" as used herein is not necessarily exposed, but can be buried wholly or partially.
  • the electronic layer 120 comprises one or more electric contacts 125 on the first surface 124.
  • the one or more electric contacts 125 may be configured to be electrically connected to one or more electrical contacts 119B of the X-ray absorption layer 110.
  • the electronics system 121 may be in or on the substrate 122.
  • the electronic layer 120 comprises one or more vias 126 extending from the first surface 124 to the second surface 128.
  • the electronic layer 120 may comprise a redistribution layer (RDL) 123 on the second surface 128.
  • RDL redistribution layer
  • the RDL 123 may comprise one or more transmission lines 127.
  • the electronics system 121 is electrically connected to the electric contacts 125 and the transmission lines 127 through the vias 126.
  • the RDL 123 may include one or more vias 129 configured to electrically connect the transmission lines 127 to circuitry outside the electronics layer 120.
  • the substrate 122 may be a thinned substrate.
  • the substrate may have at thickness of 750 microns or less, 200 microns or less, 100 microns or less, 50 microns or less, 20 microns or less, or 5 microns or less.
  • the substrate 122 may be a silicon substrate or a substrate or other suitable semiconductor or insulator.
  • the substrate 122 may be produced by grinding a thicker substrate to a desired thickness.
  • the one or more electric contacts 125 may be a layer of metal or doped semiconductor.
  • the electric contacts 125 may be gold, copper, platinum, palladium, doped silicon, etc.
  • the vias 126 pass through the substrate 122 and electrically connect electrical components (e.g., the electrical contacts 125) on the first surface 124 to electrical components (e.g., the RDL) on the second surface 128.
  • electrical components e.g., the electrical contacts 125
  • electrical components e.g., the RDL
  • the vias 126 are sometimes referred to as "through-silicon vias" although they may be fabricated in substrates of materials other than silicon.
  • the RDL 123 may comprise one or more transmission lines 127.
  • the transmission lines 127 electrically connect electrical components (e.g., the vias 126) in the substrate 122 to bonding pads at other locations on the substrate 122.
  • the transmission lines 127 may be electrically isolated from the substrate 122 except at certain vias 126 and certain bonding pads.
  • the transmission lines 127 may be a material (e.g., AI) with small mass attenuation coefficient for the X-ray energy of interest.
  • the RDL 123 may redistribute electrical connections to more convenient locations.
  • the RDL 123 is especially useful when the detector 100 has a large number of pixels. If the detector 100 does not have a large number of pixels, the RDL 123 may be omitted and signals from the pixels may be routed on the first surface 124.
  • Fig. 3A further schematically shows bonding between the X-ray absorption layer 110 and the electronic layer 120 at the electrical contact 119B and the electrical contacts 125.
  • the bonding may be by a suitable technique such as direct bonding or flip chip bonding.
  • Direct bonding is a wafer bonding process without any additional intermediate layers (e.g., solder bumps).
  • the bonding process is based on chemical bonds between two surfaces. Direct bonding may be at elevated temperature but not necessarily so.
  • Flip chip bonding uses solder bumps 199 deposited onto contact pads (e.g., the electrical contact 119B of the X-ray absorption layer 110 or the electrical contacts 125). Either the X-ray absorption layer 110 or the electronic layer 120 is flipped over and the electrical contact 119B of the X-ray absorption layer 110 are aligned to the electrical contacts 125.
  • the solder bumps 199 may be melted to solder the electrical contact 119B and the electrical contacts 125 together. Any void space among the solder bumps 199 may be filled with an insulating material.
  • Fig. 3B schematically shows the electronics layer 120 according to an embodiment.
  • the electronics layer 120 shown in Fig. 3B is different from the electronics layer 120 shown in Fig. 3A in the following ways.
  • the electronics system 121 is buried in the substrate 122.
  • the electronic layer 120 comprises one or more vias 126A extending from the first surface 124 to the second surface 128.
  • the vias 126A electrically connect the electrical contacts 125 to the transmission lines 127 in the RDL 123 on the second surface 128.
  • the electronic layer 120 further comprises one or more vias 126B extending from the second surface 128 to the electronics system 121.
  • the vias 126B electrically connect the transmission lines 127 to the electronics system 121.
  • the X-ray absorption layer 110 and the electronic layer 120 may also be bonded together (e.g., at the electrical contact 119B and the electrical contacts 125) by a suitable technique such as direct bonding or flip chip bonding.
  • Fig. 3C schematically shows the electronics layer 120 according to an embodiment.
  • the electronics layer 120 shown in Fig. 3C is different from the electronics layer 120 shown in Fig. 3A in the following ways.
  • the electronics system 121 is buried in the substrate 122.
  • the electronic layer 120 does not comprise one or more electric contacts 125 on the first surface 124.
  • the substrate 122 including the buried electronics system 121 is bonded to the X-ray absorption layer 110 by direct bonding. Holes are formed in the substrate 123 and filled with metal to form the vias 126A that electrically route the electrical contact 119B to the second surface 128 and to form the vias 126B that electrically route the electronics system 121 to the second surface 128.
  • the RDL 123 is then formed on the second surface 128 such that the transmission lines 127 electrically connect the vias 126A and 126B to complete the electrical connection from the electrical contact 119B to the electronics system 121.
  • the X-ray absorption layer 110 may include multiple discrete chips. Each of the chips may be bonded to the electronic layer 120 individually or collectively. The X-ray absorption layer 110 including multiple discrete chips may help to accommodate the difference between the thermal expansion coefficients of the materials of the X-ray absorption layer 110 and the electronic layer 120.
  • the electronics layer 120 as shown in Fig. 3A , Fig. 3B or Fig. 3C are mere examples.
  • the RDL (e.g., 123), the vias (e.g., 126, 126A, 126B, 129) and the transmission lines (e.g., 127) are not required for signal readout from the electronics system 121.
  • the signal readout schemes illustrated in Fig. 4A , Fig. 4B and Fig. 4C may be implemented without using the RDL, the vias or the transmission lines.
  • Signal from the detector 100 may be read out column by column.
  • signal from one pixel may be stored in a memory in the electronics system 121 associated with it; the signal may be successively shifted from one column to the next, and eventually to other processing circuitry.
  • Fig. 4A shows a top view of the RDL 123 in Fig. 3A to illustrate the positions of the vias 126 and the transmission lines 127, relative to the electric contacts 125 and the electronics system 121, according to an embodiment.
  • the electric contacts 125, the electronics system 121 and the transmission lines 127 are shown in dotted lines because they are not directly visible in this view. As shown in Fig.
  • Signal from the detector 100 may be read out pixel by pixel.
  • signal from one pixel may be stored in a memory in the electronics system 121 associated with it; the signal may be successively shifted from the electronics system 121 associated with one pixel to the electronics system 121 associated with the next pixel, and eventually to other processing circuitry.
  • Fig. 4B shows a top view of the RDL 123 in Fig. 3A to illustrate the positions of the vias 126 and the transmission lines 127, relative to the electric contacts 125 and the electronics system 121, according to an embodiment.
  • the electric contacts 125, the electronics system 121 and the transmission lines 127 are shown in dotted lines because they are not directly visible in this view.
  • Signal from the detector 100 may be read out region by region.
  • signal from one pixel may be stored in a memory in the electronics system 121 associated with it; the signal may be successively shifted from the electronics system 121 associated with one pixel to the electronics system 121 associated with the next pixelwith in the same region, and eventually to other processing circuitry.
  • Fig. 4C shows a top view of the RDL 123 in Fig. 3A to illustrate the positions of the vias 126 and the transmission lines 127, relative to the electric contacts 125 and the electronics system 121, according to an embodiment.
  • the signal may be directed to the other processing circuitry through the vias 129 in the RDL 123.
  • the electric contacts 125, the electronics system 121 and the transmission lines 127 are shown in dotted lines because they are not directly visible in this view.
  • Fig. 5C if the electronics system 121 of one pixel 534 is defective (as marked by a breakline symbol), signal readout from all pixels (e.g., 531-533) upstream to the pixel 534 in the same region may fail. For example, if the memory in the electronics system 121 of the pixel 534 is defective, any signal shifted into the defective memory from the upstream pixels may be lost.
  • the electronics system 121 may be configured to reduce the chance of or prevent losing signal from non-defective pixels upstream to a defective pixel.
  • Fig. 6A shows a function block diagram of the electronic system 121, according to an embodiment.
  • the electronics system 121 may have a redundancy in the memory of the electronics system 121.
  • the electronic system 121 may have multiplememories (e.g., 641 and 642).
  • the memories may be configured to store signal from a pixel the electronics system 121 associates with or store signal shifted from an upstream pixel.
  • the memories may be on separate and electrically parallel signal paths (e.g., 631 and 632) between an input terminal 601 and an output terminal 602 of the electronics system 121.
  • the input terminal 601 is configured to receive signal into the electronics system 121, e.g., from the pixel the electronics system 121 associates with or an upstream pixel.
  • the output terminal 602 is configured to transmit signal stored in the electronics system 121 to downstream circuitry such as a downstream pixel.
  • the electronic system 121 may have a switch (e.g., two multi-pole multi-throw switches 610 and 620) that selects one of the multiple signal paths.
  • the signal path 631 may be selected by default and the memory 641 is used by default, unless the memory 641 is defective; if the memory 641 is defective, the signal path 632 may be selected and the memory 642 used as a result. With the redundancy in the memory of electronics system 121, even if one memory among the multiple memories is defective, the electronics system 121 still functions and signal from upstream pixels can still be shifted into and out of the electronics system 121.
  • Fig. 6B shows a function block diagram of the electronic system 121, according to an embodiment.
  • the electronics system 121 may have a bypass path (e.g., 633) that connects the input terminal 601 and the output terminal 602, without a memory thereon.
  • the bypass path may be selected by the multi-pole multi-throw switches 610 and 620 when all the memories are defective. When the bypass path is selected, signal from an upstream pixel to shift directly to a downstream pixel. When the bypass path is selected, signal from the pixel the electronics system 121 associates may not be read out.
  • Fig. 6C shows a function block diagram of the electronic system 121, according to an embodiment.
  • the electronic system 121 may have only one memory 641 on the signal path 631, and a bypass path (e.g., 633) that connects the input terminal 601 and the output terminal 602, without a memory thereon.
  • the bypass path may be selected by the multi-pole multi-throw switches 610 and 620 when all the memory is defective. When the bypass path is selected, signal from an upstream pixel to shift directly to a downstream pixel. When the bypass path is selected, signal from the pixel the electronics system 121 associates may not be read out.
  • Fig. 6D schematically shows a chain of twelve electronics systems (671-682) according to the embodiment of Fig. 6B , each of the electronics systems associated with a pixel. Defective memories are marked with breakline symbols. In this example shown in Fig. 6D , despite that eight (672-675, 677, 679, 681 and 682) of the twelve electronics systems are defective, the chain is not broken (i.e., signal from pixels upstream to these twelve electronics systems 121 can still pass it).
  • one of the non-defective memory is selected, for example by the multi-pole multi-throw switches, such that the non-defective memory can still store the signals from the pixels these electronics systems associate and allow signal from upstream pixels to be shifted into and out of these electronics systems.
  • the bypass signal pass is selected, for example by the multi-pole multi-throw switches, such that signal from an upstream pixel is shifted directly to a downstream pixel.
  • the defectiveness state and the selection of the signal path in the electronics system may be represented by a code.
  • the memories of an electronics system of Fig. 6B may have four different defectiveness states: memory 641 defective and memory 642 defective, memory 641 defective but memory 642 not defective, memory 641 not defective but memory 642 defective, and memory 641 not defective and memory 642 not defective.
  • these states are represented by codes "11,” “10,” “01,” and "00.”
  • the codes "11,” “10,” “01,” and "00” can respectively represent selection of the signal paths 633, 632, 631 and 631.
  • These codes may be concatenated to represent the signal path of an entire chain of electronics systems.
  • the signal path of chain of Fig. 6D can be represented by the code "00 10 01 11 10 00 00 01 00 00.”
  • Fig. 8A schematically shows that the code representing the defectiveness state of the electronics system 121 (or the corresponding state of the switches) may be stored in the electronics system 121 itself.
  • the electronics system 121 may include a memory 810 separate from the memories (e.g., 641 and 642 in Fig. 6A and Fig. 6B ) for storing the signal.
  • the memories 810 may be a non-volatile memory. In the example of Fig. 6A and 6C , the memories 810 may have one bit or more. In the example of Fig. 6B , the memories 810 may have two bits or more.
  • Fig. 8B schematically shows that the memory for storing the code representing the defectiveness state of the electronics system 121 (or the corresponding state of the switches) may have redundancy, to guard against any failure in this memory for storing the code.
  • the memory for storing the code representing the defectiveness state of the electronics system 121 may have redundancy, to guard against any failure in this memory for storing the code.
  • Fig. 9A schematically shows that the code representing the signal path of a chain of electronics system 121 may be stored in a memory of the detector 100.
  • the memories 910 may be a non-volatile memory.
  • a controller 920 of the detector 100 may be configured to select the signal path of the chain based on the code stored in the memory 910.
  • the code representing the signal path of the chain of electronics system 121 may be used as a key to the detector 100, e.g., for controlling access to the detector 100, determining the times of use, or billing.
  • Fig. 9B schematically shows that the selection between the redundant memories for storing the codes representing the defectiveness states (or the corresponding states of the switches) in a group of electronics systems 121 may be switched collectively.
  • the selection may be stored in another memory 911.
  • the codes stored in every memory 810A (see Fig. 8B ) of the group of electronics systems 121 may be used to represent the defectiveness states, or the codes stored in every memory 810B (see Fig. 8B ) of the group of electronics systems 121 may be used to represent the defectiveness states.
  • one code representing the selection between the redundant memories may be stored in the memory 911.
  • the codes representing these selections stored in the memory 911 may be 00100011... ("0" representing 810A is selected and "1" representing 810B is selected).
  • a controller 920 of the detector 100 may be configured to select among the redundant memories (e.g., 810A and 810B) based on the code stored in the memory 911.
  • the code stored in the memory 911 may be used as a key to the detector 100, e.g., for controlling access to the detector 100, determining the times of use, or billing.
  • Fig. 10 schematically shows that the code representing the signal path of the chain of electronics system 121 may be stored in a removable dongle, which can be in a form of a memory card or memory stick. Physical presence of the dongle may be required before the detector 100 may be used. Other functions can be integrated into the dongle. For example, the dongle can serve as a license that requires periodic renewal; the dongle may have an amount of money recorded thereon to charge a fee for each use of the detector 100.
  • Fig. 11 schematically shows a system comprising the detector 100 described herein.
  • the system may be used for medical imaging such as chest X-ray radiography, abdominal X-ray radiography, etc.
  • the system comprises an X-ray source 1201.
  • X-ray emitted from the X-ray source 1201 penetrates an object 1202 (e.g., a human body part such as chest, limb, abdomen), is attenuated by different degrees by the internal structures of the object 1202 (e.g., bones, muscle, fat and organs, etc.), and is projected to the detector 100.
  • the semiconductor X-ray detector 100 forms an image by detecting the intensity distribution of the X-ray.
  • Fig. 12 schematically shows a system comprising the detector 100 described herein.
  • the system may be used for medical imaging such as dental X-ray radiography.
  • the system comprises an X-ray source 1301.
  • X-ray emitted from the X-ray source 1301 penetrates an object 1302 that is part of a mammal (e.g., human) mouth.
  • the object 1302 may include a maxilla bone, a palate bone, a tooth, the mandible, or the tongue.
  • the X-ray is attenuatedby different degrees by the different structures of the object 1302 and is projected to the detector 100.
  • the detector 100 forms an image by detecting the intensity distribution of the X-ray. Teeth absorb X-ray more than dental caries, infections, periodontal ligament.
  • the dosage of X-ray radiation received by a dental patient is typically small (around 0.150 mSv for a full mouth series).
  • Fig. 13 schematically shows a cargo scanning or non-intrusive inspection (NII) system comprising the detector 100 described herein.
  • the system may be used for inspecting and identifying goods in transportation systems such as shipping containers, vehicles, ships, luggage, etc.
  • the system comprises an X-ray source 1401.
  • X-ray emitted from the X-ray source 1401 may backscatter from an object 1402 (e.g., shipping containers, vehicles, ships, etc.) and be projected to the detector 100.
  • object 1402 e.g., shipping containers, vehicles, ships, etc.
  • Different internal structures of the object 1402 may backscatter X-ray differently.
  • the semiconductor X-ray detector 100 forms an image by detecting the intensity distribution of the backscattered X-ray and/or energies of the backscattered X-ray photons.
  • Fig. 14 schematically shows another cargo scanning or non-intrusive inspection (NII) system comprising the detector 100 described herein.
  • the system may be used for luggage screening at public transportation stations and airports.
  • the system comprises an X-ray source 1501. X-ray emitted from the X-ray source 1501 may penetrate a piece of luggage 1502, be differently attenuated by the contents of the luggage, and projected to the semiconductor X-ray detector 100.
  • the detector 100 forms an image by detecting the intensity distribution of the transmitted X-ray.
  • the system may reveal contents of luggage and identify items forbidden on public transportation, such as firearms, narcotics, edged weapons, flammables.
  • Fig. 15 schematically shows a full-body scanner system comprising the detector 100 described herein.
  • the full-body scanner system may detect objects on a person's body for security screening purposes, without physically removing clothes or making physical contact.
  • the full-body scanner system may be able to detect non-metal objects.
  • the full-body scanner system comprises an X-ray source 1601. X-ray emitted from the X-ray source 1601 may backscatter from a human 1602 being screened and objects thereon, and be projected to the detector 100. The objects and the human body may backscatter X-ray differently.
  • the semiconductor X-ray detector 100 forms an image by detecting the intensity distribution of the backscattered X-ray.
  • the detector 100 and the X-ray source 1601 may be configured to scan the human in a linear or rotational direction.
  • Fig. 16 schematically shows an X-ray computed tomography (X-ray CT) system.
  • the X-ray CT system uses computer-processed X-rays to produce tomographic images (virtual "slices") of specific areas of a scanned object.
  • the tomographic images may be used for diagnostic and therapeutic purposes in various medical disciplines, or for flaw detection, failure analysis, metrology, assembly analysis and reverse engineering.
  • the X-ray CT system comprises the detector 100 described herein and an X-ray source 1701.
  • the detector 100 and the X-ray source 1701 may be configured to rotate synchronously along one or more circular or spiral paths.
  • Fig. 17 schematically shows an electron microscope.
  • the electron microscope comprises an electron source 1801 (also called an electron gun) that is configured to emit electrons.
  • the electron source 1801 may have various emission mechanisms such as thermionic, photocathode, cold emission, or plasmas source.
  • the emitted electrons pass through an electronic optical system 1803, which may be configured to shape, accelerate, or focus the electrons.
  • the electrons then reach a sample 1802 and an image detector may form an image therefrom.
  • the electron microscope may comprise the detector 100 described herein, for performing energy-dispersive X-ray spectroscopy (EDS).
  • EDS is an analytical technique used for the elemental analysis or chemical characterization of a sample. When the electrons incident on a sample, they cause emission of characteristic X-rays from the sample.
  • the incident electrons may excite an electron in an inner shell of an atom in the sample, ejecting it from the shell while creating an electron hole where the electron was.
  • An electron from an outer, higher-energy shell then fills the hole, and the difference in energy between the higher-energy shell and the lower energy shell may be released in the form of an X-ray.
  • the number and energy of the X-rays emitted from the sample can be measured by the detector 100.
  • the semiconductor X-ray detector 100 described here may have other applications such as in an X-ray telescope, X-ray mammography, industrial X-ray defect detection, X-ray microscopy or microradiography, X-ray casting inspection, X-ray non-destructive testing, X-ray weld inspection, X-ray digital subtraction angiography, etc. It may be suitable to use this detector 100 in place of a photographic plate, a photographic film, a PSP plate, an X-ray image intensifier, a scintillator, or another semiconductor X-ray detector.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Measurement Of Radiation (AREA)
  • Apparatus For Radiation Diagnosis (AREA)

Claims (13)

  1. Appareil (100) adapté pour détecter une image, comprenant :
    une pluralité de pixels (150) configurée pour générer un signal électrique en cas d'exposition à une radiation ;
    un système électronique (121) associé à chacun des pixels, le système électronique étant conçu pour recevoir des signaux électriques transférés d'un système électronique d'un pixel en amont et pour transférer les signaux électriques à un système électronique d'un pixel en aval ;
    le système électronique comprenant une première mémoire (641) sur un premier chemin de signal (631) et une seconde mémoire (642) sur un second chemin de signal (632), les deux chemins de signal étant situés entre un terminal d'entrée (601) et un terminal de sortie (602) du système électronique ;
    chacune de la première mémoire et de la seconde mémoire étant associée à, enregistrant un signal électrique transféré du système électronique d'un pixel en amont, et
    transférant un signal électrique à un système électronique d'un pixel en aval ; et
    le système électronique comprenant un premier interrupteur (610) disposé au niveau du terminal d'entrée et un second interrupteur (620) disposé au niveau du terminal de sortie, les premiers et seconds interrupteurs étant conçus pour sélectionner un des chemins de signal,
    le premier chemin de signal étant sélectionné sauf si la première mémoire est défectueuse.
  2. Appareil selon la revendication 1, dans lequel l'appareil est conçu pour détecter une image en rayons X.
  3. Appareil selon la revendication 1, dans lequel le système électronique comprend une mémoire configurée pour enregistrer un code représentant un état de défectuosité et une sélection du chemin de signal.
  4. Appareil selon la revendication 3, dans lequel la mémoire a une mémoire redondante.
  5. Appareil selon la revendication 1, comprenant une mémoire configurée pour enregistrer des codes représentant des états de défectuosité et une sélection de chemins de signal de la pluralité de systèmes électroniques.
  6. Appareil selon la revendication 5, comprenant un contrôleur conçu pour sélectionner les chemins de signal parmi la pluralité de systèmes électroniques en fonction des codes.
  7. Appareil selon la revendication 6, dans lequel la mémoire est un dispositif enfichable amovible, l'appareil étant désactivé sauf si le dispositif enfichable amovible est présent.
  8. Procédé selon la revendication 1,
    dans lequel le système électronique comprend un chemin de dérivation qui raccorde le terminal d'entrée au terminal de sortie sans qu'il y ait une mémoire sur le chemin de dérivation ;
    les premiers et seconds interrupteurs étant configurés pour sélectionner le premier chemin de signal, le second chemin de signal ou le chemin de dérivation.
  9. Appareil (100) adapté pour détecter une image, comprenant :
    une pluralité de pixels (150) configurée pour générer un signal électrique en cas d'exposition à une radiation ;
    un système électronique (121) associé à chacun des pixels, le système électronique étant conçu pour recevoir des signaux électriques transférés d'un système électronique d'un pixel en amont et pour transférer les signaux électriques à un système électronique d'un pixel en aval ;
    le système électronique comprenant une première mémoire (641) sur un chemin de signal (631) entre un terminal d'entrée (601) et un terminal de sortie (602) du système électronique,
    la première mémoire étant configurée pour : enregistrer un signal électrique généré par le pixel auquel le système électronique est associé ; enregistrer un signal électrique transféré du système électronique d'un pixel en amont, et transmettre un signal électrique au système électronique d'un pixel en aval ;
    dans lequel le système électronique comprend un chemin de dérivation (633) qui raccorde le terminal d'entrée au terminal de sortie sans qu'il y ait une mémoire sur le chemin de dérivation ; et
    le système électronique comprenant un premier interrupteur (610) disposé au niveau du terminal d'entrée et un second interrupteur (620) disposé au niveau du terminal de sortie, les premiers et seconds interrupteurs étant conçus pour sélectionner le chemin de signal ou le chemin de dérivation, le premier chemin de signal étant sélectionné sauf si la première mémoire est défectueuse.
  10. Appareil selon la revendication 9, dans lequel l'appareil est conçu pour détecter une image en rayons X.
  11. Appareil selon la revendication 9, dans lequel le système électronique comprend une mémoire configurée pour enregistrer un code représentant un état de défectuosité et une sélection du chemin de signal ou du chemin de dérivation.
  12. Appareil selon la revendication 9, comprenant une mémoire configurée pour enregistrer des codes représentant des états de défectuosité et une sélection des chemins de signal ou des chemins de dérivation de la pluralité de systèmes électroniques.
  13. Appareil selon la revendication 12, comprenant un contrôleur conçu pour sélectionner les chemins de signal ou les chemins de dérivation parmi la pluralité de systèmes électroniques en fonction des codes.
EP16891038.8A 2016-02-26 2016-02-26 Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs Active EP3420560B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/074663 WO2017143584A1 (fr) 2016-02-26 2016-02-26 Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs

Publications (3)

Publication Number Publication Date
EP3420560A1 EP3420560A1 (fr) 2019-01-02
EP3420560A4 EP3420560A4 (fr) 2020-03-25
EP3420560B1 true EP3420560B1 (fr) 2023-05-10

Family

ID=59684963

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16891038.8A Active EP3420560B1 (fr) 2016-02-26 2016-02-26 Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs

Country Status (5)

Country Link
US (1) US11122221B2 (fr)
EP (1) EP3420560B1 (fr)
CN (1) CN108701490B (fr)
TW (1) TWI742030B (fr)
WO (1) WO2017143584A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102567134B1 (ko) * 2018-10-01 2023-08-16 삼성전자주식회사 엑스선 조사량 측정 장치, 이를 포함하는 반도체 메모리 장치 및 반도체 메모리 장치의 테스트 방법
JP7271209B2 (ja) * 2019-02-06 2023-05-11 キヤノン株式会社 放射線撮像装置、放射線撮像システムおよび放射線撮像装置の制御方法
CN114127586A (zh) * 2019-07-26 2022-03-01 深圳帧观德芯科技有限公司 带有闪烁体的辐射检测器

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4254477A (en) * 1978-10-25 1981-03-03 Mcdonnell Douglas Corporation Reconfigurable memory circuit
JPS5788446A (en) * 1980-11-20 1982-06-02 Toshiba Corp X-ray cine-stereo photographing device
JPS58152542A (ja) * 1982-03-05 1983-09-10 株式会社東芝 Ｘ線診断装置
US5063378A (en) 1989-12-22 1991-11-05 David Sarnoff Research Center, Inc. Scanned liquid crystal display with select scanner redundancy
GB9219836D0 (en) 1992-09-18 1992-10-28 Philips Electronics Uk Ltd Electronic drive circuits for active matrix devices,and a method of self-tasting and programming such circuits
CN101086898A (zh) 1999-03-19 2007-12-12 株式会社东芝 半导体存储装置
US7202894B2 (en) * 2002-06-04 2007-04-10 Micron Technology, Inc. Method and apparatus for real time identification and correction of pixel defects for image sensor arrays
KR100535636B1 (ko) * 2003-02-24 2005-12-08 매그나칩 반도체 유한회사 불량 화소 보상 기능을 갖는 이미지센서
JP2006068512A (ja) * 2004-08-06 2006-03-16 Canon Inc 撮像装置、撮像システム、撮像方法、およびコンピュータプログラム
US7852391B2 (en) * 2004-12-14 2010-12-14 Bae Systems Information And Electronic Systems Integration Inc. Substitution of defective readout circuits in imagers
JP4782524B2 (ja) * 2005-09-29 2011-09-28 株式会社東芝 半導体集積回路、設計支援ソフトウェアシステム、および、テストパターン自動生成システム
JP4847202B2 (ja) * 2006-04-27 2011-12-28 キヤノン株式会社 撮像装置及び放射線撮像システム
JP5038031B2 (ja) * 2006-07-11 2012-10-03 キヤノン株式会社 放射線撮影装置、その駆動方法及び放射線撮影システム
JP5038101B2 (ja) 2007-11-12 2012-10-03 キヤノン株式会社 放射線撮像装置、その駆動方法及びプログラム
WO2013018003A1 (fr) * 2011-07-29 2013-02-07 Koninklijke Philips Electronics N.V. Visualisation précise de mouvement de tissu mou sur des rayons x
KR101932664B1 (ko) * 2012-08-27 2018-12-26 삼성전자 주식회사 리던던시 셀을 포함하는 반도체 메모리 장치 및 시스템
US20130284927A1 (en) * 2012-04-10 2013-10-31 Ud Holdings, Llc Infrared detector having at least one switch positioned therein for modulation and/or bypass
KR20140000477A (ko) * 2012-06-22 2014-01-03 삼성디스플레이 주식회사 엑스레이 검출기, 엑스레이 검출기를 포함하는 엑스레이 촬영 시스템 및 엑스레이 검출기 구동 방법
US10312374B2 (en) 2012-10-01 2019-06-04 Sharp Kabushiki Kaisha Circuit board and display device
JP2015535348A (ja) 2012-10-30 2015-12-10 カリフォルニア インスティチュート オブ テクノロジー フーリエ・タイコグラフィー撮像システム、装置、及び方法
JP5816316B2 (ja) * 2013-03-29 2015-11-18 富士フイルム株式会社 放射線画像検出装置およびその作動方法、並びに放射線撮影装置
US20140361189A1 (en) * 2013-06-05 2014-12-11 Canon Kabushiki Kaisha Radiation imaging system
KR101534098B1 (ko) * 2013-09-13 2015-07-07 삼성전자주식회사 Ｃｔ 장치 및 이를 이용한 엑스선 제어 방법
KR101684448B1 (ko) * 2014-01-07 2016-12-08 삼성전자주식회사 방사선 디텍터, 그에 따른 단층 촬영 장치, 및 x 선 촬영 장치
US9445027B2 (en) 2014-02-20 2016-09-13 Semiconductor Components Industries, Llc Image sensors with column memory repair circuitry
US20150288907A1 (en) * 2014-04-03 2015-10-08 Raytheon Company Method and system for managing defects in focal plane arrays using redundant components
WO2015170220A1 (fr) 2014-05-09 2015-11-12 Semiconductor Energy Laboratory Co., Ltd. Dispositif de mémoire et dispositif électronique
JP6308018B2 (ja) 2014-05-22 2018-04-11 コニカミノルタ株式会社 放射線画像撮影装置
JP3193542U (ja) * 2014-07-28 2014-10-09 株式会社島津製作所 Ｘ線検査装置

Also Published As

Publication number Publication date
EP3420560A1 (fr) 2019-01-02
CN108701490A (zh) 2018-10-23
US11122221B2 (en) 2021-09-14
TW201740136A (zh) 2017-11-16
TWI742030B (zh) 2021-10-11
US20200280686A1 (en) 2020-09-03
EP3420560A4 (fr) 2020-03-25
WO2017143584A1 (fr) 2017-08-31
CN108701490B (zh) 2022-07-12

Similar Documents

Publication Publication Date Title
US11009614B2 (en) Semiconductor X-ray detector
US11224388B2 (en) Image sensors having X-ray detectors
US11063082B2 (en) Methods of making semiconductor X-ray detector
US10353086B2 (en) Semiconductor X-ray detector capable of dark current correction
US10007007B2 (en) Methods for making an X-ray detector
US11353604B2 (en) Packaging methods of semiconductor X-ray detectors
US11901244B2 (en) Methods of making a radiation detector
EP3420560B1 (fr) Procédés de sortie de données depuis un détecteur d'image à semi-conducteurs

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20180823

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.

A4 Supplementary search report drawn up and despatched

Effective date: 20200226

RIC1 Information provided on ipc code assigned before grant

Ipc: G01T 1/24 20060101ALI20200220BHEP

Ipc: G11C 29/00 20060101ALI20200220BHEP

Ipc: G11C 29/24 20060101AFI20200220BHEP

Ipc: H04N 5/374 20110101ALI20200220BHEP

Ipc: H04N 5/3745 20110101ALI20200220BHEP

Ipc: H04N 5/367 20110101ALI20200220BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20210907

RAP3 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

RIC1 Information provided on ipc code assigned before grant

Ipc: H04N 5/32 19680901ALI20230106BHEP

Ipc: H04N 25/771 20230101ALI20230106BHEP

Ipc: G11C 29/00 19680901ALI20230106BHEP

Ipc: G01T 1/24 19680901ALI20230106BHEP

Ipc: G11C 29/24 20060101AFI20230106BHEP

INTG Intention to grant announced

Effective date: 20230215

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1567537

Country of ref document: AT

Kind code of ref document: T

Effective date: 20230515

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602016079430

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

P01 Opt-out of the competence of the unified patent court (upc) registered

Effective date: 20230522

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20230510

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1567537

Country of ref document: AT

Kind code of ref document: T

Effective date: 20230510

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230911

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230810

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230910

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230811

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602016079430

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20240213

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240213

Year of fee payment: 9

Ref country code: GB

Payment date: 20240221

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20230510