EP3405974A1 - Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat - Google Patents

Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat

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Publication number
EP3405974A1
EP3405974A1 EP17701653.2A EP17701653A EP3405974A1 EP 3405974 A1 EP3405974 A1 EP 3405974A1 EP 17701653 A EP17701653 A EP 17701653A EP 3405974 A1 EP3405974 A1 EP 3405974A1
Authority
EP
European Patent Office
Prior art keywords
chamber
copper
substrate
layer
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP17701653.2A
Other languages
German (de)
English (en)
French (fr)
Inventor
Julien VITIELLO
Fabien PIALLAT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kobus SAS
Original Assignee
Kobus SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kobus SAS filed Critical Kobus SAS
Publication of EP3405974A1 publication Critical patent/EP3405974A1/fr
Withdrawn legal-status Critical Current

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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/4401Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
    • C23C16/4405Cleaning of reactor or parts inside the reactor by using reactive gases
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523Pulsed gas flow or change of composition over time
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
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    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7687Thin films associated with contacts of capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Definitions

  • the present invention relates to a method of manufacturing an interconnection comprising a via extending through a substrate.
  • TSV through vias
  • the manufacture of such an interconnection typically comprises:
  • the titanium or tantalum nitride layer has a barrier function to prevent diffusion of copper into the substrate.
  • the deposited layers must be consistent and of good quality.
  • “compliant layer” is meant a layer whose thickness measured in a direction perpendicular to a surface on which it is deposited is constant. In other words, the surface of said layer is parallel to the surface on which it is deposited.
  • PVD Physical vapor deposition
  • CMP chemical mechanical polishing
  • “Chemical Vapor Deposition” provides better compliance than the PVD process but it has the disadvantage of introducing contaminants (including carbon) which reduce the quality of the layer formed.
  • An object of the invention is to design a method of manufacturing an interconnection comprising a via extending through a substrate that avoids the aforementioned problems and which allows in particular to improve the compliance of the deposited layers and to avoid the deposition of an excess thickness of material to be removed from the main surface of the substrate.
  • Another object of the invention is also to provide interconnections whose reliability over time is increased.
  • an interconnection comprising a via extending through a substrate, comprising successively:
  • step (a) the substrate is arranged in a first deposition chamber and in that said step (a) comprises injecting a precursor of titanium or tantalum in the gas phase into the deposition chamber by a first injection route according to a first pulse sequence and the injection of a nitrogen-based reactive gas into the deposition chamber by a second injection route distinct from the first injection path according to a second pulse sequence, the first pulse sequence and the second pulse sequence being out of phase.
  • the deposition of the titanium nitride or tantalum layer allows a faster chemical reaction but also a better compliance than the conventional CVD process. Moreover, it promotes the reaction on the surface of the substrate and thus limits any contamination of said surface due to parasitic reactions.
  • width is meant the smallest dimension of the hole in the plane formed by the main surface of the substrate.
  • hole designates an opening of any shape practiced in a main surface of the substrate, and includes for example a trench having a length greater than its width, or even but not limited to a circular orifice (in the latter case, the width corresponds to the diameter of the hole).
  • step (c) of filling the hole is carried out by electroplating copper
  • the thickness of the titanium nitride or tantalum nitride layer deposited in step (a) is less than or equal to 100 nm;
  • the thickness of the copper layer deposited in step (b) is between 50 and 300 nm;
  • step (b) the deposition of the copper layer in step (b) is carried out in a second deposition chamber different from the first chamber;
  • step (b) is carried out by chemical vapor deposition
  • the first and second deposition chambers are connected separately in leaktight manner to an intermediate chamber and between steps (a) and (b), the substrate is transferred from the first chamber to the second chamber by the intermediate vacuum chamber; air;
  • - via has a form factor greater than or equal to 5: 1;
  • the method comprises, after the filling of the hole, the removal of at least a portion of the thickness of the substrate opposite the main surface on which the titanium nitride or tantalum nitride layer and the copper layer have have been deposited so as to expose the interior of the via so as to make said via via;
  • the method comprises cleaning the chamber in which the titanium nitride or tantalum nitride layer has been deposited to remove said titanium nitride or tantalum nitride deposited on an inner wall of said bedroom, said cleaning being performed with a reactive gas composed of fluorine and activated by a plasma source;
  • the method comprises cleaning the chamber in which the copper layer has been deposited to remove said copper deposited on an inner wall of said chamber, said cleaning comprising the following steps:
  • step (ii) injection, according to a sequence of pulses, of chemical species adapted to volatilize said oxidized copper, said step (ii) beginning after the start of step (i).
  • Another object relates to a device for implementing the aforementioned method.
  • Said device is characterized in that it comprises:
  • a first sealed deposition chamber connected to a source of a titanium or tantalum precursor by a first injection route and to a source of a nitrogen-based reactive gas by a second injection route distinct from the first way
  • a second sealed deposition chamber connected to a source of copper and
  • FIGS. 1A to 1E illustrate various steps of the method according to one embodiment of the invention
  • Figure 2 is a block diagram of a device for implementing the method.
  • FIGS. 1A to 1E illustrate successive steps in the formation of an interconnection.
  • a substrate 1 is provided in which at least one hole 10 has been formed from a main surface 1A of the substrate.
  • the substrate may be any substrate suitable for producing electronic circuits.
  • the substrate may be solid (that is to say made of a single material) or composite (that is to say consisting of a stack of different materials).
  • the substrate may be a silicon substrate.
  • the hole is not through, that is to say that its depth is less than the thickness of the substrate.
  • the hole has a form factor greater than 5: 1, preferably greater than 10: 1.
  • the invention can be implemented regardless of the shape factor of the hole.
  • a conformal layer 1 1 of titanium nitride (TiN) or tantalum nitride (TaN) is deposited on the main surface 1A of the substrate, on the side wall 10A of the hole and on the bottom 10B of the hole.
  • This deposit is made by chemical vapor deposition implemented in a pulsed manner.
  • the substrate is introduced into a first deposition chamber (reference 100 in FIG. 2) comprising two distinct injection paths: a first channel makes it possible to connect the chamber to a source of a titanium or tantalum precursor and second channel connects the chamber to a source of a nitrogen-based reactive gas.
  • a first channel makes it possible to connect the chamber to a source of a titanium or tantalum precursor
  • second channel connects the chamber to a source of a nitrogen-based reactive gas.
  • nitrogen-based is meant that said reactive gas contains mainly nitrogen but may optionally contain other species, such as hydrogen.
  • the first injection path comprises a first plurality of channels through which the titanium or tantalum precursor is injected into the deposition chamber and the second injection path comprises a second plurality of channels through which the nitrogen-based reactive gas is injected into the deposition chamber, all of said channels opening into the deposition chamber facing the surface of the substrate.
  • the substrate is placed in the deposition chamber on a substrate holder possibly comprising a heating system of the substrate at a temperature advantageous for the deposition.
  • the deposition comprises injecting said titanium or tantalum precursor in the gas phase into the deposition chamber by the first injection route according to a first pulse sequence and injecting the nitrogen-based reactive gas into the chamber. deposition by the second injection path distinct from the first injection path according to a second pulse sequence, the first pulse sequence and the second pulse sequence being out of phase.
  • pulse sequence is meant at least one pulse per sequence. This process is called pulsed CVD. Such a method has been described, for applications and materials different from those referred to in the present invention, in WO 2015/140261.
  • the duration of a pulse of the first sequence of pulses is between 0.02 s and 5 s;
  • the delay between two pulses of the first sequence of pulses is between 0.5 s and 10 s;
  • the duration of a pulse of the second pulse sequence is between
  • the delay between two pulses of the second sequence of pulses is between 0.5 s and 10 s.
  • the duration of a pulse of the first sequence of pulses, respectively of the second sequence of pulses, is between 0.02 s and 5 s;
  • the delay between two pulses of the first sequence of pulses, respectively of the second sequence of pulses, is between 0.02 s and 10 s.
  • the duration of a pulse of the first sequence of pulses or the second sequence of pulses is between 0.02 s and 1 s;
  • the delay between two pulses of the first sequence of pulses, respectively of the second sequence of pulses, is between 0.02 s and 1 s.
  • the duration of a pulse of the first sequence of pulses or the second sequence of pulses is between 1 s and 5 s;
  • the delay between two pulses of the first sequence of pulses, respectively of the second sequence of pulses, is between 1 s and 10 s.
  • the travel time of the species injected into the chamber is defined by the time required for said species to travel the distance between the output of the respective injection path and the free surface of the substrate.
  • the injection of the different species is carried out in a sequence adapted so that the reaction between said species takes place essentially on the free surface of the substrate.
  • the heating system of the substrate carrier heats the substrate to a temperature higher than the temperature at which the species are injected into the chamber. As the rate of reaction between the species is increasing with temperature, the reaction rate is thus higher on the free surface of the substrate.
  • the first pulse sequence and the second pulse sequence are out of phase, ie during the deposition process there are moments during which only the titanium or tantalum precursor is injected into the deposition chamber and times during which only the nitrogen-based reactive gas is injected into the reaction chamber. Eventually, there may also be instants during which a simultaneous injection is used and / or times during which no injection takes place.
  • the pressure in the deposition chamber is greater than a predetermined value throughout the duration of the process unlike atomic layer deposition (ALD) techniques.
  • ALD deposition involves the injection of only one type of species at a time, and requires a complete purge of the chamber before the other type of species is injected.
  • the pressure in the deposition chamber is greater than 500 mTorr, preferably greater than 1 Torr.
  • this method it is possible to maintain the advantage of a deposition rate of a layer on the surface of a substrate comparable to the technique of vapor deposition (CVD). Moreover, the compliance of the deposition of the layer is greatly improved over the conventional vapor deposition technique. In addition, this method promotes a reaction between the tantalum or titanium precursor and the nitrogen-based reactive gas on the surface of the substrate, thus limiting the parasitic reactions and a contamination that may degrade the properties of the layer formed on the substrate. surface of the substrate.
  • a conformal layer 1 1 of titanium nitride or tantalum nitride is deposited, said layer advantageously having a thickness less than or equal to
  • the layer performs a copper diffusion barrier function used to fill the hole to the substrate.
  • a conformal layer 12 of copper is then formed on the layer 1 1, a conformal layer 12 of copper, a thickness generally between 50 and 300 nm.
  • the substrate 1 covered with the layer 1 1 is advantageously moved to a second deposition chamber (reference 200 in Figure 2) separate from the first chamber and isolated vis-à-vis thereof.
  • said displacement is carried out without venting the substrate, which avoids any contamination or oxidation.
  • contamination or oxidation of the deposited layers is likely to reduce the adhesion of said layers and to promote electromigration of copper during operation of a device comprising the via.
  • the deposition of the layer 12 can be implemented by any appropriate technique.
  • said deposit is made by chemical vapor deposition, pulsed or not.
  • the hole 10 is filled with copper.
  • said filling can be performed by continuing the copper deposition performed in the previous step.
  • the filling the hole can be made by electrodeposition, this technique being faster and less expensive than the chemical vapor deposition.
  • At least a portion of the tantalum nitride or titanium and copper layers are removed from the main surface 1A of the substrate by chemical mechanical polishing.
  • FIGS. 1D and 1E can optionally be inverted.
  • the chamber 100 and / or the chamber 200 can be cleaned after the deposition step, once the substrate has been removed from the chamber.
  • said cleaning is advantageously carried out by injecting into the chamber a reactive gas composed of fluorine and activating said gas by a plasma source located in situ or at a distance from the chamber.
  • said cleaning comprises the following steps:
  • step (ii) injection, according to a sequence of pulses, of chemical species adapted to volatilize said oxidized copper, said step (ii) starting after the start of step (i) and taking place either after the end of the step (i) during part of step (i).
  • the first pulse of step (ii) is implemented after the beginning of step (i), whether said step is completed or not.
  • Step (i) can be performed by injecting oxidizing species comprising at least one of the following species: oxygen, ozone, nitrous oxide. Said oxidizing species can be injected continuously during the entire cleaning process.
  • the chemical species used to volatilize oxidized copper include hfacH (hexafluoroacetylacetone).
  • said chemical species adapted to volatilize the oxidized metal deposit could also react with the copper deposit, and thus passivate the exposed surface of said deposit.
  • This passivation reaction of the metal deposition 2 is a parasitic reaction which limits or blocks any oxidation reaction of said deposition by the oxidizing species.
  • the chemical species adapted to volatilize the oxidized copper deposit are injected, in step (ii), according to a sequence of pulses.
  • the chamber 200 can be maintained at a temperature between 20 and 250 ° C so as to maintain gaseous form the chemical species adapted to volatilize the copper deposit.
  • the temperature of the chamber 200 is maintained at a temperature between 20 and 150 ° C, more preferably between 20 and 100 ° C.
  • the pressure in the chamber 200 is maintained between 0.1 and 10 Torr, or, preferably, between 1 and 5 Torr.
  • the duration of the injection pulse (s) of the chemical species adapted to volatilize the oxidized metal deposit is between 0.02 s and 5 s, and the delay between two consecutive pulses (if any) is between 0.02 s and 10 s;
  • the duration of the injection pulse (s) of the chemical species adapted to volatilize the oxidized metal deposit is between 0.02 s and 1 s, and the delay between two consecutive pulses (if any) is between 0.02 s and 1 s;
  • the duration of the injection pulse (s) of the chemical species adapted to volatilize the oxidized metal deposit is between 1 s and 5 s, and the delay between two consecutive pulses (if any) is between 1 s and 10 s .
  • the pulse duration of the pulse sequence is adjusted so that the oxidized copper layer is not fully volatilized.
  • the remaining portion of the oxidized copper layer forms a barrier to the passivation of the metal deposit by the chemical species injected in step (ii).
  • the passivation reaction is then blocked.
  • the chemical species are injected in sub-stoichiometric amount relative to the amount of the metal deposit oxidized between said two successive pulses.
  • the aforementioned sub-stoichiometric amount is determinable by knowing both the amount of the oxidized copper deposit in step (i) between two pulses of the pulse sequence of step (ii), and the mechanism of volatilization reaction of said oxidized copper deposit with the chemical species.
  • the mode of injection of the chemical species adapted to volatilize the oxidized copper deposit thus has many advantages.
  • the first advantage is to provide an effective cleaning process. Indeed, the parasitic reaction comprising the passivation of copper deposition by the chemical species injected is thus neutralized. The neutralization of said parasitic reaction avoids having to open the chamber 200, and to use a decontamination process thereof.
  • the second advantage is to control the amount of chemical species injected in step (ii), and thus reduces the cost of the cleaning process.
  • This cleaning makes it possible to minimize the risk of deposition of particles on the surface of the substrate 1 and thus to improve the quality of the deposited layers. It also allows to increase the number of plates that can be deposited before a chemical bath cleaning of the room.
  • the titanium nitride or tantalum and copper layers are not only formed with good compliance in a reduced time (typically of the order of 2 minutes for a 40 nm layer) but also that they have a better quality which minimizes the risk of subsequent electromigration of copper.
  • the interconnection is more reliable and, in a longer period, than the existing interconnections.
  • said device comprises a first sealed and vacuumable deposition chamber 100 connected by a first injection route to a source of a titanium or tantalum precursor (not shown) and by a second injection path to a source of a nitrogen-based reactive gas (not shown), and a second sealed deposition chamber 200 connected to a copper source (not shown).
  • the device further comprises an inlet / outlet lock 400 through which the substrates on which the tantalum nitride or titanium and copper layers are to be formed and the substrates on which said layers have been formed are removed.
  • Said inlet / outlet airlock 400 opens into a sealed intermediate chamber 300, which is able to communicate separately with the first deposition chamber 100 and with second deposition chamber 200.
  • a system for handling and transporting the substrate (not shown) is arranged inside the device to allow the displacement of the substrate from one chamber to another.
  • the atmosphere in the chamber 300 is controlled, so as to avoid contamination of a substrate flowing between the different chambers.
  • the substrate moves between the intermediate chamber 300, the deposition chamber 100 and the deposition chamber 200, said chambers being fluidly isolated from one another during the implementation of the steps of the method.
  • the substrate avoids any mutual contamination of the rooms may generate deposits difficult to clean on the internal walls of the rooms.

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EP17701653.2A 2016-01-19 2017-01-16 Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat Withdrawn EP3405974A1 (fr)

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FR1650408A FR3046878B1 (fr) 2016-01-19 2016-01-19 Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat
PCT/EP2017/050761 WO2017125336A1 (fr) 2016-01-19 2017-01-16 Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat

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US5186718A (en) * 1989-05-19 1993-02-16 Applied Materials, Inc. Staged-vacuum wafer processing system and method
US6284052B2 (en) * 1998-08-19 2001-09-04 Sharp Laboratories Of America, Inc. In-situ method of cleaning a metal-organic chemical vapor deposition chamber
US8696875B2 (en) * 1999-10-08 2014-04-15 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
KR100363088B1 (ko) * 2000-04-20 2002-12-02 삼성전자 주식회사 원자층 증착방법을 이용한 장벽 금속막의 제조방법
WO2003008663A1 (en) * 2001-07-16 2003-01-30 Applied Materials, Inc. Formation of titanium nitride films using a cyclical deposition process
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US6784096B2 (en) * 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
US7241686B2 (en) * 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA
KR100667561B1 (ko) * 2005-02-18 2007-01-11 주식회사 아이피에스 박막 증착 방법
US20080242078A1 (en) * 2007-03-30 2008-10-02 Asm Nutool, Inc. Process of filling deep vias for 3-d integration of substrates
WO2009042713A1 (en) * 2007-09-28 2009-04-02 Applied Materials, Inc. Vapor deposition of tungsten materials
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
US8531033B2 (en) * 2009-09-07 2013-09-10 Advanced Interconnect Materials, Llc Contact plug structure, semiconductor device, and method for forming contact plug
US8907457B2 (en) * 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
KR20120031811A (ko) * 2010-09-27 2012-04-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
FR3018825B1 (fr) 2014-03-21 2017-09-01 Altatech Semiconductor Procede de depot en phase gazeuse

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US20210202314A1 (en) 2021-07-01
KR20180118627A (ko) 2018-10-31
WO2017125336A1 (fr) 2017-07-27
TW201733066A (zh) 2017-09-16
FR3046878B1 (fr) 2018-05-18
US11114340B2 (en) 2021-09-07
CN108475660A (zh) 2018-08-31

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