EP3319075B1 - Kompensierung des spannungsverlusts in stromversorgungsleitungen für aktivmatrixanzeigen - Google Patents

Kompensierung des spannungsverlusts in stromversorgungsleitungen für aktivmatrixanzeigen Download PDF

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Publication number
EP3319075B1
EP3319075B1 EP16197152.8A EP16197152A EP3319075B1 EP 3319075 B1 EP3319075 B1 EP 3319075B1 EP 16197152 A EP16197152 A EP 16197152A EP 3319075 B1 EP3319075 B1 EP 3319075B1
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EP
European Patent Office
Prior art keywords
pixel
calibration
power supply
pixels
voltage drop
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EP16197152.8A
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English (en)
French (fr)
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EP3319075A1 (de
Inventor
Jan Genoe
Wim Dehaene
Florian DE ROOSE
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Priority to EP16197152.8A priority Critical patent/EP3319075B1/de
Priority to TW106134225A priority patent/TWI734842B/zh
Priority to CN201780067935.3A priority patent/CN109906477B/zh
Priority to KR1020197013472A priority patent/KR102521163B1/ko
Priority to PCT/EP2017/077988 priority patent/WO2018083135A1/en
Publication of EP3319075A1 publication Critical patent/EP3319075A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the invention relates to the field of active-matrix LED panels. More specifically it relates to methods for driving and compensating non-uniformities of digitally driven AMLED or AMOLED displays.
  • ALED Active-Matrix Light-Emitting Diode
  • OLED organic Light-Emitting Diode
  • TFTs organic Light-Emitting Diode
  • VDS source-drain voltage
  • Document US2007/0164937 A1 discloses a display device including a central controller and a memory.
  • the controller can control switching and driving transistors.
  • Each pixel of the display device also includes a detecting transistor, which can be also activated by the control unit for extracting current flowing through the electrode of the light emitting layer of the pixel.
  • the controller can detect the current from the pixel and calibrate the voltage accordingly, to correct brightness.
  • AMOLED active-matrix OLED
  • AMLED active-matrix LED
  • the present invention provides driving circuitry for an active-matrix display comprising a plurality of pixels each comprising a light emitting element and a drive transistor connected in series with the light emitting element in each pixel.
  • the driving circuitry comprises:
  • correction can be performed dynamically, correcting differences in the output due to differences in transistor characteristics, differences in light emitting element characteristics, temperature changes, degradation in time, taking into account the voltage at the power supply line and ground line of several rows together.
  • the drive transistor is adapted to provide a same current flowing through every pixel upon pixel activation.
  • the reference current source is connected to a feedback loop.
  • the current source can be made highly accurate and can be implemented in an integrated circuit, which can be easily distributed over several data driver chips in an active-matrix panel. It is an additional advantage that the internally generated voltage may be used as a reference, so the impedance matching is independent of the silicon chip.
  • the calibration means comprise an interpolation unit and ground voltage drop multiplication unit, both adapted, via a sum unit, to provide voltage regulation to the data driver module of the active-matrix panel. Voltage regulation and compensation can thus be provided through data drivers already present in active-matrix displays, with no need of extra current sources, DAC, etc., which saves wafer area and allows obtaining displays with high resolution. It is an additional advantage that variations of impedance due to grounding can be taken into account.
  • the voltage source and calibration means may be connectable to a first side of the at least one power supply line.
  • the at least one power supply line may further comprise a second side connectable to the voltage source via the driving mode switch.
  • the voltage source may comprise a DC/DC converter. This way, a highly efficient voltage source can be obtained, without need of ADCs or DACs and their additional voltage drops
  • the present invention provides an active-matrix display comprising an array of pixels logically organized in rows and columns, each pixel comprising at least one light emitting element, and a driving circuitry according to any of embodiments of the first aspect of the present invention.
  • the pixels may comprise a 2T1C structure.
  • Such implementation has a simple layout and is easily controlled, with few components, which reduces losses.
  • the array may be divided in two sets of pixels, each set comprising driving circuitry according to any of the embodiments of the first aspect. It is an advantage of embodiments of the present invention that calibration of multiple pixels on different rows can be done in parallel, by duplicating the number of reference current I ref sources, mode select switches and comparators.
  • the present invention provides a method of driving an active-matrix display according to an embodiment of the second aspect of the present invention. The method comprises
  • OLED displays are displays comprising an array of light-emitting diodes in which the emissive electroluminescent layer is a film of organic compound which emits light in response to an electric current.
  • OLED displays can either use passive-matrix (PMOLED) or active-matrix (AMOLED) addressing schemes.
  • PMOLED passive-matrix
  • AMOLED active-matrix
  • the present invention relates to AMOLED displays.
  • the corresponding addressing scheme makes use of a thin-film transistor backplane to switch each individual OLED pixel on or off.
  • AMOLED displays allow for higher resolution and larger display sizes than PMOLED displays.
  • the present invention is not limited to AMOLED displays, but in a broader concept relates to active-matrix displays. Any type of active-matrix displays may use the concepts of embodiments of the present invention, although AMOLED displays are particularly advantageous in view of the current switching speeds of their pixel elements. It is advantageous if the pixel elements of the active-matrix displays can switch faster, as this allows to obtain higher frame rates, hence fewer flickering images.
  • An active-matrix display e.g. an AMLED or AMOLED display, according to embodiments of the present invention comprises a plurality of pixels, each comprising a light emitting element, e.g. a light-emitting diode (LED), or an organic LED (OLED) element.
  • the light emitting elements are arranged in an array, and are logically organized in rows and columns.
  • the terms “horizontal” and “vertical” (related to the terms “row” and “column”, respectively) are used to provide a co-ordinate system and for ease of explanation only. They do not need to, but may, refer to an actual physical direction of the device.
  • the terms “column” and “row” are used to describe sets of array elements which are linked together.
  • the linking can be in the form of a Cartesian array of rows and columns; however, the present invention is not limited thereto.
  • columns and rows can be easily interchanged and it is intended in this disclosure that these terms be interchangeable.
  • non-Cartesian arrays may be constructed and are included within the scope of the present invention. Accordingly the terms “row” and “column” should be interpreted widely. To facilitate this wide interpretation, the description and claims refer to logically organized in rows and columns. By this is meant that sets of pixel elements are linked together in a topological linear intersecting manner; however, that the physical or topographical arrangement need not be so.
  • the rows may be circles and the columns radii of these circles and the circles and radii are described in this invention as "logically organized" rows and columns.
  • specific names of the various lines e.g. select line and data line, are intended to be generic names used to facilitate the explanation and understanding, and to refer to a particular function. This specific choice of words is not intended to in any way limit the invention.
  • the present invention relates to a driving circuit for an active-matrix LED (AMLED) or OLED (AMOLED) display panel, allowing uniform pixel powering and thus reducing display degradation and non-uniformities. It also relates to an AMLED and AMOLED display panels, comprising driving circuitry according to embodiments of the present invention. It also relates to a method for digital driving of an AM(O)LED displays including power supply line voltage drop compensation.
  • AMLED active-matrix LED
  • AMOLED OLED
  • voltage mode digital driving is used for driving the display panels. Compensation schemes to substantially reduce or eliminate non-uniformities and degradation of both frontplane and backplane are provided, based on impedance matching at block level.
  • the array of pixels can be calibrated in various ways when using the voltage mode digital driving. Essentially, there is a feedback which somehow either checks or programs the current flowing in the individual pixels.
  • the present invention encompasses several mechanisms which are all based on this concept. As a core principle, the current in the pixel is determined by changing the pixel impedance, as also described in WO 2014/080014 . The techniques described in this document can be used for the present concept as well. The impedance matching is done to eliminate variations in the TFTs and OLEDs and to compensate for the voltage drop over the lines.
  • a first scheme comprises monitoring the current during a calibration cycle, with a current sensor monitoring the current consumed by a single pixel. This would require activating one pixel per channel (row or column, determined by the direction of the power lines, which define the voltage drop) each calibration cycle and tuning the driving transistor, until the pixel current reaches a predetermined reference value. This would result in tuning a single pixel per current sensor during the calibration cycle. This is not the preferred scheme, because measurement data would be obtained for a lot of currents and in the digital driving methods, only a single current is needed.
  • a second, preferred, scheme comprises sending a current during a calibration cycle, and adapting a tunable resistor until the effective supply voltage V DD for which the system is designed is reached, thus taking into account the number of pixels per row and its resistive model.
  • the calibration refresh time depends on the number of pixels per calibration channel (i.e. a row or a plurality of rows taken together) and the time between pixel calibration. The time between the calibration of different pixels depends on whether the calibration is done only at startup or during the display runtime.
  • any unused time slots within the digital driving scheme can be used for the calibration.
  • a duty cycle as described in page 15, line 10 to page 16, line 15 of WO 2014 068017 shows that a first time slot of the first sub-frame is 0, and the rest of time slots will be either 1 (if the most significant bit is 1) or 0 (if the most significant bit is 0).
  • the digital signal is 11111111, the first time slot will be 0 in this type of duty cycle, as it is seen in page 16, lines 23 to 28 of the same document.
  • Such unused time slot can be used for calibration according to embodiments of the present invention.
  • a method for digital driving and calibrating of an AM(O)LED display is provided.
  • Embodiments of the present method can provide compensation of shift of the (O)LED characteristics (time-dependent degradation, degradation due to use) and of the TFT characteristics, which are in general mostly dominated by bias stress (either voltage or illumination bias), thus obtaining a good picture quality for an AM(O)LED display.
  • bias stress either voltage or illumination bias
  • the current in every pixel needs to be matched to the digital value of the pixel to be displayed.
  • a calibration value is obtained for each pixel, for example by using a reference current I ref and measuring and regulating the voltage drop across the pixel, or by directly measuring the current through the pixel by means of a current sensor.
  • Each of the calibration values required for obtaining a calibrated pixel are stored in a calibration memory.
  • the AM(O)LED display is actually used, a data stream representing an image to be displayed is obtained, and introduced in a data driver for driving the active-matrix in a compensated way. The AM(O)LED display is then driven, taking into account the previously determined calibration values for each pixel. Obtaining the calibration data and performing calibration and voltage corrections can be made with the same hardware block.
  • FIG. 4 shows an exemplary system outline for a digitally driven active-matrix display according to embodiments of the present invention. It comprises image interface hardware 107, first data driver hardware 401 and optionally second data driver hardware 402 (for example data drivers which may be all or a part thereof implemented in chips), a first set of dedicated line drivers 403 and a optionally a second set of dedicated line drivers 404 (e.g. embedded line drivers) which comprise the "select" lines for selecting pixels in the array, a first "voltage distribution and voltage drop calibration" block, or "power distribution” block 109 and an optional second voltage distribution unit or block 108 according to embodiments of the second aspect of the present invention, and a pixel backplane 405.
  • the voltage distribution unit e.g.
  • the voltage distribution unit together with voltage compensation unit may also form a compact unit 109, for example an integrated unit. In an alternative embodiment, only the unit 109 is present.
  • the actual frontplane containing the pixels including the LEDs or OLEDs is not illustrated in FIG. 4 .
  • image input under the form of digital data representing an image to be displayed, reaches the image interface hardware 107 through an input 406, e.g. wires or a bus.
  • control and data signals are sent to the data driver hardware 401 and optionally 402, and control signals are sent to the first and optionally second set of dedicated line-drivers 403, 404.
  • signals may come back from the voltage drop calibration block 109 towards the image interface hardware 107 as a feedback.
  • FIG. 5 shows two possible embodiments of data driver wiring.
  • first data drivers 401 and second data drivers 402 are present on both sides of the display, respectively, for each controlling a subset of the pixels.
  • each data driver may control a set of data lines 501, 502 that may run until the middle of the display.
  • only data drivers 401 are present on one side of the display and its corresponding data lines 511 run over the whole display, until the other side thereof.
  • a part of the data driver block e.g. a multiplexer
  • Select wiring may present options similar to the ones of the data wires (data lines). They may for example run perpendicular to the data wires of FIG. 5 (this example not limiting the present invention).
  • the select wires (select lines) may run from the dedicated line-drivers 403, 404 on both sides of the display up to the middle of the display, or may run from line drivers 403 on one side of the display up to the other side thereof, in which case only one set of dedicated line drivers 403 would be needed.
  • the active-matrix display further comprises driving circuitry comprising on the one hand a set 102 powering voltage lines, which may run parallel to the select lines in some embodiments of the present invention, depending on design, or in any other suitable way, and on the other hand the voltage distribution and voltage drop calibration unit 109 and optionally the second voltage distribution unit 108.
  • power supply lines comprise both the VDD and GND connections for each pixel of the array.
  • FIG. 1 shows two examples for driving circuitry.
  • the upper circuit 100 presents a voltage source 101 connected to both sides of a set of power supply lines 102 for powering the LEDs of a display.
  • the power source is only connected to one side of the panel.
  • this connection is provided by a switch, i.e., driving mode switch or switches 103, 104, i.e., transistors, for select (enabling or disabling) driving of the panel.
  • the display panel can be driven with a voltage source, and this makes the introduction of a DAC in each row unnecessary, reducing the number of components and saving space in the display, thus improving design scaling.
  • the display is not limited by the DAC bit resolution (which usually needs to be bigger than the number of pixels being steered).
  • the drivers can be made simple, lowering the cost.
  • Using a voltage source and avoiding the use of DAC brings the additional advantage that additional voltage drops from connections are reduced or eliminated.
  • the voltage source 101 can be made with high efficiency (with for example a DC/DC converter). Therefore, a driving circuit comprising a voltage source is advantageously energy saving.
  • the "driving mode” switch or switches 103, 104 are turned on and the power source VDD is connected on both sides of the power supply lines 102, and turned off when not active.
  • the "driving mode” is off and the “calibration mode” switch 105 is active, a unity current I ref is driven through the power supply line, e.g. with a current source 106.
  • the lower drawing 110 of FIG. 1 shows a double driving circuit configuration, in which there are two sets of "driving mode” switches 103, 113 and “calibration mode” switches 105, 115, and two reference current sources 106, 116. They may form two integrated units 109, 119 connected to each side of the panel. This configuration may divide the rows, and each set can drive a subset of the pixels in the panel 112, e.g. each half of the pixels. The calibration and powering can be parallelized, in this configuration.
  • the present invention relates to a driving circuit for an active-matrix display, such as an AMLED or AMOLED display panel.
  • the driving circuit comprises a set 102 of power supply lines (e.g. wires, buses, other electronic pathways) for powering a group of pixels, which may be arranged as rows, each group of pixels being connected to a separate power supply line of the set 102.
  • power supply lines e.g. wires, buses, other electronic pathways
  • the pixels are arranged in rows and columns, all pixels on a row are connected to a same power supply line, and pixels of different rows are connected to different power supply lines.
  • a set 102 of supply lines is provided such that there is one power supply line for each row of pixels in the array.
  • the power supply lines comprise both the lines connected to the source VDD and lines connected to ground GND.
  • a voltage source VDD is used to supply the panel.
  • the voltage source VDD can be connected to or disconnected from both sides of the set 102 of power supply lines, via switches 103, 104, 113.
  • a signal labeled “driving mode select” is active, closing the switches 103, 104, and the power source VDD is connected on both sides of the set 102 of power supply lines.
  • driving mode select is not active, the power source VDD is disconnected from both sides of the set 102 of power supply lines. Due to the fact that the display can be powered with a voltage source, despite the fact a current source is needed, there is no need to include current mode Digital-to-Analog converters (DACs) for all the rows.
  • DACs Digital-to-Analog converters
  • a further advantage of using a voltage supply is the elimination of the voltage drop within the current DAC.
  • the voltage source can be made with high efficiency (with for example a DCDC convertor). In the current DAC, a predetermined amount of voltage drop will be required in order for the DAC to operate, and this is lost power. Therefore, the use of a voltage source as in accordance with embodiments of the present invention is a better solution from a power perspective.
  • a reference current source is provided at one side of the set 102 of power supply lines. This is used for calibration, as explained in more detail below.
  • a voltage is measured at the same side of the power supply line where the current is injected, and this measured voltage is sent to a comparator unit where it is compared with a set of reference voltages V ref(i) , with i going from 1 to p, p being the number of reference voltages having been predefined for the calibration. The result of this comparison is provided to the digital logic in the image interface hardware 107.
  • pixels may comprise a relatively simple configuration such as 2T1C (a circuit with 2 transistors and 1 capacitor), as shown in FIG. 6 .
  • the present invention is not limited to 2T1C configurations, and other configurations (e.g. 4T2C, 5T2C, 6T2C) may also be applied for keeping the TFT voltage threshold shift very low, thus reducing variations in pixel luminance.
  • other configurations e.g. 4T2C, 5T2C, 6T2C
  • the present invention can be applied to p-type as well as n-type transistors and to driving circuitry comprising any type of back-plane, e.g. comprising for instance hydrogenated amorphous Si (a-Si :H), polycrystalline silicon , organic-semiconductors, (amorphous) indiumgallium zinc oxide(a-IGZO, IGZO) TFT, or others.
  • back-plane e.g. comprising for instance hydrogenated amorphous Si (a-Si :H), polycrystalline silicon , organic-semiconductors, (amorphous) indiumgallium zinc oxide(a-IGZO, IGZO) TFT, or others.
  • FIG. 6 shows two basic configurations for pixel structures of an AM(O)LED display according to embodiments of the present invention.
  • the illustrated embodiments are 2T1C (2 transistor, 1 capacitor) configurations, but any other suitable configuration can be applied.
  • the pixel structures comprise a LED or an OLED 601 connected in series with a drive transistor M1.
  • the (O)LED 601 can either be coupled between ground line 603 coupled to ground GND and transistor M1, as shown in the left-hand part of FIG. 6 , or between the power supply line 604 coupled to the power supply V DD and the transistor M1, as in the right-hand part of FIG. 6 .
  • the sum of the voltages over the (O)LED and transistor M1 results in the voltage over the pixel.
  • the transistor M1 acts as a switch for powering the (O)LED 601 with power from the power supply line 604.
  • the select transistor M2 connects a data line 606 with the gate of the drive transistor M1.
  • the gate of the select transistor M2 is connected to a select line 607, which is shown as running parallel to the power supply line 604 and the ground line 603.
  • the select lines 607 run perpendicular to the data lines 606.
  • the capacitor C1 is connected between gate and source of drive transistor M1.
  • a plurality of such pixels as represented in FIG. 6 may be logically arranged in rows and columns. Pixels arranged in a same column may be connected to a same data line 606, and pixels arranged in a same row may be connected to a same select line 607.
  • the voltages, currents, impedances and related parameters used for calibration in each pixel will have different values depending on the position of each pixel in the row, because the resistance between the power source and each pixel depends on its position in the row due to contact leads, contacts between pixels, etc.
  • Embodiments of the present invention provide impedance matching per pixel, during normal use of the display, i.e. during displaying of an image.
  • the voltage over each pixel is measured while a reference current is introduced in that pixel according to predetermined calibration schemes, as will be set out below, and then the current is controlled in each pixel via impedance matching to eliminate variations in the active-matrix and (O)LEDs and to compensate for voltage drop over the rows.
  • Impedance matching is realized for each pixel by tuning a variable impedance connected in series with the LED or OLED of the pixel.
  • the driving transistor of each pixel is used as a variable resistor.
  • FIG. 7 shows that each pixel in a row is subject to a voltage drop which depends on the position (n) of the pixel in the row of N pixels, because the resistance in series between the pixel and the connection to the power source increases with increasing distance to the power source.
  • FIG. 7 Two possible configurations of a pixel row connected to the power supply line 604 are shown in FIG. 7 , together with the resistances between pixels, in a resistive model.
  • the upper implementation of FIG. 7 illustrates a resistive model for a row of pixels driven from both sides, while the lower implementation illustrates a resistive model of a row of pixels driven from a single side.
  • power supply line resistance R1 between neighboring pixels
  • ground line resistance R2 between neighboring pixels
  • R1+R2 Rref.
  • R S1 + R S 2 M
  • R ref M
  • the upper implementation 700 in FIG. 7 comprises power supply lines contacted from both sides, thus the pixels at the extremities of the row are connected to the power source VDD.
  • the resistive voltage drop for this case is illustrated in FIG. 8.
  • FIG. 8 illustrates 3 cases: graph 201 - no (O)LED is on, graph 202 - a typical distribution of (O)LEDs along the row are on, and graph 203 - all (O)LEDs along the row are on. It can be seen from these graphs that the power drop on the power supply lines increases with increasing number of pixels being switched on between the connection point of the power supply line to the power source, and the pixel at location n under consideration.
  • the resistive voltage drop for the case the power lines are contacted from both sides may be calculated as herein below.
  • a current source e.g. the current source 106 of FIG. 1
  • the resistive voltage drop over the pixel at location n in the row of N pixels is obtained from the injected reference current I ref .
  • the current flowing in the row is firstly calculated at the pixel in position n, as a function of the current at the contact I 0 and the binary code b i (b sub i) that defines when a pixel is ON (and hence draws the current I ref ).
  • the algorithm hence uses a stream of N bits from a row of the image data. This stream of N bits is b N ... b i+1 b i ... b 1 .
  • the resistance of the wiring between two pixels R ref defines the voltage drop ⁇ V n between two pixels.
  • the voltage drop is thus expressed in units of R ref I ref .
  • This number M is dependent on the geometry of the layout of the external wiring to the display. When there are more than 1000 pixels in a row, the precision with which the voltage drop is calculated is less than a microvolt. Due to this high precision, some of the least significant bits can be disregarded at the final outcome.
  • This number A N may be calculated one row ahead of the actual driving during operation. Hence the number A N for row x+1 is calculated during driving of row x.
  • the expression for the voltage drop can be separated into two terms A N and B n , each of which can be calculated iteratively.
  • This hardware block may be present in the image interface hardware 107. It may comprise one counter and two adders.
  • This loop defines the different values of B n .
  • FIG. 8 illustrates how, in accordance with embodiments of the present invention, the power line voltage drop reference levels V ref(1..N) are defined.
  • the maximum (graph 203) and minimum (graph 201) power line voltage drops are known (they are calculated exactly from the values of the resistances and the imposed reference current I ref ), and in between a set of equally spaced voltage drop reference levels 801 that can occur during operation are defined (the number of levels is defined by the required accuracy or maximum cost of the system).
  • the levels corresponding to the most significant bits (MSBs) of the Bn numbers calculated are defined. For each voltage drop level defined in 801 and for each pixel, a calibration will be done during the calibration phase of the display.
  • Bn is a binary number representative of the voltage drop for a bit string in a pixel n, and for example three MSBs are chosen. This choice determines the number of voltage drop reference levels, which, for the three MSBs, corresponds to eight voltage drop reference levels 801.
  • the value "000” corresponds to no resistive drop (case of minimum drop 201), and the value "111" corresponds to the maximal resistive drop, only obtained in the middle of the maximum drop diagram 203.
  • a calibration voltage value for each pixel and for each of the eight levels is stored.
  • the actual Bn numbers comprise a string longer than their three MSBs.
  • the real value used for calibration is a linear interpolation between the relevant pixel n and the next pixel n+1.
  • the rest of the string (the least significant bits) can be used to improve interpolation.
  • FIG. 10 shows the calibration method for one pixel, similar to method the method disclosed on page 13, line 23 to page 14, line 10 of WO2014/080014 .
  • the display is thus driven row by row (activation of select transistor M2 by line drivers 403, 402, and flowing the reference current I ref through the power supply line).
  • the reference current I ref is only applied in a pixel row through one single active pixel, keeping the rest of pixels of the row inactive. Because I ref is injected through both the (O)LED and the transistor M1, the total voltage is the sum of the voltage over the (O)LED, V*, and the voltage over the transistor, between V* and the voltage over the pixel V L at that I ref .
  • the voltage at the gate of the drive transistor M1 of the active pixel is set at its lowest relevant value for the switch formed by the drive transistor M1 to be ON, and, as a consequence, the voltage V L over the pixel is higher than the supply voltage V DD .
  • Increasing the voltage at the gate of the transistor results in a lower V L .
  • the gate voltage is increased until the voltage over the pixel is the same as the supply voltage.
  • V DD usually taking place in the pixel at the beginning of the power supply line, i.e. directly connected to the power source.
  • This value is stored in the calibration memory of the pixel as the minimum power line voltage drop.
  • the process can be described as a gate voltage sweep during calibration, shown by the arrow 1001 in FIG. 10 . This is performed for each pixel until all power supply line voltage drop reference levels are obtained and stored in the calibration memory. Hence, for each pixel the delta for n voltage drop calibration levels are stored in the calibration memory of the pixel.
  • One of the differences with the method of WO2014/080014 is that the pixel is now driven by a voltage source, and the calibration values can be used for voltage regulation directly on the data line.
  • Calibration of multiple pixels on different rows in parallel can be done by duplicating the number of reference current I ref sources, mode select switches and comparators as illustrated in FIG. 1 .
  • FIG. 9 shows how the actual data driver is addressed.
  • This hardware block may be present inside the image interface hardware 107. It has two input data streams: the power supply line voltage drop 901 (B N .... B i+1 B i .... B 1 ) and the digital data bit stream 902 (b N .... b i+1 b i .... b 1 ) representing the image to be displayed.
  • a stream of data driver voltage values 903 D N .... D i+1 D i .... D 1 is obtained and introduced in the data driver module 904 of the active-matrix panel display. For each pixel, the most significant bit (MSB) of the power supply line voltage drop values are sent to the calibration memory 905.
  • MSB most significant bit
  • the calibration value for the voltage drop of pixel n and the calibration value for the voltage drop of the next pixel n+1 are provided to an interpolation unit 906.
  • the least significant bits (LSB) of the same voltage drop of pixel n are also provided to the interpolation unit 906 and enables to do an accurate interpolation between both calibrations.
  • the influence of the ground line voltage drop can advantageously be taken into account in the calculation of the voltage drop, for example, to drive the gate of the transistor M1 (see FIG. 6 ) which controls the powering of the LED.
  • the ratio between ground line voltage drop and the total power supply line voltage drop is known (usually it is half), so the ground line voltage drop is obtained in the multiplication unit 907 by the multiplication with this known ratio. This voltage needs to be added in the sum unit 908 to the voltage driven to the gate of M1.
  • the output multiplexer 909 selects the output, which is the calculated gate voltage when the bit is '1', and 0 when the bit is '0'.
  • a counter 910 may be included for regulating the calibration process and/or storing the values in the calibration memory.
  • the counter 910 is at the beginning of the calibration procedure set at a value corresponding to the lowest possible gate voltage, and when the obtained pixel voltage is higher than the first reference voltage, the corresponding counter value is stored in the first calibration value address.
  • As the calibration value is also applied to the MSB input of the calibration lookup table 905, its value is also obtained at the output.
  • the LSB bits are set to zero (thus disabling interpolation), and the digital data stream 902 is set to '1', thus turning each pixel on, giving the requested data driver voltage at the output. This increases until the requested reference voltage is obtained. This is subsequently done for all reference voltages.
  • the calibration per pixel shown in FIG. 10 can be done for each pixel in a recursive manner, including storing the values in the memory 905 (e.g. lookup table) of the calculation unit of FIG. 9 .
  • the relationship between the power supply line voltage drop and the required gate voltage has a 1/(ax) behavior, with "a" being larger than the maximal power supply line resistive drop as illustrated in FIG. 8 .
  • the data driver can be advantageously implemented with 1/(a-x) behavior, thus reducing the required number of calibration levels and increasing the accuracy.
  • This correction can be implemented occasionally (e.g. periodically) by tweaking the gamma response curve that can be implemented in some existing display data drivers.
  • the regulation of the gamma curve is known in the art, for example it can be implemented as interpolation of values that can be uploaded by software, and it can be readily integrated within embodiments of the present invention.
  • the power line voltage drop along the row of N pixels, for an exemplary sequence of driven pixels on and off, is shown in graph 202 in FIG. 8 , and the upper leftmost drawing 200 of FIG. 2 , for a row of pixels being driven from both sides.
  • the pixel number n is a number between 1 and the total number of pixels on the row, being N.
  • the algorithm may use a stream of N bits from a row of the image data as defined in the prior art, for example in document WO2014068017A1 . This stream of N bits is b N .... b i+1 b i .... b 1 . These bits may represent pixel intensity data representing the image.
  • connections between the pixels, between pixels and power source, and between pixels and ground GND are conductive connections, typically metallic connections and leads, which present electric resistance and generate a voltage drop along the rows, which voltage drop depends on the position of the pixel. Pixels close to the center of the display (e.g. farther away from the connection with the power source) will show, on average, higher voltage drop than pixels close to the source.
  • FIG. 2 shows the voltage drop profiles for the minimum drop 201 (all (O)LEDs are off), a typical drop 202 (few (O) LEDs are on, others off), and maximum drop 203 (all (O) LEDs are on) for three cases:
  • the corresponding resistive model is illustrated in the lower implementation 710 at the bottom of FIG. 7 .
  • the resistive voltage drop may be calculated in a similar process as before.
  • the current flowing in the row is firstly calculated as before, at position of pixel n as a function of the current at the contact I 0 and the binary codes b i that define when a pixel is on and hence draws the current I ref :
  • the voltage drop ⁇ V n between two pixels is defined with the resistance R ref of the wiring between two pixels.
  • R ref resistance of the wiring between two pixels.
  • the unit that calculates B n for such embodiment comprises only a counter and two adders (which may be duplicated for parallelization in a double configuration, as illustrated in the lower drawing 110 of FIG. 1 ). As such these are very compact hardware implementations.
  • the iteration is equivalent to the previous example of iteration for B n .
  • bit stream of data comprising a bit b per pixel in a row of N pixels, is used to calculate the parameter A N . Then both the bit stream and the parameter A N are used to calculate a voltage drop per pixel (thus, N voltage drops) for that bit of data.
  • the voltage can be swept and the current can be directly measured by means of a current sensor, using the configuration of a current source and an ADC (as it is shown in FIG. 3 ).
  • the current sensor would monitor the current through a single pixel during a calibration cycle, and the drive transistor acting as a tunable resistor can be used to tune the current until the pixel current is the same as the reference pixel current.
  • FIG. 3 shows an example comprising a variable voltage source 301, so the voltage can be swept during calibration, and current sensors 302, 303 for measuring the current.
  • This implementation is compatible with driving circuits with double connection to the voltage source (upper drawing 100 of FIG. 1 ) or double driving circuits (lower drawing 110 of FIG. 1 ).
  • the power is connected to only one side of the display, and the driving circuit comprises a single current sensor 302 and single ADC 304.
  • FIG. 11 shows a practical implementation of a digitally driven OLED display. Power and ground are connected from one side, which is the worst-case scenario for calibration methods. When power and ground are connected from both sides, calibration is expected to be much better. Additionally, the simulation has been performed using a blue OLED in order to have the worst case for the simulation. Calibration is expected to be better for other OLEDs (red, green) which require lower current.
  • the resistivity of the power supply line is an important factor in calibration quality.
  • Power supply line is simulated at 4 ⁇ /pixel (4 ohms/pixel) (15.4 k ⁇ for the complete power supply line of 3840 pixels). With a lower power supply line resistivity, better calibration is expected.
  • the chosen values for V T and V OLED are significantly spread. Thus, it would be valid for a transistor with a V T of +0.4 and also a transistor of a V T of -0.4V. The same holds for the OLED spread. If these spreads were lower, variation would be lower, so again, the calibration is expected to be better in actual applications.
  • the display of FIG. 11 and the pixel of FIG. 6 have been used for the simulation.
  • the calibration of marked display line 1101 was simulated, as it is representative for all lines., considering the display fully on, with the following characteristics:
  • the results for pixel current vs. pixel position are compared in an uncalibrated display ( FIG. 12 ), a calibration (level 1) without the resistivity of the power supply line correction in the calibration method ( FIG. 13 ) and full calibration (level 2), including the resistivity of the power supply line correction in the calibration method ( FIG. 14 ).
  • the graphs show the pixel current as a function of the pixel position along the row of the display according to FIG. 11 , the first pixel 1102 of the row 1101 at the 0 position (closest to the power connector) and the last pixel 1103 of the row (in the middle of the display) at the position 1920, which is the largest distance from the power connector.
  • Absolute pixel current is shown in full line, and the relative error with respect to the reference current (predetermined as 0.15 ⁇ A) is shown in dashed line in FIG. 12 to FIG. 14 .
  • the largest difference in light output between two neighboring pixels can be as big as 50%. This is far too high, indicating that calibration is strictly needed. Additionally, it is noticed that the effect of voltage drop along the power supply line is visible, but the current is dominated by local spread.
  • the SPICE simulation shows high uniformity of display after taking into account the resistive drops of the power supply lines.
  • the spread on the transistors and OLEDs is equal to the spread in the former simulations.
  • the obtained pixel output is very uniform and does not depend on the position on the display.
  • the pixels in the middle of the display (position close to 1920) have an intensity almost equal to the pixels at the edge of the display.
  • the global spread on the pixel current is less than the least significant bit (LSB) when using an 8-bit per color coding. The largest difference between two pixels corresponds to 1.5 times LSB
  • FIG. 15 shows a comparison of the three methods (thin line 1501 for the uncalibrated result, thick line 1502 for the level 1 calibration, dashed line 1503 for the level 2 calibration), for the same row of the display.
  • the upper graph shows the absolute pixel current, and in the lower graph the relative error, with respect to the reference current (0.15 ⁇ A).
  • the encircled area 1510 closest to the power connection shows the initial variations.
  • resistive drop is not taken into account (level 1 calibration)
  • the initial variations present in the non-calibrated current mostly disappear, and a uniform current is obtained. However the current drops linearly towards the center of the display (the end of the row).
  • embodiments of the method of the present invention manage to reduce pixel variations and intensity gradients from edge to end of row or edge to middle of display. This is advantageous, for example, in cases where there are more than 640 pixels on a 4Q/pixel powerline of the display, as the method can take the resistive drops into account.

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Claims (8)

  1. Treiberschaltungen (100, 110) für eine Aktiv-Matrix-Anzeige, die eine Vielzahl von Pixeln umfasst, welche jeweils ein lichtemittierendes Element (601, 611) und einen mit dem lichtemittierenden Element (601, 611) in jedem Pixel in Reihe geschalteten Treibertransistor (M1) umfassen, wobei die Treiberschaltungen umfassen:
    - ein Datentreibermodul (904), das dazu ausgelegt ist, einen digitalen Datenbitstrom (903) zu empfangen, der ein von der Aktiv-Matrix-Anzeige anzuzeigendes Bild darstellt,
    - eine oder mehrere Leistungsversorgungsleitungen (102, 604), um die Vielzahl von Pixeln mit Leistung zu versorgen,
    - einen Satz dedizierter Leitungstreiber (403, 404), die dazu ausgelegt sind, Auswahlleitungen anzusteuern, um Pixel in der Aktiv-Matrix-Anzeige auszuwählen,
    und wobei die Leitungstreiber (403, 404) und das Datentreibermodul (401, 402, 904) dazu geeignet sind, einen Referenzstrom durch ein einziges aktives Pixel fließen zu lassen, während der Rest der Pixel der Leistungsversorgungsleitung (102, 604) inaktiv gehalten wird;
    - einen Treibermodusschalter (103, 104) und eine Spannungsquelle (101), die über den Treibermodusschalter (103, 104) mit der einen oder den mehreren Leistungsversorgungsleitungen (102, 604) verbunden werden kann,
    - ein Kalibrierungsmittel zum Kompensieren von Leistungsabfall über der einen oder den mehreren Leistungsversorgungsleitungen,
    wobei das Kalibrierungsmittel umfasst:
    - ein erstes Mittel, das dazu ausgelegt ist, einen Referenzstrom durch die eine oder die mehreren Leistungsversorgungsleitungen (102, 604) und durch jedes Pixel fließen zu lassen, wobei das erste Mittel einen Kalibrierungsmodusschalter (105, 115) und eine Referenzstromquelle (106, 116) umfasst, wobei die Referenzstromquelle (106, 116) über den Kalibrierungsmodusschalter (105, 115) mit der einen oder den mehreren Leistungsversorgungsleitungen (102, 604) verbunden ist;
    - ein zweites Mittel, das dazu ausgelegt ist, einen Spannungsabfall (201, 202, 203) über jedem Pixel zu bestimmen, diesen mit einer vorbestimmten Referenzspannung für dieses Pixel zu vergleichen, und auf Basis des Vergleichs ein N-Bit binäres Datensignal des Spannungsabfalls (901, (BN....Bi+1 Bi.... B1)) auszugeben;
    - ein drittes Mittel, umfassend:
    eine Kalibrierungs-Nachschlagetabelle (905), die dazu ausgelegt ist, das höchstwertige Bit (MSB) des N-Bit binären Spannungsabfall-Datensignals (901, (BN....Bi+1, Bi....B1)) zu empfangen, eine Interpolationseinheit (906), die dazu ausgelegt ist, einen Ausgang der Kalibrierungs-Nachschlagetabelle (905) und die niedrigstwertigen Bits (LSB) des N-Bit binären Spannungsabfall-Datensignals zu empfangen, eine Multiplikationseinheit (907), die dazu ausgelegt ist, das N-Bit binäre Spannungsabfall-Datensignal mit einem bekannten Verhältnis zu multiplizieren,
    eine Summiereinheit (908), die dazu ausgelegt ist, den Ausgang der Interpolationseinheit (906) und der Multiplikationseinheit (907) zu summieren, einen Ausgangsmultiplexer (909), der dazu ausgelegt ist, auf Basis eines digitalen Datenbitstroms (902, (bN.... bi+1 bi.... b1)), der das Eingangsbild darstellt, zwischen dem Ausgang der Summiereinheit (908) und dem Wert 0 zu wählen, wobei der Ausgang des Ausgangsmultiplexers (903) mit dem Eingang des Datentreibermoduls (904) verbunden ist.
  2. Treiberschaltungen nach Anspruch 1, wobei der Treibertransistor (M1) dazu geeignet ist, ein und denselben Strom bereitzustellen, der bei Pixelaktivierung durch jedes Pixel fließt.
  3. Treiberschaltungen nach einem der vorstehenden Ansprüche, wobei die Referenzstromquelle (106, 116) mit einer Rückkopplungsschleife verbunden ist.
  4. Treiberschaltungen nach einem der vorstehenden Ansprüche, wobei die Spannungsquelle (101) und die Kalibrierungsmittel mit einer ersten Seite der mindestens einen Leistungsversorgungsleitung (102) verbunden werden können, wobei die mindestens eine Leistungsversorgungsleitung (102) weiter eine zweite Seite umfasst, die über den Treibermodusschalter (103, 104) mit der Spannungsquelle (101) verbunden werden kann.
  5. Aktiv-Matrix-Anzeige, die eine Anordnung von Pixeln umfasst, welche logisch in Zeilen und Spalten organisiert sind, wobei jedes Pixel mindestens ein lichtemittierendes Element (601, 611) umfasst, wobei die Aktiv-Matrix-Anzeige weiter Treiberschaltungen (100, 110) nach einem der vorstehenden Ansprüche umfasst.
  6. Aktiv-Matrix-Anzeige nach Anspruch 5, wobei die Pixel eine 2T1C-Struktur umfassen.
  7. Aktiv-Matrix-Anzeige nach einem der Ansprüche 5 oder 6, wobei die Anordnung in zwei Pixelsätze unterteilt ist, wobei jeder Satz Treiberschaltungen (100, 110) nach einem der Ansprüche 1 bis 4 umfasst.
  8. Verfahren zum Ansteuern einer Aktiv-Matrix-Anzeige nach einem der Ansprüche 5 bis 7, wobei das Verfahren umfasst
    Fließenlassen eines Referenzstroms durch eine Leistungsversorgungsleitung (102, 604) und durch ein einzelnes Pixel einer Zeile von Pixeln, die mit der Leistungsversorgungsleitung (102, 604) der Anordnung verbunden sind, wobei das Fließenlassen eines Referenzstroms das Aktivieren der Kalibrierung durch Aktivieren eines Kalibrierungsmodusschalters (105, 115) und damit das Verbinden einer Referenzstromquelle (106, 116) mit einer Leistungsversorgungsleitung (102, 604) umfasst, und wobei das Fließenlassen eines Stroms durch ein einzelnes Pixel das Senden von Steuersignalen an Leitungstreiber (403, 404) und ein Datentreibermodul (401, 402, 904) umfasst, um den Referenzstrom durch ein einziges aktives Pixel fließen zu lassen, während der Rest der Pixel der Leistungsversorgungsleitung (102, 604) inaktiv gehalten wird,
    Bestimmen eines Spannungsabfalls (201, 202, 203) über dem Pixel, Vergleichen desselben mit einer vorbestimmten Referenzspannung (801) für dieses Pixel, und Ausgeben eines N-Bit binären Spannungsabfall-Datensignals auf Basis des Vergleichs (901, (BN....Bi+1 Bi.... B1)),
    Empfangen des höchstwertigen Bits (MSB) des N-Bit binären Spannungsabfall-Datensignals (901, (BN....Bi+1, Bi.... B1)) an einer Kalibrierungs-Nachschlagetabelle (905),
    Ausgeben eines Kalibrierungswerts für den Spannungsabfall eines Pixels und eines Kalibrierungswerts für den Spannungsabfall eines nächsten Pixels aus der Kalibrierungs-Nachschlagetabelle (905) an eine Interpolationseinheit (906),
    Interpolieren des Ausgangs der Kalibrierungs-Nachschlagetabelle (905) und der niedrigstwertigen Bits (LSB) des N-Bit binären Spannungsabfall-Datensignals unter Verwendung einer Interpolationseinheit (906), Multiplizieren des N-Bit binären Spannungsabfall-Datensignals mit einem bekannten Verhältnis unter Verwendung einer Multiplikationseinheit (907),
    Summieren des Ausgangs der Interpolationseinheit (906) und des Ausgangs der Multiplikationseinheit (907) unter Verwendung einer Summiereinheit (908),
    Auswählen zwischen dem Ausgang der Summiereinheit (908) und dem Wert 0 auf Basis eines digitalen Datenbitstroms (902, (bN....bi+1 bi.... b1)), der das Eingangsbild darstellt, unter Verwendung eines Ausgangsmultiplexers (909), und
    Einleiten des Ausgangs des Ausgangsmultiplexers (903), der einen ein von der Aktiv-Matrix-Anzeige anzuzeigendes Bild darstellenden digitalen Datenbitstrom (903) umfasst, in das Datentreibermodul (904).
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KR20190076984A (ko) 2019-07-02
KR102521163B1 (ko) 2023-04-13
CN109906477A (zh) 2019-06-18
EP3319075A1 (de) 2018-05-09
TWI734842B (zh) 2021-08-01
CN109906477B (zh) 2022-06-14
TW201818392A (zh) 2018-05-16

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