EP3276653A4 - Halbleiterbauelement - Google Patents
Halbleiterbauelement Download PDFInfo
- Publication number
- EP3276653A4 EP3276653A4 EP15886418.1A EP15886418A EP3276653A4 EP 3276653 A4 EP3276653 A4 EP 3276653A4 EP 15886418 A EP15886418 A EP 15886418A EP 3276653 A4 EP3276653 A4 EP 3276653A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/059514 WO2016151866A1 (ja) | 2015-03-26 | 2015-03-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3276653A1 EP3276653A1 (de) | 2018-01-31 |
EP3276653A4 true EP3276653A4 (de) | 2018-11-21 |
Family
ID=56979060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP15886418.1A Pending EP3276653A4 (de) | 2015-03-26 | 2015-03-26 | Halbleiterbauelement |
Country Status (7)
Country | Link |
---|---|
US (2) | US10424575B2 (de) |
EP (1) | EP3276653A4 (de) |
JP (1) | JPWO2016151866A1 (de) |
KR (1) | KR20170127401A (de) |
CN (2) | CN106716625A (de) |
TW (1) | TW201705376A (de) |
WO (1) | WO2016151866A1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10424575B2 (en) * | 2015-03-26 | 2019-09-24 | Renesas Electronics Corporation | Semiconductor device |
JP6849927B2 (ja) * | 2016-03-28 | 2021-03-31 | 株式会社ソシオネクスト | 半導体集積回路装置 |
TWI691050B (zh) * | 2018-07-31 | 2020-04-11 | 日商東芝記憶體股份有限公司 | 半導體記憶裝置 |
JP7163250B2 (ja) | 2019-06-26 | 2022-10-31 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JPWO2021153169A1 (de) * | 2020-01-27 | 2021-08-05 | ||
CN111965523B (zh) * | 2020-08-14 | 2023-05-09 | 上海兆芯集成电路有限公司 | 芯片测试方法 |
US11943939B2 (en) * | 2021-01-04 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit device and method |
US11877445B2 (en) | 2021-01-15 | 2024-01-16 | Micron Technology, Inc. | Integrated assemblies and semiconductor memory devices |
US11594536B2 (en) * | 2021-03-10 | 2023-02-28 | Micron Technology, Inc. | Integrated assemblies and semiconductor memory devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006310467A (ja) * | 2005-04-27 | 2006-11-09 | Renesas Technology Corp | 半導体記憶装置 |
US20080197419A1 (en) * | 2007-02-15 | 2008-08-21 | Jhon-Jhy Liaw | Cell structure for dual port SRAM |
US20130181297A1 (en) * | 2012-01-12 | 2013-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM Cells and Arrays |
US20130258759A1 (en) * | 2012-03-30 | 2013-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for SRAM Cell Structure |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11111860A (ja) | 1997-10-06 | 1999-04-23 | Mitsubishi Electric Corp | 半導体装置 |
JP3159191B2 (ja) * | 1998-12-09 | 2001-04-23 | 日本電気株式会社 | 半導体装置 |
JP2004040042A (ja) * | 2002-07-08 | 2004-02-05 | Fujitsu Ltd | 半導体記憶装置 |
JP3920804B2 (ja) | 2003-04-04 | 2007-05-30 | 松下電器産業株式会社 | 半導体記憶装置 |
KR100615085B1 (ko) * | 2004-01-12 | 2006-08-22 | 삼성전자주식회사 | 노드 콘택 구조체들, 이를 채택하는 반도체소자들, 이를채택하는 에스램 셀들 및 이를 제조하는 방법들 |
JP4997969B2 (ja) | 2004-06-04 | 2012-08-15 | 日本電気株式会社 | 半導体装置およびその製造方法 |
WO2010050094A1 (ja) | 2008-10-30 | 2010-05-06 | パナソニック株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
JP5705053B2 (ja) | 2011-07-26 | 2015-04-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8830732B2 (en) * | 2012-11-30 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cell comprising FinFETs |
JP6034764B2 (ja) | 2013-08-05 | 2016-11-30 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
KR20160040577A (ko) | 2013-08-06 | 2016-04-14 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 집적 회로 장치 |
US10424575B2 (en) * | 2015-03-26 | 2019-09-24 | Renesas Electronics Corporation | Semiconductor device |
-
2015
- 2015-03-26 US US15/512,933 patent/US10424575B2/en active Active
- 2015-03-26 CN CN201580048810.7A patent/CN106716625A/zh active Pending
- 2015-03-26 EP EP15886418.1A patent/EP3276653A4/de active Pending
- 2015-03-26 CN CN202210392184.5A patent/CN114784007A/zh active Pending
- 2015-03-26 JP JP2017507302A patent/JPWO2016151866A1/ja active Pending
- 2015-03-26 KR KR1020177008370A patent/KR20170127401A/ko unknown
- 2015-03-26 WO PCT/JP2015/059514 patent/WO2016151866A1/ja active Application Filing
- 2015-12-22 TW TW104143214A patent/TW201705376A/zh unknown
-
2019
- 2019-07-31 US US16/528,177 patent/US10811405B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006310467A (ja) * | 2005-04-27 | 2006-11-09 | Renesas Technology Corp | 半導体記憶装置 |
US20080197419A1 (en) * | 2007-02-15 | 2008-08-21 | Jhon-Jhy Liaw | Cell structure for dual port SRAM |
US20130181297A1 (en) * | 2012-01-12 | 2013-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM Cells and Arrays |
US20130258759A1 (en) * | 2012-03-30 | 2013-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for SRAM Cell Structure |
Non-Patent Citations (1)
Title |
---|
See also references of WO2016151866A1 * |
Also Published As
Publication number | Publication date |
---|---|
US10811405B2 (en) | 2020-10-20 |
JPWO2016151866A1 (ja) | 2017-06-08 |
CN106716625A (zh) | 2017-05-24 |
EP3276653A1 (de) | 2018-01-31 |
US10424575B2 (en) | 2019-09-24 |
US20190355712A1 (en) | 2019-11-21 |
WO2016151866A1 (ja) | 2016-09-29 |
CN114784007A (zh) | 2022-07-22 |
US20170301664A1 (en) | 2017-10-19 |
TW201705376A (zh) | 2017-02-01 |
KR20170127401A (ko) | 2017-11-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20170328 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20181018 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 27/11 20060101ALI20181012BHEP Ipc: G11C 11/419 20060101ALI20181012BHEP Ipc: G11C 11/418 20060101ALI20181012BHEP Ipc: H01L 21/8244 20060101AFI20181012BHEP |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |
|
17Q | First examination report despatched |
Effective date: 20210430 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: EXAMINATION IS IN PROGRESS |