EP3201949A1 - Transistor à effet de champ avec contact de drain mixte optimisé et procédé de fabrication - Google Patents
Transistor à effet de champ avec contact de drain mixte optimisé et procédé de fabricationInfo
- Publication number
- EP3201949A1 EP3201949A1 EP15774593.6A EP15774593A EP3201949A1 EP 3201949 A1 EP3201949 A1 EP 3201949A1 EP 15774593 A EP15774593 A EP 15774593A EP 3201949 A1 EP3201949 A1 EP 3201949A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- contact
- elementary
- drain
- schottky
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Definitions
- FIELD OF THE INVENTION Field of the invention is that of the field effect components and in particular that of the transistors whose fields of application are both those of the microwave frequencies and those of the transistor. power electronics.
- the present invention is more specifically focused on producing the contacts and access resistance of the drain contact of a field effect component while facilitating the production of components in a collective manner and which may have different characteristics, and in particular in the case of components with submicron grid sizes.
- the field effect transistors contact a semiconductor rod (s) using three contacts:
- a gate corresponding to a contact which may be of Schottky type (metal-semiconductor) or a junction of a semiconductor of the opposite type to that of the semiconductor in which the carriers propagate;
- Figure 1 shows the block diagram of a field effect transistor.
- the conventional solution is to use two ohmic contacts of DC drain and CS source subjected to a voltage Vds, to inject and collect the carriers schematized by the current Ids, whose flow is controlled by the voltage Vgs carried at the gate BOY WUT.
- the ohmic contacts are differentiated from the so-called Schottky contacts by the function of evolution of the current as a function of the applied voltage.
- this function is linear and passes through 0, then it has a lower threshold voltage V min for that the current is non-zero in the case of a Schottky contact.
- a simple ohmic contact must be made in such a way that no energy barrier opposes the crossing of the interface between the ohmic contact and the semiconductor to be contacted, which limits the access resistances.
- the present invention relates to a field effect transistor comprising a substrate and a semiconductor structure having a channel region, said transistor comprising a drain contact, a source contact and a gate said source and drain contacts for generating a charge carrier stream in the channel region, said flow being controlled by said gate, characterized in that:
- said drain contact is a mixed drain contact comprising at least one continuous drain ohmic elementary contact and a drain Schottky elementary contact, said mixed drain contact flush with said semiconductor structure;
- said elementary Schottky drain contact partially or totally overlapping said ohmic drain elementary contact.
- the elemental Schottky drain contact partially or totally overlapping said ohmic drain elementary contact allows for reliable fabrication easily taking into account alignment and lithographic dimensional tolerances, perfect juxtaposition being impossible.
- the additional advantage is to easily allow a setting at the same potential of the Schottky contact to that of the ohmic drain contact.
- the source contact is a mixed contact comprising at least one source ohmic source contact and a source Schottky elementary contact.
- the elementary Schottky drain contact and / or the source Schottky elemental contact partially overlaps the ohmic elementary drain contact and / or the source ohmic source contact.
- the term partial overlap means that the ohmic drain and / or source elementary contact is covered by a Schottky elementary contact of drain and / or source, said Schottky elementary contact also having a portion in contact with said substrate.
- said gate comprises a Schottky type contact: metal / conductor.
- said grid has a complex shape presenting:
- a so-called lower part in contact with the semiconductor structure comprising the channel zone and having a first section;
- a so-called high second portion referred to as a gate cap, in contact with said lower portion and having a second section;
- the semiconductor structure comprises a set of layers of materials III-V, of which at least two materials have different forbidden bands, the largest (s) band (s) prohibited (s) for the containment of free carriers in the smallest bandgap.
- the transistor comprises a dielectric layer covering the source contact and / or the drain contact and / or the gate.
- the transistor further comprises a metal field plate located on said dielectric at said gate.
- the subject of the invention is also a component comprising a set of field effect transistors, comprising several subsets of transistors according to the invention:
- a subset of transistors being characterized by a width between the gate and the mixed drain contact and a width between said gate and the ohmic elementary contact of said mixed drain contact, for each of the transistors of said subset;
- said length between the gate and the ohmic elementary contact of said mixed drain contact being identical from one subset to the other.
- control of the field effect transistors is generally carried out using a metal grid which can be isolated (for example MOSFET or MOSHEMT) or not (HEMT, MESFET, etc.) from the underlying semiconductor.
- This metal grid is all the more difficult to realize that the cutoff frequencies of power gains and power are high. Indeed, it is necessary to control a grid foot length can be below 80 nm while ensuring a profile to reduce the series resistance obtained by increasing the section at the top of the electrode.
- the conventional method of producing a grid uses electronic or even optical lithographs.
- a stack of two different electro-sensitive resins (or even photosensitive for optical steppers) is used which makes it possible to form a metal grid of a suitable profile, generally called "mushroom”.
- Solutions with successive electronic or optical lithographs are also used by first opening the gate foot through a dielectric and then making a second lithography which delimits the "hat” of the grid. A metal deposit is then made which allows to "mold” a grid in the form of Gamma or T.
- Applicant has detected a manufacturing performance problem when attempting to modify certain key dimensions of the devices.
- the origin of the problem lies essentially in the variations of the thicknesses of the resins used to define the gate electrode during the crossing of the walkways, in this case ohmic contacts source and drain.
- Figure 2 shows for this purpose, the critical parameters that define the topology of an elementary component, knowing that the final component often involves the parallelization of several basic components.
- the perpendicular dimension is not represented but it defines the total development of the transistor.
- linear geometries are widely used although it is also possible to use circular or polygonal geometries.
- the gate length Lg which is related to the current transit frequency, said frequency decreasing when said gate length Lg increases;
- the section of the gate cap CG making it possible to size the gate resistance, while ensuring that said gate can have a narrow foot, this section influencing the gate resistance and the gain in microwave power;
- the distance Lds between source and drain which influences the breakdown voltage of the component (power) and the microwave gain (the greater the distance Ldg is large and the greater the breakdown voltage is important but at the cost of a degradation of the microwave gains);
- the ohmic contacts are defined and then the gate contact.
- the indicated order is often conditioned by the high thermal budget to make the ohmic contacts (metal alloys, ion implantation anneals, etc.).
- the annealing of the ohmic contacts in GaN technology often reaches 850 ° C for one to two minutes, ie a heat budget difficult to impose on Schottky contacts.
- These ohmic contacts have a thickness e_s and e_d which is close to the height of the gate foot Hg in order to have the sufficient lithographic resolution.
- a conventional method of producing a grid having a CG cap is to use at least two resins:
- foot + hat is then obtained by chemistries and sensitivities different from the insolations and the physicochemical revelations
- FIG. 3 shows the sectional view of a field effect transistor during the coating of the first resin. It is noted that the filling of the Lds interval is performed differently depending on the coating, viscosity and post-coating creep conditions of the resin, leaving an inherent width. The thickness of this first resin varies and it is even thicker than the length Lds is small.
- the applicant estimated at 25% the variation of thickness when the distance Lds is modified from 10 ⁇ to 1, 5 ⁇ for an electrosensitive resin used for grids up to 0,15 ⁇
- a consequence on the performance of manufacturing is shown as an example of 90% for standard topologies and drops to 40% for grid-source deviations of 0.5 ⁇ .
- the present invention also relates to a method of manufacturing a field effect transistor according to the invention, characterized in that it comprises the following steps:
- the method comprises the realization of a source Schottky elementary contact so as to achieve a mixed source contact comprising at least one ohmic elementary contact and a Schottky elementary contact.
- the realization of the elementary Schottky drain and / or source contact is made by partially overlapping respectively said ohmic elementary contact drain and / or associated source.
- the grid having:
- a so-called lower part in contact with the semiconductor structure comprising the channel zone and having a first section;
- a so-called high second portion referred to as a gate cap, in contact with said lower portion and having a second section;
- said method comprises:
- the realization of said elementary Schottky drain contact and / or Schottky elementary source contact is (are) carried out simultaneously with the production of said gate.
- the realization of said elementary Schottky drain contact and / or said source Schottky elementary contact is (are) carried out simultaneously with the realization of said gate cap.
- the subject of the invention is a method of collective fabrication of a set of field effect transistors, said set of transistors comprising subsets of transistors:
- transistors of the same subset of transistors having a width between the gate and the identical mixed drain contact for each transistor of the same subset and different from one subset to the other;
- the width between the gate and the ohmic elemental drain contact being identical from one subset to the other, characterized in that it comprises the following steps:
- the invention thus makes it possible to improve the production efficiency of the field effect transistors while improving their power efficiencies.
- FIG. 1 illustrates the block diagram of a field effect transistor
- FIG. 2 illustrates the technological parameters that are important for the optimization of a field effect component.
- FIG. 3 illustrates the effects of the deposition of a resin with step transition between drain and source contacts for the production of a field effect transistor
- FIG. 4 illustrates a first component variant according to the invention
- FIG. 5 shows the block diagram of a transistor according to the invention comprising a mixed drain contact
- FIG. 6 illustrates a second component variant according to the invention
- FIG. 7 illustrates a third component variant according to the invention
- FIG. 8 illustrates a fourth component variant according to the invention
- FIG. 9 illustrates an exemplary component according to the invention.
- FIG. 10 details the grid formed according to the example illustrated in FIG. 8;
- FIG. 11 illustrates a method of collective fabrication of transistors, making it possible to produce different sizes of components, with variable dimensions of Li G -D width between grid and mixed drain contact.
- the present invention thus relates to a component in which the drain contact which is mixed combines a conventional elementary ohmic contact and a metal-semiconductor Schottky elementary contact. It thus makes it possible to have to optimize only once the lithographic profile of the grid and this for a wide range of distance between ohmic contacts drain and source, for a given gate-source distance.
- Using a live Schottky elemental contact to collect carriers can also improve reliability by providing a more consistent collection of carriers.
- the Schottky contact of the mixed ohmic contact assures a role of field shield plate (Field plate) improving the voltages of breakdown of the component.
- FIG. 4 A first example of a component according to the present invention is illustrated in FIG. 4, comprising a mixed drain contact.
- a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:
- a mixed drain contact comprising an ohmic elementary contact of drain C D oh and a Schottky elementary contact of drain C D s
- the continuity of elementary Schottky drain contact partially covering the end of the elementary contacting ohmic drain which may have imperfections, overcomes the potential defects of achieving ohmic contact.
- the ohmic contact is located at a sufficiently distant distance for the Schottky drain contact to cover the different spacings required for the intended applications.
- the elementary Schottky drain contact can also be realized.
- the unevenness of conventional ohmic contacts crossed by the resins successively used to make the grid are therefore constant. This ensures a better manufacturing yield.
- the Schottky elementary drain contact also provides the possibility of a contact with low resistance (direct-to-majority junction) above the elbow voltage of the Schottky diode. This is achieved more with a low thermal budget.
- FIG. 5 illustrates the diagram of an ohmic drain contact by association of a conventional ohmic contact and a Schottky contact.
- the current lds_co (in solid lines) corresponds to the current passing conventionally via the ohmic contact.
- the lds_Sch current (in dotted lines) represents the current flowing through the Schottky contact.
- the resistance control associated with the traditional ohmic contact is obtained either by playing on the topology of the contact (length of the semiconductor rod to be crossed, width of the ohmic contact), or on the conductivity of the semiconductor, or by using for this plate of a Schottky junction field with a low potential barrier.
- the breakdown voltages can be improved according to the semiconductors contacted.
- FIG. 6 schematizes a second example of a component according to the present invention comprising a mixed drain contact and a mixed source contact.
- a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:
- a source mixed contact comprising an ohmic elementary contact of source C S 0 h and a Schottky elementary contact of source C S s ch;
- a mixed drain contact comprising an ohmic elementary contact of drain C D oh and a Schottky elementary contact of drain C D s
- FIG. 7 schematizes a third example of a component according to the present invention comprising a mixed drain contact.
- a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:
- a mixed drain contact comprising an ohmic elementary contact of drain C D oh and a Schottky elementary contact of drain C D s
- the mixed drain contact is associated with a field plate to avoid electric field peaks.
- This field plate P ch which can be brought to the potential of the source or of the gate is materialized by a conducting layer above a dielectric layer 2 and surrounding said gate G.
- FIG. 8 schematizes a fourth example of a component according to the present invention comprising a mixed drain contact.
- a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:
- a mixed drain contact having an ohmic drain elementary contact C D oh and a Schottky elementary contact of drain Co sch-
- the mixed drain contact is associated with a field plate P ch that can be brought to the potential of the source or the gate and which is materialized by a conductive layer above a dielectric layer 2 and surrounding said gate G.
- the end of the Schottky contact vis-à-vis the gate drain comprises a protuberance on the dielectric for amplifying the drain field plate effect.
- the realization of Schottky drain contacts does not require additional level of lithography. It is possible to form these contacts at other stages of the process succeeding the realization of the gate (for example during a level of the field plate type for example).
- Exemplary embodiment of a field effect transistor HEMT according to the invention.
- FIG. 9 illustrates the production of a stack of layers enabling the constitution of a field effect transistor heterostructure.
- a homogeneous crystalline substrate 100 or not SiC, Si, sapphire, GaN or composite
- SiC, Si, sapphire, GaN or composite the following heterostructure by stacking layers below:
- nucleation layer 101 allowing growth on the heterogeneous substrate (SiC, Si, or sapphire);
- a layer or set of layers 102 enabling the control of mechanical stresses
- a buffer layer 103 of GaN or doped or non-doped GaN compound allowing the confinement of the free carriers present in the layer 104;
- a layer 104 of GaN semiconductor channel (which may have a thickness of 40 nm to 250 nm depending on the applications);
- a barrier layer 105 in AI 2 5 % Gay 5% N (which may have a thickness 25nm) or in ln x Ali. x N;
- a doped or undoped GaN encapsulation layer 106 (which may have a thickness of 2 nm) or another dielectric.
- the ohmic source contact C S Oh and the elementary ohmic drain contact C D 0h are then made in a known manner by diffusion from Ti / Al / Ni / Au deposits and rapid thermal annealing operation.
- the gate G is also produced.
- FIG. 10 illustrates, for this purpose, the various metallic layers constituting the gate, for example: Ni / Pt / Au, in the central cavity previously made by successive resin deposits, for example, in order to obtain the complex shape.
- the Schottky elemental drain contact C D S ch is also made with a metal structure (not shown).
- the first layer in contact with the GaN free surface may be silicon nitride of a hundred nanometers thick.
- the gate width Lg may typically be 0.15 ⁇ but may vary between 0.05 ⁇ to several microns;
- the width between the drain contact and the Ldg gate may be between 0.5 ⁇ and several tens of microns depending on the cut-off frequencies of the microwave gains and the targeted breakdown voltages;
- the width between the gate and the source contact Lgs is generally shorter than the width Ldg but may also range from 0.5 ⁇ to several microns;
- the gate height Hg can typically be 0.25 ⁇ up to 2 ⁇ and beyond;
- the total height of the gate may typically be 0.4 ⁇ , but also may be optimized from 0.1 ⁇ to several microns.
- the shape of the grid can be adjusted.
- the shape can be a mushroom as previously illustrated for grids shorter than ⁇ , ⁇ , beyond this form is not necessary.
- a rectangular shape can be considered also for very short grids, but this may increase the series resistance of the grid.
- the thicknesses of source and drain contacts e_s and e_d can typically be 0.2 ⁇ , this value being relatively free. According to the present invention, it is advantageous to collectively produce components having different characteristics, avoiding differentiated delicate steps to make the ohmic contacts, the most complex contacts to obtain.
- Figure 1 1 illustrates such a collective method for producing a set of components to the surface of a substrate according to the invention.
- the step of complex realization of the set of ohmic contacts can be performed in a uniform manner.
- the step of producing the Schottky drain contacts is carried out in a second step and makes it possible to achieve the desired differentiation between components having different performances and characteristics by obtaining distances between grids and elementary Schottky drain contacts (C D s ch ) variables. Is thus obtained subsets of transistors ST ⁇ , ST i + comprising:
- the invention thus enables n having to optimize lithographic once the profile of the gate and for a wide range of distance between the source and drain ohmic contacts, for a given gate-source distance.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR1402238A FR3026892B1 (fr) | 2014-10-03 | 2014-10-03 | Transistor a effet de champ avec contact de drain mixte optimise et procede de fabrication |
PCT/EP2015/072624 WO2016050879A1 (fr) | 2014-10-03 | 2015-09-30 | Transistor à effet de champ avec contact de drain mixte optimisé et procédé de fabrication |
Publications (1)
Publication Number | Publication Date |
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EP3201949A1 true EP3201949A1 (fr) | 2017-08-09 |
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EP15774593.6A Withdrawn EP3201949A1 (fr) | 2014-10-03 | 2015-09-30 | Transistor à effet de champ avec contact de drain mixte optimisé et procédé de fabrication |
Country Status (4)
Country | Link |
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EP (1) | EP3201949A1 (fr) |
CN (1) | CN107078153A (fr) |
FR (1) | FR3026892B1 (fr) |
WO (1) | WO2016050879A1 (fr) |
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CN110190126A (zh) * | 2019-04-30 | 2019-08-30 | 福建省福联集成电路有限公司 | 一种抗反激信号的半导体器件及制作方法 |
US11145735B2 (en) * | 2019-10-11 | 2021-10-12 | Raytheon Company | Ohmic alloy contact region sealing layer |
CN111952356A (zh) * | 2020-07-13 | 2020-11-17 | 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) | Hemt器件结构及其制备方法 |
CN117133805A (zh) * | 2023-10-16 | 2023-11-28 | 重庆邮电大学 | 一种混合漏极增强型GaN高电子迁移率晶体管 |
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KR101120921B1 (ko) * | 2010-03-25 | 2012-02-27 | 삼성전기주식회사 | 반도체 소자 및 그 제조 방법 |
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KR20120120828A (ko) * | 2011-04-25 | 2012-11-02 | 삼성전기주식회사 | 질화물 반도체 소자 및 그 제조방법 |
CN102810559A (zh) * | 2012-08-21 | 2012-12-05 | 中山大学 | 一种兼具反向导通的异质结构场效应晶体管及其制作方法 |
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2014
- 2014-10-03 FR FR1402238A patent/FR3026892B1/fr active Active
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2015
- 2015-09-30 WO PCT/EP2015/072624 patent/WO2016050879A1/fr active Application Filing
- 2015-09-30 EP EP15774593.6A patent/EP3201949A1/fr not_active Withdrawn
- 2015-09-30 CN CN201580060895.0A patent/CN107078153A/zh active Pending
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JPS546777A (en) * | 1977-06-17 | 1979-01-19 | Nec Corp | Field effect type transistor |
US5321284A (en) * | 1984-07-06 | 1994-06-14 | Texas Instruments Incorporated | High frequency FET structure |
JPH03238831A (ja) * | 1990-02-15 | 1991-10-24 | Nec Corp | 化合物半導体電界効果トランジスタ |
US20140252370A1 (en) * | 2013-03-05 | 2014-09-11 | Seoul Semiconductor Co., Ltd. | Nitride semiconductor device and method of manufacturing the same |
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Also Published As
Publication number | Publication date |
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WO2016050879A1 (fr) | 2016-04-07 |
CN107078153A (zh) | 2017-08-18 |
FR3026892B1 (fr) | 2017-12-01 |
FR3026892A1 (fr) | 2016-04-08 |
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