EP3140854A1 - Procédé d'application de préparation de frittage métallique séchée au moyen d'un substrat de transfert sur un support pour composants électroniques, support correspondant et son utilisation pour la liaison par frittage avec des composants électroniques - Google Patents
Procédé d'application de préparation de frittage métallique séchée au moyen d'un substrat de transfert sur un support pour composants électroniques, support correspondant et son utilisation pour la liaison par frittage avec des composants électroniquesInfo
- Publication number
- EP3140854A1 EP3140854A1 EP14758919.6A EP14758919A EP3140854A1 EP 3140854 A1 EP3140854 A1 EP 3140854A1 EP 14758919 A EP14758919 A EP 14758919A EP 3140854 A1 EP3140854 A1 EP 3140854A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- electronic components
- carrier
- transfer substrate
- metal sintering
- conductive surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 97
- 239000002184 metal Substances 0.000 title claims abstract description 97
- 238000005245 sintering Methods 0.000 title claims abstract description 87
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 48
- 150000001875 compounds Chemical class 0.000 title abstract 9
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 10
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000002923 metal particle Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
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- 239000000463 material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 229920002799 BoPET Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229920002313 fluoropolymer Polymers 0.000 description 2
- 239000004811 fluoropolymer Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
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- 150000002736 metal compounds Chemical class 0.000 description 2
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- 239000002245 particle Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
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- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009770 conventional sintering Methods 0.000 description 1
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- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0244—Powders, particles or spheres; Preforms made therefrom
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0244—Powders, particles or spheres; Preforms made therefrom
- B23K35/025—Pastes, creams, slurries
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/4867—Applying pastes or inks, e.g. screen printing
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/4871—Bases, plates or heatsinks
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/49838—Geometry or layout
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/207—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a prefabricated paste pattern, ink pattern or powder pattern
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1131—Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
Definitions
- metal sinter preparations for fastening and electrical contacting of and for heat dissipation from electronic components such as semiconductor chips.
- metal sinter preparations are disclosed in WO201 1/026623 A1, EP2425920A1, EP2428293A2 and EP2572814A1.
- metal sintering compositions are applied by printing, for example screen or stencil printing, on carrier substrates, optionally dried, equipped with electronic components and then subjected to a sintering process. Without passing through the liquid state, the metal particles combine by diffusion during sintering to form a solid, electrical and heat conductive metallic connection between the carrier and the electronic component.
- the object of the invention was to find a method which allows the simultaneous application (application in one process step) of several layer fragments of metal sintering preparation to not completely flat and possibly already equipped with electronic components te carrier and the temperature stress of the carrier or possibly already Electronic components as low as possible.
- the present invention relates to a method for applying a plurality of discrete layer fragments of dried metal sintering preparation to predetermined, electrically conductive surface portions of a support for electronic components.
- a flat transfer substrate provided with the dried metal sintering preparation is used. The method comprises the steps:
- adhesion force of the dried metal sintering preparation after completion of step (4) is greater than the predetermined, electrically conductive surface portions of the carrier for electronic components, as compared to the surface of the transfer substrate,
- planar transfer substrate is a non-sinterable and optionally coated metal foil or a thermoplastic plastic film
- the carrier for electronic components is a substrate having a planar, one or more recesses of 10 to 500 ⁇ having surface and at the same time from the group consisting of lead frames (lead frames), ceramic substrates, DCB substrates and metal composite materials is selected, and wherein at least one predetermined, electrically conductive surface portion is located in a recess.
- the invention also relates to the carrier for electronic components produced by the process according to the invention and provided with dried metal sintering preparation.
- Examples of electronic components are active components (for example semiconductor chips such as LEDs, diodes, IG-BTs, thyristors, MOSFETs, transistors) and / or passive components (for example resistors, capacitors, inductors and memristors) and / or piezoceramics and / or Peltier elements.
- active components for example semiconductor chips such as LEDs, diodes, IG-BTs, thyristors, MOSFETs, transistors
- passive components for example resistors, capacitors, inductors and memristors
- piezoceramics and / or Peltier elements for example semiconductor chips such as LEDs, diodes, IG-BTs, thyristors, MOSFETs, transistors
- passive components for example resistors, capacitors, inductors and memristors
- the term “dried metal sintering preparation” means no longer moist, fully or essentially devolatilized, non-sintered metal sintering preparation.
- “Dried metal sintering preparation” means, for example, that 98 to 100% by weight of the volatiles originally contained in the metal sintering preparation have been removed and the dried metal sintering preparation gravimetrically proves to be mass constant or substantially constant in mass even after repeated application of the drying conditions used in step (2).
- the dried metal sinter preparation is a solidified, sinterable metal sintering preparation which is stable at temperatures of ⁇ 70 ° C. The metal in ter terzurung used as such in step (1) of the process according to the invention will be discussed further below.
- the carrier for electronic components to which the metal sintering preparation dried in the process according to the invention is applied is a carrier substrate customary in the electronics industry selected from the group consisting of stamped gratings, ceramic substrates, DCB substrates and metal composite materials, the substrate for electronic components also being a substrate with a surface which is in itself planar, but which has one or more recesses of 10 to 500 ⁇ m, also referred to as cavities.
- the carrier may be a flat substrate.
- the carrier for electronic components has electrically conductive surface portions for voltage / current supply of the electronic components.
- electrically conductive surface portions refers to the layout of the electrically conductive surface portions of or on the electrically insulating surface of the carrier, ie, for example, the pattern of printed conductors Reference is made to those proportions of the electrically conductive surface portions on which dried metal sintering preparation is applied or where electronic components are to be fastened and electrically contacted by means of the dried metal sinter preparation. At least one predetermined, electrically conductive surface portion is located in a recess of 10 to 500 ⁇ . In other words, several constellations are possible:
- the carrier has a depression of 10 to 500 ⁇ m and there is a predetermined, electrically conductive surface portion in the depression, wherein one or more further predetermined electrically conductive surface portions are located outside the depression ,
- the carrier has a recess of 10 to 500 ⁇ and there are several predetermined, electrically conductive surface portions in the recess, with one or more further predetermined, electrically conductive surface portions are outside the recess.
- the carrier has a recess of 10 to 500 ⁇ and there are all predetermined, electrically conductive surface portions in the recess.
- the carrier has several wells of 10 to 500 ⁇ and there is one of the predetermined, electrically conductive surface portions in one of the wells, while the one or more predetermined, electrically conductive surface portions are outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are a plurality of predetermined, electrically conductive surface portions in one of the wells, while one or more further predetermined, electrically conductive surface portions are outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are all predetermined, electrically conductive surface portions in one of the wells.
- the carrier has several wells of 10 to 500 ⁇ and there is in each case a predetermined, electrically conductive surface portion in each of the wells, while there are no, one or more further predetermined, electrically conductive surface portions outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there is in each case a predetermined, electrically conductive surface portion in some of the wells, while no, one or more further predetermined, electrically conductive surface portions are outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are in each case a plurality of predetermined, electrically conductive surface portions in each of the wells, while none, one or more further predetermined, electrically conductive surface portions are outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are each a plurality of predetermined, electrically conductive surface portions in some of the wells, while no, one or more further predetermined, electrically conductive surface portions are outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are partly one and partly a plurality of predetermined, electrically conductive surface portions in two or more of the wells, while there are none, one or more further predetermined, electrically conductive surface portions outside the wells.
- the carrier has several wells of 10 to 500 ⁇ and there are partly one and partly a plurality of predetermined, electrically conductive surface portions in the wells, wherein no wells without predetermined, electrically conductive surface portions exist and wherein none, one or more further predetermined, electrically conductive surface portions are located outside the wells.
- the carrier for electronic components can also be equipped with one or more electronic components before it is provided in the process according to the invention with the layer fragments of dried metal sintering.
- a depth or total depth of, for example, 10 to 200 ⁇ m or, in the case of components having a relatively large component height, even of, for example, 200 to 1000 ⁇ m, can prevail between such adjacent ones.
- the total depth may, for example, be composed of the depth of one of the recesses of 10 to 500 ⁇ m plus the highest component height of the electronic component or components adjacent to such a recess or located next to such a recess.
- the electrically conductive surface portions of the carrier for electronic components are in particular metallic. In the latter case, it is customary for electrical contacting thin metal layers or metallizations, for example, copper, silver, gold, palladium, nickel, aluminum and suitable alloys of such metals. They may also be metals coated with other metal layers, for example gold coated with gold, nickel coated with gold and palladium, silver / palladium coated with a gold layer.
- a metal sintered preparation in the form of a plurality of discrete layer fragments is applied to one side of a planar transfer substrate in a mirror-image arrangement to the predetermined, electrically conductive surface portions of the electronic component carrier; in the predetermined, electrically conductive surface portions of the carrier for electronic components corresponding, but mirror-image arrangement.
- the discrete layer fragments are applied in one step or simultaneously.
- Discrete layer fragments means that it is not a continuous layer but individual layered elements of the metal sinter preparation which are isolated from one another given explanations, it is also at the predetermined, electrically conductive surface portions to individual and isolated from each other surface portions.
- the metal sintering preparation is a per se known metal sintering preparation as used in the electronics industry for fastening and electrical contacting of and for heat dissipation from electronic components.
- the metal sintering preparation contains, in addition to possible additives, in particular also volatile organic solvents.
- the metal particles are, for example, those of copper, nickel, aluminum or in particular of silver, in each case with average particle sizes (d50, determined by laser diffraction) in the range of, for example, 1 to 10 ⁇ m.
- the planar transfer substrate is a non-sinterable and optionally coated metal foil or a thermoplastic plastic film, for example of polyester, fluoropolymer such as polytetrafluoroethylene, polyimide, silicone or polyolefin.
- the plastic film may be provided, for example coated, with an adhesion-reducing material in the mass or on the side to be provided with the metal sintering preparation.
- adhesion reducing materials include silicone or fluoropolymer based materials.
- the planar transfer substrate is a transparent plastic film.
- the adhesion force of the dried metal sintering preparation to the predetermined, electrically conductive surface portions of the electronic component carrier is greater after completion of step (4) than to the surface of the transfer substrate.
- the adhesive force is greater by 0.4 or more N / cm, determined in accordance with DIN EN 14099 (October 2002) with adhesive tape having an adhesive strength of 220 g / cm.
- the transfer substrate is a non-rigid thermoplastic film, which is largely dimensionally stable even after thermal stress.
- the non-rigid thermoplastic resin film has a dimension change in length and width of ⁇ 1.5% (ASTM D 1204) after a thermal load of 30 minutes at 120 ° C object temperature, i.e., a dimensional change. Under these conditions, preference is given to no dimensional change or a maximum change in the length and width direction of up to a maximum of 1.5% (ASTM D 1204).
- thermoplastic films which can be used as transfer substrates in the process according to the invention are the commercially available plastic films Hostaphan® RN75 from Mitsubishi, Mylar® A 50 ⁇ m or 75 ⁇ m from DuPont and Lumirror® 40.01 from Toray.
- the application of the metal sintering preparation to the transfer substrate is usually carried out by printing, for example screen printing or stencil printing, in a dry film thickness of, for example, 5 to 200 ⁇ m.
- the application can also be carried out by spray application, it may be appropriate to take measures to protect areas that should not come into contact with the metal sintering preparation. Examples of such measures are masking or masking with stencils.
- step (2) of the process of the invention the wet metal sintering composition applied in step (1) is dried to avoid sintering, i. from volatiles such as organic solvents.
- the drying of the metal sintering preparation is preferably carried out under conditions, in particular temperature conditions, which are suitable for removing the volatile constituents from the metal sintering preparation, without, however, that after the drying sintering processes within the metal sintering preparation have already completely run off.
- the transfer substrate provided with the metal sintering preparation can be heated, for example, for 10 to 30 minutes at an object temperature of 80 to 150 ° C., for example in an oven, for example a circulating air oven.
- the furnace may optionally be inertized, for example by means of a nitrogen atmosphere.
- the dried metal sinter preparation is at least substantially freed from volatile constituents such as solvents and, in addition to the metal particles and / or the metal forming metal compounds during the subsequent sintering process, it contains non-volatile additives, for example.
- the dried metal sinter preparation is solidified, but not or only partially sintered, i. the solidified metal sinter preparation is still sinterable.
- the transfer substrate with the dried metal sinter preparation thereupon thus forms a preform which can be supplied as an intermediate to the further production process comprising steps (3) to (5).
- the further manufacturing process comprising steps (3) to (5) may be carried out by the manufacturer performing steps (1) and (2) or by another manufacturer.
- the intermediate product is stable overall and so manageable that it can be transported for further processing. This is because the dried metal sintering preparation is solidified and dimensionally stable.
- step (3) of the method according to the invention the transfer substrate with the layer fragments of dried metal sintering preparation is turned to the surface of the support for electronic components and ensuring a congruent positioning of the dried metal sintering preparation surface portions of the transfer substrate and the predetermined, electrically conductive surface portions of the support for Electronic components arranged and brought into contact. In this way, it is ensured that the locations with the dried metal sintering preparation on the transfer substrate overlap with said predetermined, electrically conductive surface portions of the carrier for electronic components, onto which dried metal sintering preparation or later where electronic components are attached by means of the previously applied dried metal sintering preparation and to be contacted electrically.
- the arrangement in step (3) can take place in any position, for example in a vertical or horizontal position. For example, in a horizontal position, the transfer substrate can be arranged below the support for electronic components or vice versa.
- step (4) of the method according to the invention the actual transfer step, pressing force is exerted on the contact arrangement created in step (3), either over the entire surface or at least completely at the positions where the dried metal sinter preparation is located.
- a contact pressure of 0.5 to 10 MPa can be used for a duration of, for example, 1 to 30 seconds.
- elevated object temperatures of up to 150 ° C;
- the heating can be effected by means of a bottom and / or top side heating of the pressing tool.
- conventional devices can be used, for example a laminating press, in particular a heatable laminating press.
- a silicone plate with an adjusted degree of hardness for example a Shore A hardness of 50 to 70, can be used between the press die and the dried metal sintered preparation transfer substrate.
- an adjusted degree of hardness for example a Shore A hardness of 50 to 70
- exertion of compressive force and aids can be used, which act in the manner of a stamp at the positions where the dried metal sintering preparation is.
- Such a procedure is particularly expedient if the carrier is already equipped with electronic components, especially electronic components with a relatively large overall height. It may also be expedient if the transfer substrate has corresponding recesses for such already existing electronic components, so that the transfer substrate can come completely into contact with the surface of the carrier for electronic components.
- step (4) the transfer substrate is removed in step (5) of the method according to the invention, wherein the dried metal sintering preparation remains on the predetermined, electrically conductive surface portions of the carrier for electronic components.
- the previously adhering to the transfer substrate, freed by means of transfer surface of the dried metal sintering preparation is now intended to hold one or for connection to an electronic component, which is reserved for another manufacturing process.
- steps (3) to (5) can be carried out as a batch process or continuously, for example in the sense of a roll lamination process.
- the discrete layer fragments are transferred in step sequence (3) to (5) in one step or simultaneously from the transfer substrate to the carrier for electronic components.
- the method according to the invention can be carried out such that the support for electronic components is provided on both sides with a dried metal sinter preparation.
- the same process steps (1) to (5) are carried out, with the difference that the support for electronic components in steps (3) to (4) is arranged between two transfer substrates suitably provided with dried metal sintering preparation and subjected to the pressing process, and then into Step (5) the transfer substrates are removed from both sides of the electronic component carrier.
- the one or more steps taken to receive and connect to electronic components are part of a further manufacturing process that may, for example, take place at another manufacturer.
- This further manufacturing process comprises the actual sintering step.
- a customary sandwich arrangement is created from the support for electronic components with dried metal sintering preparation transferred thereto according to the method according to the invention and the electronic components.
- the sandwich arrangement is then subjected to the sintering process, in the course of which the sintered metal sinter preparation is formed from the dried metal sinter preparation and a mechanical, electrical and heat-conducting connection is formed between support and electronic components.
- the product of the process according to the invention comprising the steps (1) to (5) in the form of the dried metal sintered carrier for electronic components forms a preform which can be supplied as an intermediate product to the further production process explained in the preceding paragraph.
- the intermediate product is stable overall and so manageable that it can be transported for further processing. This is because the transferred dried metal sintering preparation is solidified and dimensionally stable.
- the inventive method allows the application of dried metal sintering preparation in the form of layer fragments on a support for electronic components in one step and without burdening the carrier or electronic components with the prevailing in the drying of the metal sintering preparation temperature.
- the inventive method allows the application of the dried metal sintering preparation in depressions on the surface of the carrier and optionally between existing on the support electronic components, which is not possible with the conventional screen or stencil printing.
- Ausfatunqsbeispiel sining of 2 diodes (IFX I DC73D120T6H) in 150 [in deep cavities in 500 ⁇ thick silver sheet (from Fa. GoodFellow, type AG000465) as a carrier for electronic components):
- a sintering paste ASP 043-04 Fa. Heraeus, Hanau was using a DEK Horizon 03iX stencil printer using a 75 ⁇ m thick steel stencil from Koenen onto a PET film from Mitsubishi, type Hostaphan® RN7525JK as transfer substrate (printing speed 20 mm / s, squeegee pressure 2 kg), the layout of the printed sintered paste being mirror-image to the layout of the cavities in the silver plate was arranged.
- the printed transfer film was dried in a circulating air oven (Binder) for 15 minutes at 100.degree.
- the printed transfer sheet which was provided with dried sintering paste, was placed on the silver sheet with the printed side in the same direction as the sintering paste and cavities.
- a silicone film (Alpha Tectrade, type Silicone 60 red Basic) was placed over the unprinted side of the transfer film. Under a laminating press (Laufer), the sintering paste was transferred to the silver plate in the cavities (10 sec. At a contact pressure of 5 MPa at a temperature of 100 ° C on the side of the silver sheet, without heating on the side of the transfer film). After completion of the transfer, the transfer film was removed and the silver plate could be loaded in the provided with dried sintered paste cavities with the diodes and then fed to a pressure sintering process.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Mechanical Engineering (AREA)
- Geometry (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP14167010 | 2014-05-05 | ||
PCT/EP2014/068739 WO2015169401A1 (fr) | 2014-05-05 | 2014-09-03 | Procédé d'application de préparation de frittage métallique séchée au moyen d'un substrat de transfert sur un support pour composants électroniques, support correspondant et son utilisation pour la liaison par frittage avec des composants électroniques |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3140854A1 true EP3140854A1 (fr) | 2017-03-15 |
Family
ID=50693471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP14758919.6A Withdrawn EP3140854A1 (fr) | 2014-05-05 | 2014-09-03 | Procédé d'application de préparation de frittage métallique séchée au moyen d'un substrat de transfert sur un support pour composants électroniques, support correspondant et son utilisation pour la liaison par frittage avec des composants électroniques |
Country Status (9)
Country | Link |
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US (1) | US20170194169A1 (fr) |
EP (1) | EP3140854A1 (fr) |
JP (1) | JP6407305B2 (fr) |
KR (1) | KR20160136351A (fr) |
CN (1) | CN106463413B (fr) |
MX (1) | MX2016012036A (fr) |
SG (1) | SG11201608656PA (fr) |
TW (1) | TW201601858A (fr) |
WO (1) | WO2015169401A1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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EP3622554A1 (fr) * | 2017-05-12 | 2020-03-18 | Heraeus Deutschland GmbH & Co. KG | Procédé pour assembler des composants au moyen d'une pâte métallique |
CN107845627B (zh) * | 2017-09-29 | 2020-02-18 | 深圳奥比中光科技有限公司 | 多接近度检测光传感器 |
US11373976B2 (en) * | 2019-08-02 | 2022-06-28 | Rockwell Collins, Inc. | System and method for extreme performance die attach |
JP7023302B2 (ja) * | 2020-02-04 | 2022-02-21 | 田中貴金属工業株式会社 | 導電性接合材料を備える接合部材及び接合方法 |
JP7536528B2 (ja) | 2020-06-29 | 2024-08-20 | 日東電工株式会社 | 積層体 |
TW202335556A (zh) * | 2022-01-20 | 2023-09-01 | 美商阿爾發金屬化工公司 | 使用層壓模組化預製件接合電組件及機械組件之方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6029882A (en) * | 1998-04-27 | 2000-02-29 | International Business Machines Corporation | Plastic solder array using injection molded solder |
JP2004172612A (ja) * | 2002-11-06 | 2004-06-17 | Ricoh Co Ltd | 微小径バンプを有する半導体素子、インクジェット方式によるバンプ形成およびそれに用いるインク組成物 |
US7059512B2 (en) * | 2002-11-06 | 2006-06-13 | Ricoh Company, Ltd. | Solder alloy material layer composition, electroconductive and adhesive composition, flux material layer composition, solder ball transferring sheet, bump and bump forming process, and semiconductor device |
US7005325B2 (en) * | 2004-02-05 | 2006-02-28 | St Assembly Test Services Ltd. | Semiconductor package with passive device integration |
US7847375B2 (en) * | 2008-08-05 | 2010-12-07 | Infineon Technologies Ag | Electronic device and method of manufacturing same |
DE102009040076A1 (de) | 2009-09-04 | 2011-03-10 | W.C. Heraeus Gmbh | Metallpaste mit Oxidationsmittel |
DE102010044329A1 (de) * | 2010-09-03 | 2012-03-08 | Heraeus Materials Technology Gmbh & Co. Kg | Kontaktierungsmittel und Verfahren zur Kontaktierung elektrischer Bauteile |
DE102010044326A1 (de) | 2010-09-03 | 2012-03-08 | Heraeus Materials Technology Gmbh & Co. Kg | Verwendung von aliphatischen Kohlenwasserstoffen und Paraffinen als Lösemittel in Silbersinterpasten |
WO2012061511A2 (fr) * | 2010-11-03 | 2012-05-10 | Fry's Metals, Inc. | Matériaux de frittage et procédés de fixation les utilisant |
DE102011005322B4 (de) * | 2011-03-10 | 2017-04-06 | Semikron Elektronik Gmbh & Co. Kg | Verfahren zur Herstellung eines Leistungshalbleitersubstrates |
HUE028880T2 (en) | 2011-09-20 | 2017-01-30 | Heraeus Deutschland Gmbh & Co Kg | Paste and process for connecting electronic components with a carrier |
US8598694B2 (en) * | 2011-11-22 | 2013-12-03 | Infineon Technologies Ag | Chip-package having a cavity and a manufacturing method thereof |
US20150107764A1 (en) * | 2012-07-03 | 2015-04-23 | Toray Industries, Inc. | Process for producing adhesive sheet having singulated adhesive layer, process for producing wiring substrate using the adhesive sheet, method of manufacturing semiconductor equipment, and equipment for producing adhesive sheet |
-
2014
- 2014-09-03 SG SG11201608656PA patent/SG11201608656PA/en unknown
- 2014-09-03 KR KR1020167028791A patent/KR20160136351A/ko not_active Application Discontinuation
- 2014-09-03 EP EP14758919.6A patent/EP3140854A1/fr not_active Withdrawn
- 2014-09-03 CN CN201480078656.3A patent/CN106463413B/zh active Active
- 2014-09-03 JP JP2016565289A patent/JP6407305B2/ja active Active
- 2014-09-03 US US15/308,739 patent/US20170194169A1/en not_active Abandoned
- 2014-09-03 WO PCT/EP2014/068739 patent/WO2015169401A1/fr active Application Filing
- 2014-09-03 MX MX2016012036A patent/MX2016012036A/es unknown
-
2015
- 2015-04-21 TW TW104112755A patent/TW201601858A/zh unknown
Non-Patent Citations (2)
Title |
---|
None * |
See also references of WO2015169401A1 * |
Also Published As
Publication number | Publication date |
---|---|
TW201601858A (zh) | 2016-01-16 |
MX2016012036A (es) | 2017-01-19 |
CN106463413A (zh) | 2017-02-22 |
US20170194169A1 (en) | 2017-07-06 |
JP2017520907A (ja) | 2017-07-27 |
WO2015169401A1 (fr) | 2015-11-12 |
SG11201608656PA (en) | 2016-12-29 |
CN106463413B (zh) | 2019-10-25 |
JP6407305B2 (ja) | 2018-10-17 |
KR20160136351A (ko) | 2016-11-29 |
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