EP2901477A4 - Flexible, space-efficient i/o circuitry for integrated circuits - Google Patents
Flexible, space-efficient i/o circuitry for integrated circuitsInfo
- Publication number
- EP2901477A4 EP2901477A4 EP13842574.9A EP13842574A EP2901477A4 EP 2901477 A4 EP2901477 A4 EP 2901477A4 EP 13842574 A EP13842574 A EP 13842574A EP 2901477 A4 EP2901477 A4 EP 2901477A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuitry
- efficient
- flexible
- space
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/627,270 US9166593B2 (en) | 2012-05-28 | 2012-09-26 | Flexible, space-efficient I/O circuitry for integrated circuits |
PCT/US2013/061317 WO2014052274A1 (en) | 2012-09-26 | 2013-09-24 | Flexible, space-efficient i/o circuitry for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2901477A1 EP2901477A1 (en) | 2015-08-05 |
EP2901477A4 true EP2901477A4 (en) | 2016-07-06 |
Family
ID=53719571
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP13842574.9A Withdrawn EP2901477A4 (en) | 2012-09-26 | 2013-09-24 | Flexible, space-efficient i/o circuitry for integrated circuits |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP2901477A4 (en) |
JP (1) | JP2015532530A (en) |
KR (1) | KR20150058273A (en) |
CN (1) | CN104781924A (en) |
WO (1) | WO2014052274A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7273654B2 (en) * | 2019-08-09 | 2023-05-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device, manufacturing method thereof, and electronic device |
JP7323847B2 (en) * | 2020-02-26 | 2023-08-09 | 株式会社ソシオネクスト | Semiconductor integrated circuit device |
WO2024042698A1 (en) * | 2022-08-26 | 2024-02-29 | 株式会社ソシオネクスト | Semiconductor integrated circuit device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070267748A1 (en) * | 2006-05-16 | 2007-11-22 | Tran Tu-Anh N | Integrated circuit having pads and input/output (i/o) cells |
US20080111255A1 (en) * | 2006-11-09 | 2008-05-15 | Daisuke Matsuoka | Semiconductor integrated circuit and multi-chip module |
US20100155845A1 (en) * | 2008-12-19 | 2010-06-24 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US20100237509A1 (en) * | 2009-03-19 | 2010-09-23 | Faraday Technology Corporation | Io cell with multiple io ports and related techniques for layout area saving |
US7932744B1 (en) * | 2008-06-19 | 2011-04-26 | Actel Corporation | Staggered I/O groups for integrated circuits |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02246354A (en) * | 1989-03-20 | 1990-10-02 | Nec Corp | Master slice layout integrated circuit device |
JP3464802B2 (en) * | 1991-09-18 | 2003-11-10 | 株式会社東芝 | Semi-custom integrated circuits |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
JP3951090B2 (en) * | 2000-06-19 | 2007-08-01 | セイコーエプソン株式会社 | Semiconductor integrated circuit device and layout design method thereof |
TW511193B (en) * | 2001-12-13 | 2002-11-21 | Acer Labs Inc | Inner circuit structure of array type bonding pad chip and its manufacturing method |
JP2004296998A (en) * | 2003-03-28 | 2004-10-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US6798069B1 (en) * | 2003-03-28 | 2004-09-28 | Lsi Logic Corporation | Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors |
US7194707B2 (en) * | 2004-09-17 | 2007-03-20 | International Business Machines Corporation | Method and apparatus for depopulating peripheral input/output cells |
KR100699894B1 (en) * | 2006-01-31 | 2007-03-28 | 삼성전자주식회사 | Semiconductor chip improving a layout of ESD protection circuit |
JP2007305822A (en) * | 2006-05-12 | 2007-11-22 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit |
JP2007335511A (en) * | 2006-06-13 | 2007-12-27 | Fujitsu Ltd | Design method for semiconductor integrated circuit device, semiconductor integrated circuit device and manufacturing method therefor |
JP5264135B2 (en) * | 2006-11-09 | 2013-08-14 | パナソニック株式会社 | Semiconductor integrated circuit and multichip module |
JP2009164195A (en) * | 2007-12-28 | 2009-07-23 | Panasonic Corp | Semiconductor chip |
JP2012235048A (en) * | 2011-05-09 | 2012-11-29 | Renesas Electronics Corp | Semiconductor device |
-
2013
- 2013-09-24 JP JP2015534591A patent/JP2015532530A/en active Pending
- 2013-09-24 EP EP13842574.9A patent/EP2901477A4/en not_active Withdrawn
- 2013-09-24 WO PCT/US2013/061317 patent/WO2014052274A1/en active Application Filing
- 2013-09-24 KR KR1020157008651A patent/KR20150058273A/en not_active Application Discontinuation
- 2013-09-24 CN CN201380050485.9A patent/CN104781924A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070267748A1 (en) * | 2006-05-16 | 2007-11-22 | Tran Tu-Anh N | Integrated circuit having pads and input/output (i/o) cells |
US20080111255A1 (en) * | 2006-11-09 | 2008-05-15 | Daisuke Matsuoka | Semiconductor integrated circuit and multi-chip module |
US7932744B1 (en) * | 2008-06-19 | 2011-04-26 | Actel Corporation | Staggered I/O groups for integrated circuits |
US20100155845A1 (en) * | 2008-12-19 | 2010-06-24 | Renesas Technology Corp. | Semiconductor integrated circuit device |
US20100237509A1 (en) * | 2009-03-19 | 2010-09-23 | Faraday Technology Corporation | Io cell with multiple io ports and related techniques for layout area saving |
Non-Patent Citations (1)
Title |
---|
See also references of WO2014052274A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2014052274A1 (en) | 2014-04-03 |
CN104781924A (en) | 2015-07-15 |
EP2901477A1 (en) | 2015-08-05 |
KR20150058273A (en) | 2015-05-28 |
JP2015532530A (en) | 2015-11-09 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 20150428 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
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AX | Request for extension of the european patent |
Extension state: BA ME |
|
DAX | Request for extension of the european patent (deleted) | ||
RA4 | Supplementary search report drawn up and despatched (corrected) |
Effective date: 20160602 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 27/118 20060101ALI20160527BHEP Ipc: H01L 23/60 20060101ALI20160527BHEP Ipc: H01L 27/04 20060101ALI20160527BHEP Ipc: H01L 23/00 20060101ALI20160527BHEP Ipc: H01L 27/02 20060101ALI20160527BHEP Ipc: H01L 21/822 20060101ALI20160527BHEP Ipc: H01L 23/50 20060101ALI20160527BHEP Ipc: H01L 21/82 20060101AFI20160527BHEP Ipc: H01L 23/528 20060101ALI20160527BHEP |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20190402 |