Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
  • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
  • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present application relates to the field of electrical test devices for interconnection elements in a microelectronic device making it possible to check the electrical continuity and / or the electrical characteristics of the interconnection elements passing through a support, in particular vertical type interconnection elements or TSVs, as well as a method of electrical testing of interconnection elements.
• connection elements of the type commonly called “TSV” (TSV for "Through Silicon Via” or through silicon) are generally provided. These connection elements at least partially cross the thickness of a substrate and optionally one or more plates or supports stacked above this substrate.
• a TSV interconnection element is generally formed of at least one conductive portion passing through a support, for example a substrate or a chip or a plate, this conductive portion being provided with at least a first end emerging on one of the faces of the support. , and a second end that can be buried in the thickness of the support or lead to another face of the support, opposite that on which the first end opens.
• the number of tests to be performed is greater than for devices formed of a single plate.
• TSV Thinough Silicon Via
• WO 2011/101393 A1 discloses an electrical test system for a microelectronic device having TSV interconnection elements passing through a substrate and having an end connected to a conductive layer, which may be in the form of a conductive polymer. and makes it possible to establish a short circuit between all the interconnection elements crossing the substrate.
• the present invention relates to an electrical test device or system of a microelectronic device having at least a first plurality of interconnection elements passing through a substrate, the interconnection elements having a first end disclosed at a level of a first face of the substrate and connected to removable connection means, the removable connection means being arranged on the first face and making it possible to establish a temporary short circuit between a plurality of said interconnection elements, the second end of the elements interconnection device being connected to a test circuit, the test device further comprising means for applying to said interconnection elements, at least one electrical connectivity test signal, simultaneously between a plurality of interconnection elements of said first plurality of interconnecting elements and to collect i of said test circuit a signal in response to said connectivity test signal,
• the removable connection means comprise a handle support provided with a plurality of distinct conductive zones, said conductive zones being assembled to said substrate by means of a layer of anisotropic conductive adhesive and arranged opposite interconnection elements. said substrate.
• anisotropic conductive adhesive is meant that this adhesive has electrical conduction properties only in a preferred direction z, for example orthogonal to the main plane of the substrate, while allowing to implement an electrical insulation in a xy plane (the xy plane realizing a non-zero angle with the direction z and can be in particular orthogonal to the direction z), for example parallel to the main plane of the substrate.
• a conductive zone of the handle support covered by this anisotropic conductive adhesive may be in electrical contact with a plurality of said interconnection elements of the substrate, without being electrically connected to the other conductive zones of the handle support.
• an electrical test can be performed simultaneously on several of said interconnection elements without necessarily having to simultaneously test all the interconnection elements of the microelectronic device.
• the anisotropic conductive adhesive may be formed of a dielectric or weakly conductive material, having adhesive properties, and traversed by conductive elements or inserts which protrude from this dielectric material.
• the conductive elements may be in the form of micro or conductive nanowires, or carbon nanotubes.
• connection means disposed on the first face makes it possible in particular to reduce the size of the device once the test has been performed, and to eliminate the connection between said interconnection elements when the microelectronic device is no longer subjected to a test.
• the test circuit can be integrated with the microelectronic device.
• test circuit is in particular integrated with said substrate.
• this test circuit may comprise at least one logic gate, in particular means forming an OR logic gate or an AND logic gate, connected to interconnection elements of said first plurality of elements. interconnections. It is thus possible to implement a test device with simple logic functions and having a limited space requirement.
• the test circuit may furthermore comprise load means or output pulling means of said logic gate, to force the output of the logic gate to a given potential.
• Polarization means for applying a given potential to the removable connection means are also provided.
• the conductive zones of the handle support may optionally be polarized respectively with different potentials.
• non-stick areas may also be provided.
• non-stick areas may correspond to localized regions of the anisotropic conductive adhesive whose adhesion has been reduced or eliminated.
• the present invention also relates to an electrical test method for interconnection elements comprising steps of:
• FIG. 1 represents a first example of an electrical test device for interconnections formed of conductive elements passing through a substrate and having an end connected to an electrical test circuit and another end connected to means producing, temporarily, an electrical connection of at least a plurality of said conductive elements;
• FIG. 2 illustrates a second example of an electrical test device, in which chips formed on a substrate are provided with conductive elements passing through the substrate and connected via one of their ends at an electrical test circuit, said conductive elements having another end connected to a removable connection island and temporarily disposed against the substrate during the duration of an electrical test;
• FIG. 3 illustrates a third example of an electrical test device, in which several chips formed on a substrate each have a plurality of conductive elements passing through the substrate and each associated with an electrical test circuit, one or more of said test circuits being connected together;
• FIG. 4 illustrates an example of an electrical test device for interconnection elements of the TSV type connected to both a temporary connection island and an integrated electrical test circuit, this test circuit being associated with a circuit evaluation;
• FIGS. 5, 6, 7 illustrate various examples of electrical test devices for TSV type interconnection elements connected to a test circuit carrying out a logic function
• FIG. 8 illustrates an example of an electrical test device for series of test type TSV interconnection elements carrying out a logic function
• FIG. 9 illustrates an example of a particular arrangement of an electrical test device
• FIG. 10 illustrates an arrangement of removable connection islands intended for carrying out an electrical test on TSV type interconnection elements of a microelectronic device, the connection islands being provided for connecting a plurality of connection elements. a TSV type interconnection during an electrical test phase (s) and intended to be withdrawn once this test phase (s) has been completed;
• FIGS. 11A-11C illustrate an example of implementation of a method of manufacturing connection islands intended for carrying out an electrical test on TSV type interconnection elements
• FIG. 12 illustrates an example of an electrical interconnection test device in which interconnecting conductive elements crossing a substrate and having an end connected to an electrical test circuit have another end connected to a conductive area of a handle support for temporarily providing an electrical connection between at least a plurality of said interconnecting conductive elements, the handle support and the substrate being assembled through anisotropic conductive adhesive;
• FIG. 13 illustrates an example of a device similar to that of FIG. 12, but in which the handle support is covered with non-stick zones to facilitate subsequent removal of the handle support.
• FIG. 1 A first example of a device for implementing electrical test (s) on one or more TSV-type interconnection elements arranged in a chip is given in FIG.
• a chip 102 has interconnection elements 107a, 107b, 107c of the TSV type at least partially traversing the thickness of a support.
• This support can be in particular a semiconductor substrate, on which or from which the chip 102 is formed.
• connection elements 107a, 107b, 107c comprise a conductive portion or a conductive area crossing the thickness of the semiconductor substrate.
• This conductive portion may for example be in the form of a pillar, possibly in contact with one or more conductive layers called “redistribution" and / or with one or more conductive balls.
• the conductive portion may be metallic and for example based on copper or aluminum, or comprise a conductive material based on silver, or gold, or titanium or tin.
• the connection elements 107a, 107b, 107c may each be surrounded by an area of dielectric material for providing isolation from the substrate.
• the semiconductor substrate 100 may have been thinned and have a thickness for example between 1 and 200 micrometer.
• connection element or elements 107a, 107b, 107c is connected to a circuit of test 116.
• connection element or elements 107a, 107b, 107c is in contact with a connection island 115.
• connection island 115 makes it possible to establish an electrical contact between the interconnection elements 107a, 107b, 107c or between several of the interconnection elements 107a, 107b, 107c.
• connection island 115 is also removable, that is to say it can be dissociated or disassembled from the chip 102, and in particular without damaging the latter.
• the connection island 115 may thus be provided to be temporarily assembled with the chip 102 during the duration of one or more electrical tests carried out on the TSV elements 107a, 107b, 107c.
• the device is represented in the test phase, when the connection island 115 is connected to the elements 107a, 107b, 107c TSV.
• the connection island 115 is preferably removed.
• the test circuit 116 may be integrated with the chip 102 and formed of so-called “front-end-of-line” (FEOL) or “front end” elements, in particular transistors, as well as elements so-called “back-end-of-line” (BEOL) or “back end”, in particular metal interconnections.
• FEOL front-end-of-line
• BEOL back-end-of-line
• the test circuit 116 may be provided to make a connection with each individual TSV-type interconnection element 107a, 107b, 107c and / or to make a connection with a group of interconnection elements 107a. 107b, or 107b-107c, or 107a-107c, or with the set 107a-107b-107c of all the interconnection elements TSV of the chip 102.
• an electrical test can be performed on a group of interconnection elements 107a-107b, or 107b-107c, or 107a-107c, or on all of the interconnection elements TSV of the chip 102.
• This test can be in particular that of the electrical conductivity of the interconnection elements 107a, 107b, 107c.
• the test circuit 116 may also be associated with DFT elements or at least one DFT circuit (DFT for "Design for Test” or “Design for Testability”, for example a DFT circuit using a test technique as described in the document "Scan Chain Design for Test Time Reduction in Core-Based ICs” Joep Aerts and Erik Jan Marinissen, IEEE Test Conference, 1998.
• DFT Design for Test
• Design for Testability for example a DFT circuit using a test technique as described in the document "Scan Chain Design for Test Time Reduction in Core-Based ICs” Joep Aerts and Erik Jan Marinissen, IEEE Test Conference, 1998.
• the DFT circuit may be formed of logic blocks temporarily connected during a test phase, through which a data string is passed which will be outputted to ensure the continuity and functionality of the logical blocks.
• FIG. 1 A second example of an electrical test device is illustrated in FIG. 1
• a chip 202 is provided with a first set of connection elements 107a, 107b, 107c crossing at least a portion of the thickness of a substrate on which this chip is formed, these interconnection elements 107a. , 107b, 107c being connected on one side of the substrate to a first integrated test circuit 116, and on the other side of the substrate to a first connection island 115 temporarily assembled with the chip 202.
• the chip 202 also has a second set of connection elements 207a, 207b, 207c passing through at least a portion of the thickness of the substrate and juxtaposed to the first set of connection elements 107a, 107b, 107c.
• the connection elements 207a, 207b, 207c have one end connected to a second test circuit 216 and the other end to a second connection island 215 temporarily attached to the chip 202.
• the first connection island 115 and the second connection island 215 are also removable and can be removed from the face of the substrate on which the connecting elements 107a, 107b, 107c, 207a, 207b, 207c open.
• the first test circuit 116 and the second test circuit 216 are connected to each other via an interconnection line 226, which may for example be one of the metal lines of the chip 202 parallel to the substrate 100. and belonging to the back-end area of the chip 202.
• the first test circuit 116 and the second test circuit 216 may be configured such that one or more elements of the first set of interconnection elements 107a, 107b, 107c are capable of being connected to one or more elements of interconnection of the second set of interconnection elements 207a, 207b, 207c.
• the test circuitry 116 and 216 may be configured to select and connect a plurality of TSV type interconnection elements 107a, 107b, 107c of the first set with a plurality of one of the network interconnection elements 207a, 207b, 207c. TSV type of the second set.
• a series linkage of pairs of interconnection elements TSV can thus be realized.
• FIG. 3 illustrates a variant of the previously described device example, for which a logic circuit 228 or a set of logic circuits 228 is provided between the first test circuit 116 and the second test circuit 216 and connected thereto.
• the logic circuit 228 or the logic circuit assembly 228 may be provided with a functional logic block of the type commonly called “intellectual property" or IP, possibly associated with one or more elements of the DFT type.
• FIG. 12 illustrates another variant of one or the other of the examples described above, in which a removable connection island 315 is in the form of a substrate or handle support 130, provided with a first conducting zone 131, and a second conductive zone 132, the first conductive zone 131 making it possible respectively to electrically connect the elements 107a, 107b, 107c of the first set of interconnection elements, while the second conductive zone 131 makes it possible to electrically connect the elements 207a, 207b, 207c of the second set of interconnection elements.
• the conductive zones 131, 133 have an arrangement that depends on that of the interconnection elements 107a, 107b, 107c, 207a, 207b, 207c in the chip 202.
• the assembly of the handle support 130 to the chip 202 is carried out by means of an anisotropic conductive adhesive 341 which can be formed, for example according to a technique presented in the document CN1821336, by mixing conductive particles with nanoparticles of filling called " filler ", the mixture is combined with an epoxy resin and a slow crosslinking agent. Due to the anisotropic conductive nature of the glue 341, the conductive areas 131, 133 of the handle support are not electrically connected to each other.
• the anisotropic conductive adhesive 341 is disposed on one side of the handle support 130 on which conductive areas 131, 133 are arranged.
• anti-adhesive areas 137 are provided to facilitate subsequent disassembly between the chip 202 and the handle support 100.
• the adhesive zones 137 may correspond to regions of the adhesive 341 whose adhesion properties have been reduced or eliminated. This can be achieved by exposing regions of the glue to a chemical process which reduces its adhesion, as described, for example, in the method published in "Ultrathin Wafer Handling in 3D Stacked IC Manufacturing Combining" Novel ZoneBOND TM Temporary Bonding Process with Room Temperature Peel Debonding ", 3DIC Proceedings, 2011.
• test circuit 116 may be provided for injecting a current or applying a potential or measuring the current or the potential at one or more end (s) of the connection elements 107i, ..., 107 N of the TSV type.
• a potential may optionally be applied to means 115 through 107 N , for example, to interconnect the other interconnection elements 107 1 to 107 N 1 in order to bias another end of the other connection elements 107 1 to 107 N _i of type TSV.
• the electrical test device is also provided with an evaluation circuit 117 connected to one or more pins 111 of input and / or output of the test.
• This evaluation circuit 117 is adapted to indicate a possible presence of functional or parametric errors.
• the circuit 117 may be provided for estimating, for example, the electrical continuity of each TSV element by means of a current or an electric potential characterizing each TSV.
• This evaluation circuit may for example be formed of a comparator which compares an output of the device of FIGS. 5, 6 and 7 to an expected value.
• test device embodiment comprising a test circuit 116 provided with means 121 for performing a connectivity test of the TSV type 107i 107 N interconnection elements is given.
• a potential V is applied to TSV-type connection elements 107i 107 N _i via a connection island 115 polarized through 107 N.
• the means 121 implementing a connectivity test function may be provided to indicate, for example, whether all the connection elements 107 TSV are placed at the same potential or not.
• Load or pull means 191 may be further connected to the output of the test circuit 116, in order to force this output to a determined potential.
• the signal at the output of the test circuit 116 may be delivered to an evaluation circuit.
• multiplexers 111 N LLLI elements respectively associated with the connecting elements 107i 107 N are provided for enable alternatively connecting one end of the connection elements
• connection elements 107i 107 N TSV are in electrical test mode, or in normal operation mode.
• the means 121 carrying out the connectivity test function may comprise means 123 forming an "AND" logic gate and a polarization pad 137.
• pulling means 193 commonly called “pull up”, for example in the form of one or more transistors and / or resistors connected to a power supply, may be arranged at the output of the test circuit 116, and force this output to state '1' or high.
• the means 121 carrying out the connectivity test function may comprise means 125 forming an "OR" logic gate and a polarization pad 197.
• a potential V equivalent to a logical '0', and a result of this test function output S of the circuit 116 is taken.
• this output result S is a logic 0, it can be deduced that all the elements TSV 107 are conductive. In the case where a floating signal is taken out, then at least one of the elements TSV 107 is not conductive.
• pulling means 195 of the commonly known type for example in the form of one or more transistors and / or pull-down resistors connected to ground, can be arranged in output of the test circuit 116, and force this output to a low state or ⁇ '.
• an arrangement comprising cascaded logic gates with interposed DFT test logic circuits can be implemented.
• connecting elements TSV 107a, ..., N 107, 207a, 207 N are disposed in series and tested via means 118, 218 of scan chain control commonly called "scan chain”.
• a first series of TSV elements 107a, ..., 107 N connected via a connecting block 115 are connected to a series of other TSV elements 207a, ..., 207 connected N another input island 215.
• a multiplexer 126, 226 which connects this series to a scanning chain or to an electronic circuit, depending on the state of the device.
• a logical selector (not shown).
• a flip-flop 129 for saving information, can be connected to the multiplexer 226 arranged at the input of a subsequent series of elements TSV.
• this sequence is correct, then it can be concluded that none of the elements TSV is defective. If this sequence is modified or attenuated, with respect to the sequence injected at the input, it can be deduced that at least one element TSV is faulty.
• An interconnection element 107a has one end opening on the underside of the substrate 100 and another end disposed in the thickness of the substrate 100, but connected via a horizontal conductive line 127 to a conductive pad 129 formed on the upper face of the substrate 100.
• a substrate 100 comprising several chips 102a, 102b each having a plurality of interconnection elements TSVs (not shown) are connected to conductive areas 131, 132, 133, 134 disposed on a temporary handle support 130.
• the support 130 handle may for example be a plate based on silicon or glass, to ensure a rigid holding of the test device and may also be provided with a size similar to that of the semiconductor substrate 100 thinned on which the chips 102a, 102b are formed.
• An anisotropic conductive adhesive 141 is provided between the handle support 130 and the substrate 100 to provide an anisotropic electrical assembly and conduction, that is to say in a preferential conduction direction which, in this example, achieves an angle of zero, in particular 90 °, with a plane parallel to the main plane of the support 130 or the substrate 100 (the main planes of the support 130 and the substrate being planes passing respectively by the support and the substrate and parallel to the plane [O; i; j] of the reference [O; i; j; k] given in FIG. 10).
• the conductive adhesive 141 of anisotropic type may have been formed of a weakly conductive adhesive material to which conductive particles passing through the material, for example metallic nanowires or nanoparticles or carbon nanochannels have been added.
• the assembly example illustrated in FIG. 10 can be temporarily maintained during one or more electrical test phases of the interconnection elements arranged in the chips 102a, 102b formed in the substrate 100.
• the support 130 and the substrate 100 can be disassembled.
• the handle 130 and the connection islands 115 can thus be detached from the substrate 100.
• This can be achieved by etching the conductive adhesive 141.
• the anisotropic conductive adhesive 141 can be based on a polymer which can be etched chemically or by plasma in a selective manner with respect to the substrate 100 and the support 130.
• FIGS. 11A-11C illustrate an example of a method for producing islands for connection and assembly of these connection islands with a microelectronic device equipped with interconnection elements of the TSV type.
• a metal layer is formed in which patterns are made, for example using photolithography or screen printing steps, in order to form metal zones 133.
• the metal zones 133 realized have an arrangement which depends on that of TSV interconnection elements in a microelectronic device with which the handle support 130 is intended to be assembled (FIG. 11A).
• This microelectronic device is formed of a semiconductor substrate 100 in which the interconnection elements TSV are arranged (the interconnection elements TSV not being shown in FIGS. 11A-11C).
• the substrate 100 and the handle support 130 are assembled, so that one face of the substrate 100 through which one end of the interconnection elements opens out, is covered with a layer of anisotropic conductive adhesive 141.
• the face of the substrate 100 covered with the anisotropic conductive adhesive 141 is then brought into contact with that of the support 130 on which the metal areas 133 are arranged.
• the anisotropic conductive adhesive 141 formed on the handle support 130 can have a thickness for example between several micrometers and several tens of micrometers.
• This conductive adhesive 141 may for example be based on an insulating polymer mixed with metal nanoparticles or nanowires or nanotubes.
• connection islands 115 formed of an anisotropic conductive adhesive layer 141 in contact with at least one metal zone 133 are made (FIG. 11C).
• a mechanical or optical alignment is implemented to ensure the alignment of the metal areas 133 with the TSV elements.
• the support 130 is removed for example by a chemical etching of the glue 141.
• the substrate 100 is recovered and can be glued on a thick adhesive ensuring a certain rigidity despite the small thickness of the substrate 133 .
• the connection islands are arranged on a handle support 130 which also has the role of giving the assembly rigidity during the electrical test or tests to be performed later on the microelectronic device.

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• Automation & Control Theory (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Tests Of Electronic Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)

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