Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0079—Receiver details
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/028—Arrangements specific to the transmitter end
  • H04L25/0286—Provision of wave shaping within the driver
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0091—Transmitter details
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
  • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
  • H04L2007/047—Speed or phase control by synchronisation signals using special codes as synchronising signal using a sine signal or unmodulated carrier

Definitions

• the invention relates to a receiving arrangement for a control device in a vehicle according to the preamble of independent claim 1 and an associated method for generating a synchronization pulse according to the preamble of independent claim 10.
• peripheral sensors for occupant protection systems mostly use power interfaces (e.g., PAS4, PSI5).
• power interfaces e.g., PAS4, PSI5
• PSI5 current interfaces
• a power clock in the form of a voltage pulse is generated by the central control unit (ECU), which is detected by the sensors on the bus and marks the beginning of a new cycle for data transmission.
• This voltage pulse is called a synchronization pulse and is generated with the aid of current sources and current sinks, which charge or discharge the bus load. Typically, this voltage pulse is repeated every 500 ⁇ .
• a trapezoidal synchronization pulse P T shown in FIG. 3 is generally used with a predetermined edge steepness.
• the edge steepness is between a slope of a first Characteristic curve representing a lower limit Vu and an edge subunit of a second characteristic representing an upper limit Vo.
• EMC electromagnetic radiation
• German Offenlegungsschrift DE 10 2009 001 370 A1 describes a receiving device for receiving current signals, a circuit arrangement having such a receiving device, and a method for transmitting current signals via a bus system.
• the receiving device described comprises at least two bus connection devices for receiving current signals from a plurality of transmitters, each bus connection device being designed for connection to at least one bus connection in each case, and a control device for outputting synchronization pulses to the bus connection devices for synchronizing the transmitters.
• the bus connection devices output the synchronization pulses with at least one time offset to the several transmitters, the synchronization pulses each having a trapezoidal shape with rounded corners.
• the receiving arrangement according to the invention for a control unit in a vehicle having the features of independent patent claim 1 and the method according to the invention for generating a synchronization pulse having the features of independent claim 10 have the advantage that the sinusoidal design of the synchronization pulse within the predetermined limits the lowest possible electromagnetic radiation, in particular in the spectral range of signal transmission (100 kHz to 300 kHz), can be achieved.
• the essence and advantage of the invention is not only to round off the corners of the synchronization pulse, but to optimize the whole shape in such a way, that the electromagnetic radiation is limited as possible to the range of the fundamental waves of the synchronization pulse.
• Embodiments of the present invention provide a receiver assembly for a controller in a vehicle having a voltage generator for generating a synchronization pulse that generates the synchronization pulse within predetermined specification limits having a predetermined shape and timing.
• the receiving arrangement outputs the synchronization pulse for synchronization of a signal transmission via a data bus to at least one sensor.
• the voltage generator comprises a voltage amplifier which generates the synchronization pulse essentially as a sine oscillation based on a reference voltage.
• a method for generating a synchronization pulse for synchronizing a subsequent signal transmission between a receiving arrangement and at least one sensor via a data bus in a vehicle is proposed.
• the synchronization pulse is generated within predetermined specification limits with a predetermined shape and a predetermined temporal behavior and transmitted from the receiving device to the at least one sensor.
• the synchronization pulse is generated essentially as a sine oscillation based on a reference voltage.
• the synchronization pulse can preferably be transmitted from the receiving arrangement to the at least one sensor before or at the beginning of the signal transmission between the at least one sensor and the receiver arrangement.
• a first voltage supply can provide a supply voltage for the voltage amplifier.
• a second voltage supply supply voltages for the digital drive circuit, the digital-to-analog converter and provide for at least one other circuit, which is connectable to the data bus.
• a first switching unit can separate the at least one further circuit from the data bus, and a second switching unit can connect the voltage amplifier to the data bus.
• the first and second switching units can be implemented, for example, as a changeover switch.
• control of the voltage amplifier can be completely outsourced to the digital part of the circuit, which can lead to an area-efficient solution due to the ever more progressive scaling of semiconductor technology.
• the at least one further circuit of the receiver arrangement can be disconnected from the data bus during the synchronization pulse, while the voltage generator is activated to generate the synchronization pulse and coupled to the data bus.
• a common voltage supply can provide a supply voltage for the voltage amplifier, the digital control circuit and the digital-to-analog converter. Furthermore, the voltage amplifier can provide the supply voltage for at least one further circuit, which is connected to the data bus.
• the supply voltage of the voltage amplifier can be set higher than a maximum amplitude of the synchronization pulse.
• the voltage amplifier can be operated with a voltage that is greater than the maximum amplitude of the synchronization pulse.
• the voltage amplifier follows with its output voltage of the form of the reference voltage from the digital-to-analog converter.
• An important feature of the amplifier is a high drive capability with appropriately sized power amplifiers. This means that the voltage amplifier or power amplifiers are capable of providing a sufficiently high current to enable the desired shape of the synchronization pulse without signal dips and signal distortions.
• the digital drive circuit can store and / or calculate the predetermined shape and the predetermined temporal behavior of the synchronization pulse, wherein the digital drive circuit can output corresponding digital data words to the digital-to-analog converter.
• the digital-to-analog converter generates from the N-bit data word a reference voltage, which is supplied to the voltage amplifier. The resolution of the data word can be selected for reasons of radiation so that the synchronization pulse can be imaged without significant jumps.
• FIG. 1 shows a schematic block diagram of a sensor arrangement with a first exemplary embodiment of a receiver arrangement according to the invention for a control device in a vehicle which generates and outputs an optimized synchronization pulse.
• FIG. 2 shows a schematic block diagram of a sensor arrangement with a second exemplary embodiment of a receiver arrangement according to the invention for a control unit in a vehicle, which generates and outputs an optimized synchronization pulse.
• Fig. 3 shows a schematic representation of the shape and the temporal behavior of a conventional trapezoidal synchronization pulse within predetermined limits.
• Fig. 4 shows a schematic representation of the shape and the temporal behavior of a conventional rounded trapezoidal synchronization pulse within the predetermined limits.
• FIG. 5 shows a schematic representation of the shape and the temporal behavior of an inventively optimized synchronization pulse within the predetermined limits.
• FIG. 6 shows a schematic illustration of a reference voltage during a synchronization pulse optimized according to the invention.
• FIG. 7 shows a schematic representation of an output voltage of the voltage generator during a synchronization pulse optimized according to the invention.
• the illustrated sensor arrangements 1, 1 ' comprise a data bus 5, at least one sensor 7 and in each case an embodiment of a receiving arrangement 3, 3' according to the invention for a control unit in a vehicle.
• the receiving arrangements 3, 3 'according to the invention each comprise a voltage generator 30, 30 'for generating a synchronization pulse P S ync.
• the voltage generator 30, 30 ' comprises a voltage amplifier 36, 36' which generates the synchronization pulse P sy nc essentially as a sine oscillation based on a reference voltage U re f.
• the voltage generator 30, 30 'generates the synchronization pulse P sy nc within predetermined specification limits Vo, Vu having a predetermined shape and a predetermined time behavior.
• the receiving arrangement 3, 3 outputs the synchronization pulse P syn c for synchronization of a subsequent signal transmission via a data bus 5 to at least one sensor 7.
• the illustrated synchronization pulse P S ync has a specific shape and a specific temporal behavior for all possible bus configurations and under all possible operating conditions. As is further apparent from Fig.
• the synchronization pulse P syn c has a slope which is given by the slope of a first characteristic representing the lower limit Vu and the slope of a second characteristic representing the upper limit Vo , Due to the sinusoidal or sinusoidal shape of the synchronization pulse P syn c in the predetermined limits Vu, Vo optimized so that the lowest possible electromagnetic radiation, especially in the spectral range of the signal transmission (100kHz to 300kHz) can be achieved, which in the range of the fundamental waves of Synchronization pulse P syn c remains limited.
• the voltage generator 30, 30 ' comprises a digital drive circuit 32, 32' and at least one digital-to-analog converter 34, 34 ', which generate and supply a substantially sinusoidal reference voltage U r ef output the voltage amplifier 36, 36 '.
• a sinusoidal reference voltage U re f is shown by way of example in FIG.
• the illustrated embodiments allow a very robust realization of the synchronization pulse P syn c and a reduced electromagnetic
• the illustrated first exemplary embodiment of the receiving arrangement 3 comprises a first voltage generator 30 having a first digital drive circuit 32 and a first digital-to-analog converter 34 which generate the substantially sinusoidal reference voltage U ref and output to a first voltage amplifier 36.
• a first power supply 3.1 provides a supply voltage for the first voltage amplifier 36
• a second power supply 3.2 provides supply voltages for the first digital drive circuit 32
• the first digital analog converter 34 and at least one further circuit 3.3 is available, which can be connected via a first switching unit 3.4 to the data bus 5.
• the first switching unit 3.4 disconnects the at least one further circuit 3.3 from the data bus 5, and a second switching unit 38 connects the voltage amplifier 36 to the data bus 5.
• the form of the synchronization pulse P syn c is either in the digital part or is stored in the first digital drive circuit 32 or is calculated in the digital part or in the first digital drive circuit 32 by means of an algorithm.
• the first digital-to-analog converter 34 generates from the N-bit data word a reference voltage, which is the first voltage amplifier 36
• the resolution of the data word is chosen for reasons of radiation so that the synchronization pulse P syn c can be mapped without significant jumps.
• the first voltage amplifier 36 is supplied with a voltage which is greater than the maximum illustrated amplitude of the synchronization pulse P sync and follows with its output voltage U sy nc the shape of
• the illustrated second exemplary embodiment of the receiving arrangement 3 ' comprises a second voltage generator 30' having a second digital drive circuit 32 'and a second digital-to-analog converter 34', which converts the substantially sinusoidal reference voltage U ref generate and output to a second voltage amplifier 36 '.
• the second voltage amplifier 36 ' provides the supply voltage for at least one further circuit 3.3', which is connected to the data bus 5.
• the at least one further circuit 3.3 'of the receiving arrangement 3' is therefore not disconnected from the data bus 5 during the synchronization pulse P sy , whereby the two switching units 3.4, 38 from FIG. 1 can be dispensed with.
• the current bus voltage U Bus is provided by the second voltage supply 3.2 of the receiving arrangement 3 up to the start time ti.
• the first voltage amplifier 36 provides the data bus 5 with the output voltage U syn c.
• the first voltage generator 30 'initially assumes too great an initial voltage when generating the synchronization pulse P syn c, so that at the transfer point UP at the time t 1 a voltage ubenssprung from the normal bus voltage U Bu s up to the value provided by the first voltage amplifier 36 value of the synchronization voltage Usync can arise.
• the voltage at the transfer point UP jumps back down to the normal bus voltage U Bus -
• the first voltage generator 30 starts from too low an initial voltage when generating the synchronization pulse P syn c, so that at the transfer point UP at the instant ti a voltage jump from the normal bus voltage U Bus downwards can arise on the provided by the first voltage amplifier 36 value of the synchronization voltage Usync.
• the voltage at the transfer point UP jumps back up to the normal bus voltage U Bus -
• FIG. 10 shows the synchronization pulse ⁇ 5 ⁇ generated by the second exemplary embodiment of the receiving arrangement 3 ' according to the invention from FIG. 2.
• the voltage at the transfer point UP is also continuously from the provided by the second voltage amplifier 36 value of the synchronization voltage U syn c on the normal bus voltage U bus over.
• the second embodiment of the receiving device 3 is the form of the synchronization pulse P syn c deposited either in the digital part or in the first digital drive circuit 32 or is calculated in the digital part or in the first digital drive circuit 32 by means of an algorithm.
• the second digital-to-analog converter 34 'generates from the N-bit data word a reference voltage U r ef which is supplied to the second voltage amplifier 36'.
• the Resolution of the data word is chosen for reasons of radiation so that the synchronization pulse P sy nc can be mapped without significant jumps.
• the second voltage amplifier 36 ' is also supplied with a voltage which is greater than the maximum illustrated amplitude of the synchronization pulse P sy nc and follows with its output voltage U sy nc the shape of the reference voltage U r ef from the second digital-to-analog converter 34th
• An important feature of the second voltage amplifier 36 ' is a high drive capability with correspondingly dimensioned output stages. This means that the second voltage amplifier 36 'or the corresponding output stages are also able to provide a sufficiently high current to enable the desired shape of the synchronization pulse P syn c without signal collapses and signal deformations.
• Embodiments of the inventive method for generating a synchronization pulse P syn c for synchronizing a subsequent signal transmission between the receiving device 3, 3 'and at least one sensor 7 via a data bus 5 in a vehicle generate the synchronization pulse P sy nc within predetermined specification limits Vo, Vu with a predetermined form and a given temporal behavior.
• the synchronization pulse P syn c from the receiver assembly 3, 3' to the at least one sensor 7 is transmitted.
• the synchronization pulse P syn c is generated essentially as a sinusoidal oscillation based on a reference voltage U r ef.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Dc Digital Transmission (AREA)
• Amplifiers (AREA)
• Lock And Its Accessories (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Arrangements For Transmission Of Measured Signals (AREA)

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• 2012
  • 2012-02-06 DE DE102012201711A patent/DE102012201711A1/de not_active Withdrawn
• 2013
  • 2013-01-21 WO PCT/EP2013/051037 patent/WO2013117415A1/de active Application Filing
  • 2013-01-21 JP JP2014555145A patent/JP5986645B2/ja not_active Expired - Fee Related
  • 2013-01-21 US US14/376,826 patent/US9294261B2/en not_active Expired - Fee Related
  • 2013-01-21 EP EP13701241.5A patent/EP2813040A1/de not_active Withdrawn
  • 2013-01-21 KR KR1020147021665A patent/KR102016775B1/ko active IP Right Grant
  • 2013-01-21 CN CN201380008061.6A patent/CN104094569B/zh not_active Expired - Fee Related
  • 2013-02-04 TW TW102104116A patent/TWI648977B/zh not_active IP Right Cessation

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