EP2732459A1

EP2732459A1 - Monolithic integrated semiconductor structure

Info

Publication number: EP2732459A1
Application number: EP12740874.8A
Authority: EP
Inventors: Bernadette Kunert
Original assignee: NASP III/V GmbH
Current assignee: NASP III/V GmbH
Priority date: 2011-07-12
Filing date: 2012-04-25
Publication date: 2014-05-21
Also published as: CN103828020A; JP2014526145A; DE102011107657A1; EP3893267A2; CN108346556A; JP6057096B2; WO2013007229A1; SG10201509068WA; EP3893267A3; CN103828020B; KR20190040359A; KR20140045425A; CA3040529A1; CA2840897A1; TW201303968A; WO2013007229A9; US9196481B2; KR101970841B1; KR102107346B1; CA3040529C

Abstract

The invention relates to a monolithic integrated semiconductor structure containing the following layer structure: A) a substrate layer based on doped or undoped Si; B) optionally a layer having the composition B_xAl_yGa_zN_tP_v, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1, and v=0.9-1; C) a relaxation layer having the composition B_xAl_yGa_zIn_uP_vSb_w, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, and w=0-1, wherein w and/or u on the side facing layer A) or B) are/is less than, equal to or greater than on the side facing away from layer A) or B), and wherein v=1-w and/or y=1-u-x-z; D) optionally a layer for blocking misfit dislocations having the composition B_xAl_yGa_zIn_uP_vSb_wN_t, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1 and t=0-0.1; E) optionally a layer for the hetero offset having the composition B_xAl_yGa_zIn_uP_vSb_wN_tAs_r, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1, t=0-0.1 and r=0-1; and F) an arbitrary, preferably group III/V, semiconductor material, or a combination of several different arbitrary semiconductor materials, wherein the above stoichiometric indices for all group III elements always result in 1 in sum, and wherein the above stoichiometric indices for all group V elements likewise always result in 1 in sum.

Description

Monolithic integrated semiconductor structure

Field of the invention

The invention relates to a monolithic integrated semiconductor structure, which are suitable for the formation of integrated semiconductor devices based on the group III / V elements on a silicon substrate, a process for its preparation and their uses

Background of the invention and prior art

The invention of the integrated circuit based on silicon and silicon dioxide has in recent years

Decades of tremendous development in microchip processor technology or microelectronics. In an integrated circuit, i.a. n-channel and p-channel transistors for data processing in the so-called CMOS logic (English: Complementary metal oxide-semiconductor) interconnected. Transistors are essentially resistors that are controlled by an external gate voltage. In recent decades, the performance of integrated circuits has been improved by increasing miniaturization of the transistors and consequent increasing transistor density. Meanwhile, the individual structures of the transistor devices in the dimensions are so small that basic physical limits occur and further miniaturization does not improve the

Circuits leads.

CONFIRMATION COPY At this point, besides silicon and silicon dioxide. Meanwhile, new materials are used in the manufacture of integrated circuits whose

physical properties lead to an improvement in the functioning. ^', The use of III / V in the CMOS Halbleitermaterialieri Ua discussed technology.

Since the electron mobility of some III / V

Semiconductor materials is substantially higher than that of silicon and the efficiency or switching speed of n-channel transistors u.a. relevant to the

As determined by electron mobility, the use of III / V semiconductor materials as n-channel layers could lead to a significant improvement of the integrated circuits. Furthermore, the gate voltage through the

Application of III / V semiconductor materials can be reduced, which in turn reduces the energy consumption and hence the thermal insulation in the integrated circuits

reduced. Currently, various institutes, universities and companies are using III / V

Channel layers studied in silicon technology.

Which III / V semiconductor is optimal for integration on silicon is determined on the one hand by the fundamental properties of the semiconductor material, e.g. the electron mobility and the electronic band gap.

On the other hand, ultimately, compatibility must be mass production in silicon technology

be taken into account. Arsenic is essential Component of many III / V semiconductor mixed crystals.

Due to the high toxicity of arsenic, a possible use of arsenic-containing materials in large-scale industrial production requires expensive disposal of the arsenic-containing waste products.

In the integration of III / V semiconductor materials on silicon-based circuits is usually worked with the epitaxial process. In this epitaxial deposition process, the lattice constants of the crystalline semiconductor materials play a crucial role. The silicon substrate used or the

Carrier substrate in the silicon chip technology specifies the underlying lattice constant. However, most III / V high electron mobility semiconductor materials have a different lattice constant than silicon, which is usually larger. This difference in lattice constants leads to the epitaxial integration of III / V channel layers on silicon substrate

Formation of dislocations in the III / V semiconductor layer. These transfers are

Crystal defects that significantly affect the electronic

Properties of the semiconductor layer deteriorate. To ensure optimum material quality of the III / V channel layers, special III / V buffer layers are necessary. These buffer layers are defined by a special sequence of different III / V

Semiconductor materials and / or by a special

Production method. Furthermore, this may

Buffer layer should not be too thick, so that the compatibility in the III / V integration on silicon to the current CMOS process is guaranteed. Various buffer layers or adaptation layers are known, for example, from the document DE 103 55 357 A.

Technical problem of the invention

The invention is based on the technical problem of specifying an integrated monolithic semiconductor structure which integrates group III / V semiconductors on silicon substrates, fulfilling all electronic requirements while avoiding or reducing arsenic-containing wastes during production and optimizing adaptation of different lattice constants Silicon on the one hand and Group III / V semiconductors on the other.

Broad features of the invention

To solve this technical problem, the invention teaches a monolithic integrated semiconductor structure comprising the following layer structure: A) a doped or undoped Si carrier layer, B) optionally a layer having the composition B _x Al _y Ga _z N _t P _v , where x = 0 -0, l, y = 0-l, z = 0-l, t = 0-0, l and v = 0,9-l C) one

Relaxation layer with the composition B _x Al _y Ga _z In _u P _v Sb _w , where x = 0-0, l, y = 0-l, z = 0-l, u = 0-l, v = 0-l and w = 0-l, wherein w and / or u on the side facing the layer A) or B) is smaller, equal, or larger than on the side facing away from the layer A) or B) and within the Relaxation layer is variable or constant, and where v = lw and / or l = u + x + y + z, D) optionally a layer for blocking dislocations having the composition B _x Al _y Ga _z In _u P _v Sb _w N _t7 where x = 0-0, l, y = 0-l, z = 0-l, u = 0-l ,. v = 0-1, w = 0-l and t = 0-0, l, E) optionally a layer for

Hetero-offset of composition B _x Al _y Ga ₂ In _u P _v Sb _w N _t As _r where x = 0-0, l, y = 0-l, z = 0-l, u = 0-l, v = 0-l, w = 0-l, t = 0-0, l and r = 0-l, and F) any group III / V

Semiconductor material or the combination of several arbitrary semiconductor materials, wherein the above indices for all group III elements in the sum always 1 and where the above indices for all group V elements in the sum also always 1 result.

The basis of the invention is a novel combination of existing semiconductor materials and their

Further developments to an optimal buffer layer or adaptation layer for the integration of III / V

Devices and in particular channel layers

To realize silicon substrate.

The peculiarity of the invention lies in the realization of a phosphorus (P) -based and arsenic (As) -armen or As-free buffer layer, which at the same time by the

Addition of aluminum (Al) on the part of group III in the III / V semiconductor mixed crystal has the material property of a relatively large electronic band gap and on the buffer surface, the lattice constant of the n-channel layer with as low as possible

Has dislocation defect density. The invention has three decisive advantages over existing integration concepts:

1 . The lattice constants of (AlGa) P and silicon

differed only minimally. Accordingly, thin (BAlGa) (NP) layers with low boron or

Nitrogen concentration without the training of

Missing dislocations are epitaxially deposited on (001) silicon substrate. procedural

Challenges of the monolithic connection of III / V semiconductor mixed crystals and silicon due to the different crystal properties of both

Materials such as e.g. atomic bonding properties and lattice basis are solved in the growth of this first thin III / V semiconductor layer. Only in the next step is the targeted addition of antimony and indium increases the lattice constant and initiates the formation of false dislocations in a controlled manner.

By using a defect-free template, the total layer thickness of the III / V buffer layer can thus be significantly reduced, which in turn is crucial for compatibility with the existing CMOS process. Furthermore, thinner layers are more cost effective in production.

2. The band gap is a characteristic

Semiconductor material property depending on the

Material composition of the III / V crystal and its state of stress. Since the band gap of the III / V

Material of the n-channel layer is predominantly small, resulting in the interface between the buffer layer and the n-channel layer, a large hetero-offset in

Conduction and / or valence band of electronic

Band structure, if the buffer layer is a comparatively has large band gap. A large offset in the conduction band is again very advantageous for the functionality of an n-channel transistor. In particular, in this invention, a large hetero-offset to the n-channel layer is realized. 3. N-channel material systems with optimal device properties often contain arsenic. These

Channel layers, however, are very thin compared to the buffer layer, so it is crucial to reduce especially the arsenic concentration in the thick buffer layers. The application of a phosphorus-based buffer allows for the first time a significant reduction of arsenic-containing compound in industrial production. Thus, the cost of the expensive disposal of

arsenic waste products are drastically reduced.

This integration concept also exploits the fact that even thin (30-60 nm) boron-aluminum-gallium-nitride-phosphide ((BAlGa) (NP)) layers are defect-free and without crystal polarity disorder on exactly oriented (001) silicon Substrate can be deposited.

Thus, the necessary Puf can be ferschichtd ^'icke significantly reduced.

This (BGaAl) (NP) -Si template is thus used as a template for the invention. In the following, the buffer in the embodiment with compulsory layers C) to E) is divided into three visual packets (1-3 or layers C) to E)):

1. The first layer package (relaxation layer C) on the template preferably consists of different

Single layers, but can also be one layer consist. The composition of these (BAlGaln) (SbP)

Single layers is varied so that many

Forming false offset defects and the lattice constant is increased systematically. Furthermore you can

special annealing methods are used to promote the formation of false dislocations.

It is crucial that the realized lattice constant on the surface of the first layer package of the

Target grid constant for the integration of the channel layer corresponds.

2. In the second layer packet (layer D)), a mislocation blocking layer is realized. These

Blocking layer may consist of one or more

(BAlGaln) (PSbN) consist of single layers of different composition. These (BAlGaln) (PSbN) layers should prevent mislocation from the first layer packet to the upper III / V layers (layer packet 2 and 3 as well as the channel layer). Here, the stress state of the individual layers is selectively varied. However, it should not be generated further mislocations, accordingly, this

Single layers deposited pseudomorphically strained.

3. In the third layer package (hetero-offset, layer E), the optimal band gap as well as the optimal hetero-offset for the integration of the channel layer is realized. This last layer package can again consist of one or more (BAlGaln) (PSbNAs) layers. While the first two layer packages are arsenic-free, this last layer package may include a thin layer containing arsenic. This layer is however comparatively thin (<50nm), which gives the distinct advantage of this

Invention with respect. the arsenic-poor production is still preserved.

In particular, the following variants of the invention are preferred.

The layers C), D) and E) can in. Their

Compositions are selected with the proviso that the lattice constant of one of the layers D) and / or E) and / or the side facing away from the layer A) or B) of the layer C) substantially the lattice constants of

Layer F) corresponds.

Layer A) is on layer B) or C)

side facing preferably a Si (001) surface of a Si single crystal.

The individual layers preferably have the following features.

The layer B) may have a thickness of 5-100 nm, in particular 30-80 nm, for example 60 nm, and / or a p- or n-doping concentration of 1 × 10 ¹⁵ -1 × 10 ²¹ cm ^-3 , in particular 1 × 10 ¹⁵ -1 * 10 ¹⁷ cm ^-3 , for example 3 * 10 ¹⁵ cm ^-3 , preferably one of the following

Compositions: z = v = 1, x = y = t = 0 or y = v = 1, x = z = t = 0 or x = 0, 01-0, 1, y = 0.90-0.99 , z = t = 0, v = 1 or x = 0, 01-0, 1, z = 0.90-0.99, y = t = 0, v = 1 or t = 0, 01-0.1 , v = 0.90-0.99, y = x = 0, z = l. For example, it is GaP.

In layer C), w and / or u may be monotonically increasing or decreasing from the side facing layer A) or B) to the side facing away from layer A) or B) (if w and / or u on the layer A or B) facing side smaller or larger than on the

opposite side is). Here, the term "monotonically increasing / decreasing" means in mathematical rigor "strictly monotonically increasing / decreasing", considered as a function of w and / or u in a direction of a location coordinate which is orthogonal to the surface of the layer A) or B). Examples are linear, exponential, or any other monotone function. The term may also include functions in which the value of w and / or u may be partially constant depending on the location. An example of this is a (rising or falling) step function, which occurs when the layer C) is produced in partial layers. In principle, however, it is not excluded that w and / or u within the layer C) also has changing signs of the slope in subregions in a location-dependent concentration course. In particular, it is also possible for the function w or u to pass through maxima or minima as a function of said spatial coordinate whose maximum and minimum values are also higher or lower than the values of w and u on the two sides of the

Layer C) can be. However, it is also possible for the maximum or minimum values to be between the values of w and u on the two sides of the layer C). However, the layer C may also consist of a single layer having a constant composition.

As already mentioned, the layer C) may consist of a plurality of partial layers, in particular 1-30

Partial layers, preferably 2-10 partial layers,

For example, 6 sub-layers, be formed, w within a sub-layer in turn variable or

be constant (in the direction orthogonal to the surface of layer A) or B)). The layer C) may have a thickness of 1-500 nm, in particular 100-400 nm, for example 300 nm. Partial layers can each, equal or different, have a thickness of 5 to 500 nm, in particular 10 to 100 nm, for example 10 to 60 nm. The layer C) or their partial layers, partly or all, a p-type or n-Dotierkohzentration of 10 ¹⁵ -10 ²¹ cm ^{"have 3,} but also undoped. The layer C) or their partial layers ^■ (same or different) preferably has one of the following compositions: y = 1, x = z = u = 0, v = lw or x = z = 0, y = lu, v + w = 1 Examples are AlP _v Sb _w and Al _y In _u P or Al _y In _u P _v Sb _w The latter layer is particularly recommended as penultimate

Partial layer within a sub-layers of sub-layers otherwise having Al _y In _u P, based on the next layer above it. This penultimate sub-layer may, for example, have w = 0.08 and v = 0.92.

The layer D) will typically have a thickness of 1-150 nm and / or undoped and / or a p- or n-doping concentration of 10 ¹⁵ -10 ²¹ cm ^-3 . It may consist of a single layer or a plurality of

(same or different) partial layers, in particular 1-10 layers, preferably 2-5 layers, for example 2, be formed. The layer thicknesses of partial layers can be in the range 1 to 150 nm, for example 5 to 100 nm. The layer D) or its partial layers

(same or different) preferably have one of the following compositions: x = 0-0, l, y = 0.9-1, v = 0-0.7, w = 0.3-1, z = u = t = 0 or u = 1, w = 0-0, 5, v = 0.5-l, t = 0-0, 1, x = y = z = 0 or y = 1, v = 0-0.7 , w = 0.3-l, t = 0-0, l, x = z = u = 0 or u = 0.9-l, x = 0-0, l, v = 0.5-l, w = 0 - 0, 5, ^' y = z = t = 0.

The layer E) or its (for example 2 to 5)

Partial layers may have a thickness of 5-200 nm, in particular 10-100 nm or 10 to 50 nm. It can be 1 to 10, preferably 2 to 5, for example, 2, sublayers set up, of the same or different

Composition and / or thickness of the sublayers (thickness Partial layers: 5-200 nm). They or their Tei 1 layers may undoped and / or have a p or n-doping concentration of 10 ¹⁵ -10 ²¹ cm ^"3. The

Layer E) or its partial layers (same or

different) may preferably be one of the following

Compositions have: y = l, v = 0.2-0.5, w = 0.5-0.8, x = z = u = t = r = 0 or y = l, w = 0.4-0 , 8, r = 0.2-0.6, x = z = u = v = t = 0.

Doping, if established, can be carried out with the elements Si, Te, S, Zn, Mg, Be and / or C.

Doping reagents for use in the methods described below are, for example, diethyltellurium,

Dimethylzinc, diethylzinc, di-tertiarybutylsilane, silane, tertiarybutylsulphide, bis-cyclopentadienylmagnesium, or tetrabromomethane.

The invention further includes a method of making a monolithic integrated

Semiconductor structure according to one of claims 1 to 15, wherein on a layer A), optionally a layer B) is epitaxially grown on the layer A) or B) a layer C) is epitaxially grown on the layer C) optionally a layer D) and / or E)

is grown epitaxially; on layer C) or D) or E) the layer F) is epitaxially grown. One or more of the layers A), B), C), D), E), and / or F) may be p- or n-doped, but may also be undoped in particular.

In detail, a method according to the invention may comprise the following method steps: a substrate containing the layer A) is introduced into an epitaxy apparatus, in particular an organometallic-gas-phase epitaxy (MOVPE) apparatus, a carrier gas, preferably nitrogen or hydrogen, is carried along Educts in defined concentrations in accordance with predetermined composition of a layer A), B), C), D), and E), optionally F), or loaded their sub-layers, the loaded carrier gas is over the surface of a temperature in the range of 300 ° C to 800 ° C ,.

in particular 400 ° C to 625 ° C in the case of the layers C) and D) or their partial layers or 525 ° C to 725 ° C in the case of the layer E) or their sub-layers, heated substrate or on the surface of the uppermost layer on the Substrate for a defined exposure time, with total concentration of the starting materials and

Exposure duration are coordinated with the proviso that the semiconductor layer having a predetermined layer thickness on the surface of the substrate or the surface of the uppermost layer on the substrate

is formed epitaxially.

The layer C) can be grown in sub-layers and wherein between the growth of two sub-layers and / or after the growth of the last sub-layer, a baking of the substrate to 550 ° C to 750 ° C,

especially at 600 ° C to 725 ° C, can be done.

As starting materials can be used: C1-C5

Trialkylgallium, in particular triethylgallium (Ga (C2H ₅ ) 3),

Triters iarybutylgallium and / or trimethylgallium

(Ga (CH ₃ ) ₃ ) as Ga starting material, diborane (B ₂ H ₆ ) or C ₁ -C ₅

Trialkylborane, in particular triethylborane (B (021 * 5) 3) and

Tritertiarybutylborane and / or borane-amine adducts such as

Dimethylaminoborane as B-Edukt, Alan-amine adducts such.

Dimethylethylaminalan or C1-C5 trialkylaluminum, especially trimethylaluminum (AI (013) 3) and

Tritertiary butylaluminum as Al reactant, C1-C5

Trialkylindium, in particular trimethylindium (In (0 3) 3) as In-Edukt, phosphine (PH ₃ ) and / or C1-C5 alkylphosphine, in particular tert-butylphosphine (TBP) (t- (C4 H9) -PH ₂ ) as

P-Edukt, arsine (AsH ₃ ) and / or C1-C5 alkylarsine,

in particular tertiarybutylarsine (TBAs) (t- (C 4 H 9) -AsH ₂ ) and / or trimethylarsine (As (CH ₃ ) ₃ ) as As starting material, C 1 -C 5 trialkyl antimony, in particular triethylantimone (Sb (C 2 H 5) 3) and / or trimethyl antimony (Sb (CH ₃ ) ₃ ) as Sb starting material _;

Ammonia (NH 3), mono (C 1 -C 8) alkylhydrazine, in particular tertiarybutylhydrazine (t- (C 4 H 9) NH 2) and / or 1, 1-di (C 1-6)

C5) alkylhydrazine, in particular 1, 1-dimethylhydrazine

((CH ₃ ) ₂ -N-NH ₂ ) as N-reactant, where C3-C5 alkyl groups can be linear or branched.

Educts for the doping are: diethyltellurium (DETe), dimethylzinc (DMZn) _. , Diethylzinc (DEC),

Di-tertiarybutylsilane (DitButSi), silane,

Di-tertiarybutyl sulphide, bis-cyclopentadienyl magnesium, tetrabromomethane.

The total pressure of carrier gas and educts can be in the range of 10 to 1000 hPa, in particular 50 to 500 hPa,

be set, wherein the ratio of the sum of the partial pressures of the educts to the partial pressure of the carrier gas is between l * 10E-6 to 0.5, and wherein the

Separation rate 0.01 to 10 μηη / h, in particular 0.05 to 5 μηη / h, is.

The invention thus also includes a new one

Epitaxy method in which the use of

organometallic group-V starting substances the

Application of extremely low deposition temperatures allowed. Low crystal growth temperatures are particularly important in order to realize the lattice mismatch in a very thin buffer layer. Since these organometallic group V precursors such as TBAs and TBP are liquid at room temperature, the handling in the production is much safer than the use of the usual gaseous and highly toxic starting substances Arsine and phosphine. In addition, the maintenance times of epitaxy machines can be reduced because parasitic

Deposits in the raw exhaust system are significantly reduced. Overall, this novel epitaxy process thus offers significant economic benefits in the

Mass production.

Finally, the invention relates to the use of a semiconductor structure according to the invention for the production of a III / V semiconductor device, such as a semiconductor device. a III / V channel transistor on a silicon substrate, wherein the III / V channel of the transistor preferably forms the layer F) and is epitaxially grown, as well as a

Semiconductor structure obtainable by a method according to the invention according to one of the claims.

The comments on the semiconductor structure according to the invention are analogous to the method and vice versa

applicable.

Of independent importance is also a combination of the layers C), D) and E) according to the claims

together as a buffer layer, regardless of the characteristics of the other layers according to the claims.

In the following, the invention is based on not

limiting embodiments explained in more detail.

Example 1.1: Layer C), first variant In this example and in all following, a CCS (close-couple showerhead) Cry-MOVPE plant from Aixtron is used.

The template to be used consists of a 60nm thick GaP on a (001) exactly oriented silicon substrate. In the first step, the template is stabilized at 675 ° C for 5 min under tertiary butyl phosphine (TBP)

baked. The reactor pressure is 100 mbar, the

Total flow 48 1 / min and the TBP flow is 1E-3 mol / min. Reactor pressure and total flow are kept constant throughout the process.

In the following step, the wafer temperature for the growth of the relaxation layer (layer C)) is lowered to 500 ° C and the molar fluxes of Al, P and Sb are set for the separation of AlPSb im., The growth mode can be continuous, preferably by means of Flow modulation modulation epitaxy (FME) or atomic layer deposition (ALD). Accordingly, the

Trimethylaluminum (TMAl) -Mol flow adjusted so that in a second, a monolayer AI occupies the substrate surface. The (TESb + TBP) / TMAl (TESb =

Triethyl antimony) is 20 while the TESb / (TBP + TESb) ratio is adjusted so that in each layer the desired composition of the group V elements

is realized.

Overall, the first layer package sets

(Relaxation layer) composed of 6 individual layers. The single layer thickness is 50nm each. Each layer is deposited in FME mode and then a bake step carried out. After heating, the wafer temperature is lowered again to 500 ° C and the mol flows for the next deposition process. The annealing takes place under a TBP stabilization, while the precursor TESb is switched only for deposition in the reactor. The annealing is carried out at a temperature of 675 ° C for 1min.

The six AlSbP monolayers have the following Sb concentration:

1) 15%

2) 30%

3) 45%

4) 60%

5) 68%

6). -60%

With the last annealing step, the deposition of the relaxation layer is completed. The process parameters are as follows:

Total gas flow 481 / min, reactor pressure 100 rabar,

Wafer temperature 500 ° C, annealing temperature 675 ° C,

Bakeout time 1min.

Example 1.2: ^' Layer C), second variant

In this example and in all following, a CCS-Crius-MOVPE system from Aixtron is used.

The template to be used consists of a 60 nm thick GaP on a (001) exactly-oriented silicon substrate. In the first step, the template is annealed at 675 ° C for 5 min under tertiary butyl phoshine (TBP) stabilization. The reactor pressure is 100 mbar, the total flow 48 1 / min and the TBP flux is 1E-3 mol / min. Reactor pressure and total flow are kept constant throughout the process.

In the following step, the wafer temperature for the growth of the relaxation layer (layer C)) is lowered to 500 ° C and the molar flows of Al, P and Sb for the deposition of AlPSb in set. The growth mode may be continuous, preferably by flow rate modulation epitaxy (FME) or atomic layer deposition (ALD). Accordingly, the

Trimethylaluminium (TMA1) mol flow adjusted so that in a second, a monolayer AI occupies the substrate surface. The (TESb + TBP) / TMA1 ratio (TESb =

is realized.

Overall, the first layer package sets

(Relaxation layer) composed of 5 individual layers. All ternary single layer thicknesses are 50nm thick, only the binary single layer AlSb is chosen in thickness so that the annealing causes a partial relaxation to the desired lattice constant of the semiconductor material of the n-channel layer. This means in this example that the AlSb layer is not completely relaxed and still has a lattice constant smaller than AlSb but identical to the n-channel layer. Each layer is deposited in FME mode and then a bake step

carried out. After annealing, the wafer temperature is lowered again to 500 ° C and the mol flows for the next deposition process. The heating takes place a TBP stabilization, while the precursor TESb is switched only for the deposition in the reactor. The annealing is carried out at a temperature of 675 ° C for 1min.

The six AlSbP monolayers are described below

Sequence deposited and have the following Sb concentration:

1) 25%

2) 50%

3) 75%

4) 100%

5) 60%

Total gas flow 481 / min, reactor pressure 100 mbar,

Wafer temperature 500 ° C, annealing temperature 675 ° C,

Bakeout time 1min.

Example 1.3: Layer C), third variant

In this example and in all following, a CCS Crius reactor from Aixtron is used.

The template to be used consists of a 60nm thick GaP on a (001) exactly oriented silicon substrate. In the first step, the template is baked at 675 ° C for 5 min under tertiary butyl (TBP) stabilization. Of the

Reactor pressure is 100 mbar, the total flow 48 1 / min and the TBP flow is 1E-3 mol / min. Reactor pressure and

Total flow is kept constant throughout the process. In the following step, the wafer temperature for the growth of the relaxation layer (layer C)) is lowered to 500 ° C, and the molar flows of Al, In, P (or Sb) for the deposition of AllnPSb are adjusted. Of the

Growth mode may be continuous, preferably by flow rate modulation epitaxy (FME) or atomic layer deposition (ALD). Accordingly, the sum of the group III mol flows, here TMA1 and

Trimethylindium (TMIn), adjusted so that in one second a monolayer group III elements the

Substrate surface occupied. The TMAl / (TMAl + TMIn) ratio as well as the TESb / (TBP + TESb) ratio is adjusted to realize the desired composition of the Group III and Group V elements in each layer.

Overall, the first layer package sets

(Relaxation layer) composed of 6 individual layers. The single layer thickness is 50nm each. Each layer is deposited in FME mode and then a bake step is performed. After annealing, the wafer temperature is lowered again to 500 ° C and the mol flows for the next deposition process. The annealing takes place under a TBP stabilization, while the precursor TESb is switched only for deposition in the reactor. The annealing is carried out at a temperature of 650 ° C for 1min.

The six AlInP single layers have the following InKonzentration:

25%

50% 3) 75%

4) 100%

5) 100%, wherein in this layer also Sb is incorporated (w = 0.08, v = 0.92)

6) 100%

Total gas flow 481 / min, reactor pressure 100 mbar,

Wafer temperature 500 ° C, annealing temperature 675 ° C,

Bakeout time 1min.

Example 2.1: Layer D, first variant

For the growth of the mislocation blocking layer, the wafer temperature is set at 575 ° C. The TMAl mole flow is adjusted for a continuous growth mode (normal deposition) of 2 m / h at 575 ° C.

In addition, the TEB flow is adjusted to incorporate 2% boron.

The false-displacement blocking layer is composed of 2 layers sequentially deposited without growth interruption or a baking step. The composition (percentages in each case based on 100% group III or group V elements) and layer thickness is as follows:

1) 50nm, B2% Al98% P40% Sb60%

2) 50nm, B2% Al98% P34.1% Sb65.9% Growth rate 2μπι / ^η (normal mode), total gas flow 481 / min, reactor pressure 100 mbar, wafer temperature 575 ° C. Layer 1) faces the layer C).

Example 2.2: Layer D, second variant

It becomes in 2.2 for example -2.1 analogous way

proceed. The false offset blocking layer is composed of 2 layers, which without

Growth interruption or one _. baking step

be deposited one after the other. The group III atoms consist in this example only of indium. Instead of TEB, the 1, 1 -Dimethylhydrazinf flow (UDMHy) so

adjusted that 2% of nitrogen are incorporated on the part of Group V.

The composition and layer thickness is as follows:

1) 50nm, N2% P98% In100%

2) 50nm, N2% Sb5.9% P92, 1% lnl00%

Layer 1) faces the layer C).

Example 3.1: Layer E), first variant

The last layer package (the buffer layer) consists of a ternary AlPSb layer. With a thickness of 50nm. The growth temperature and reactor pressure and

Flow settings are identical to the parameters for the misplacement blocking layer deposition. The composition of 100% Al, 40% P and 60% Sb results in the targeted lattice constancy for the integration of the n-channel layer. Settings, as in Example 2.1, but growth rate 1 μπι / h. Example 3.2: Layer E), second variant

The last layer package (the buffer layer) here consists of a ternary AlPSb layer according to Example 3.1 with a thickness of lOnm as the layer D) facing

Partial layer and a, 40nm thick sublayer of

Composition AlAs ₀ , 56Sb ₀ , 44. The growth temperatures and reactor pressure and flow settings are identical to the parameters for the deposition of the misplacement blocking layer, but the growth rate is 1 μπι / h

Claims

Claims:

1. Monolithic integrated semiconductor structure

containing the following layer structure:

A) a carrier layer based on doped or

undoped Si,

B) optionally a layer of the composition

B _x Al _y Ga _z N _t P _v , where x = 0-0, l, y = 0-l, z = 0-l, t = 0-0, l and v = 0, 9-1 ,.

C) a relaxation layer with the composition B _x Al _y Ga _z In _u P _v Sb ", where x = 0-0, l, y = 0-l, z = 0-l, u = 0-1, v = 0 -l and w = 0-l, wherein w and / or u on the side facing the layer A) or B) is smaller, equal, or larger than on the side facing away from the layer A) or B) and within the relaxation layer or is constant, and where v = lw and / or y = luxz,

D) optionally a layer for blocking of

Missing dislocations with the composition

B _x AlyGa _z In _u P _v SbwN _t , where x = 0-0, l, y = 0-l, z = 0-l, u = 0-l, v = 0-l, w = 0-l and t = 0-0, l,

E) optionally a hetero-of-set layer having the composition B _x Al _y Ga _z In _u PvSb _w NtASr where x = 0-0, 1, y = 0-1, z = 0-1, u = 0- l, v = 0-l, w = 0-l, t = 0-0, l and r = 0-l, and

F) any, preferably group III / V,

Semiconductor material, or a combination of several different

Semiconductor materials,

wherein the above stoichiometric indices for all group III elements in the sum always give 1 and wherein the above stoichiometric indices for all group V elements in the sum also always 1 result.

A semiconductor structure according to claim 1, wherein said

Layers C), D) and E) are chosen in their compositions with the proviso that the

Lattice constant of one of the layers D) and / or E) and / or of the layer A) or B) facing away from the layer C) substantially corresponds to the lattice constants of the layer F).

3. A semiconductor structure according to claim 1 or 2, wherein the layer A) on the side facing the layer B) or C) is an Si 001 surface of a Si single crystal.

4. The semiconductor structure according to one of claims 1 to 3, wherein. the layer B) has a thickness of 20-100 nm

and / or a p or n doping concentration of

1 * 10 ¹⁵ -1 * 10 ²¹ cm ^"3 .

A semiconductor structure according to any one of claims 1 to 4, wherein the layer B) is one of the following

Compositions have z = v = l, x = y = t-0 or

y = v = 1, x = z = t = 0 or

x = 0.01-0.1.7 = 0.90-0.99, z = t = 0, v = 1 or

x = 0.01-0, l, z = 0, 90-0.99, y = t = 0, v = 1 or

t = 0, 01-0.1, v = 0.90-0.99, y = x = 0, z = l.

6. Semiconductor structure according to one of claims 1 to 5, wherein in the layer C) w and or u on the Layer A) or B) facing side is smaller than on the side facing away from the layer A) or B) and in the direction of a location coordinate which is orthogonal to the main surfaces of the layer C) passes through a maximum, w and or u in the maximum optionally greater than on the side facing away from the layer A) or B) may be.

7. A semiconductor structure according to any one of claims 1 to 6, wherein the layer C) consists of a plurality of

Partial layers, in particular 1-30 layers,

preferably 2-10 layers, wherein w and or u is variable or constant within a sub-layer.

8. A semiconductor structure according to any one of claims 1 to 7, wherein the layer C) has a thickness of 1-500 nm, in particular 100-400 nm, and / or no doping or a p- or n-doping concentration of 1 * 10 ¹⁵ - 1 * 10 ²¹ cm ^"3 .

9. A semiconductor structure according to any one of claims 1 to 8, wherein the layer C) or its sub-layers has one of the following compositions: y = l, x = z = u = 0, v = l-w or

x = z = 0, y = l-u, v + w = l.

10. A semiconductor structure according to any one of claims 1 to 9, wherein the layer D) has a thickness of 1-150 nm and / or undoped and / or a p- or n-doping concentration of 1 * 10 ¹⁵ -1 * 10 ²¹ cm ^{" 3} has.

11. A semiconductor structure according to any one of claims 1 to 10, wherein the layer D) of a single layer or a plurality of sub-layers, in particular 1-10 Layers, preferably 2-5 layers, is formed.

12. A semiconductor structure according to any one of claims 1 to 11 wherein the layer D) or its sub-layers has one of the following compositions: x = 0-0, l, y = 0.9-l, v = 0-0.7, w = 0.3-l, z = u = t = 0 or u = l, w = 0-0.5, v = 0.5-l, t = 0-0, l, x = y = z = 0 or

y = 1, v = 0-0.7, w = 0.3-l, t = 0-0, l, x = z = u = 0 or

u = 0.9-l, x = 0-0, l, v = 0.5-l, w = 0-0.5, y = z = t = 0.

13. A semiconductor structure according to any one of claims 1 to 12 wherein the layer E) has a thickness of 5-200 nm, in particular 10-100 nm, and / or undoped and / or a p or n-doping concentration of 1 * 10 ¹⁵ -1 * 10 has ²¹ cm ^"3 .

14. The semiconductor structure according to claim 1, wherein the layer E) is formed from a single layer or a plurality of partial layers, in particular 1-10 layers, preferably .2-5 layers.

15. The semiconductor structure according to one of claims 1 to 14, wherein the layer E) is one of the following

Compositions comprises ·.

y = 1, v = 0.2-0.5, w = 0, 5-0, 8,. x = z = u = t = r = 0 or

y = 1, w = 0, 4-0,8, r = 0,2-0,6, x = z = u = v = t = 0.

16. A process for producing a monolithic

integrated semiconductor structure according to one of

Claims 1 to 15,

wherein on a layer A)

optionally a layer B) is epitaxially grown,

on layer A) or B) a layer C) is grown epitaxially,

on the layer C) optionally a layer D) and / or E) is epitaxially grown,

on layer C) or D) or E) the layer F) is epitaxially grown.

17. The method of claim 16, wherein one or more of layer A), B), C), D), E), and / or F) is p- or n-doped.

18. The method according to claim 16 or 17 with the following method steps:

A substrate containing the layer A) is introduced into an epitaxy apparatus, in particular an MOVPE apparatus,

a carrier gas is reacted with educts in defined concentrations in accordance with the given

Composition of a layer A), B), C), D), and E), optionally also F), or loaded their sub-layers,

The laden carrier gas is transported over the surface of the to a temperature in the range of 300 ° C to 800 ° C, especially 400 ° C to 625 ° C in the case of

Layers C) and D) or their partial layers or 525 ° C to 725 ° C in the case of the layer E) or their

Sub-layers, heated substrate or on the surface of the uppermost layer on the substrate for a defined exposure time, with total concentration of the reactants and exposure time are coordinated with the proviso that the semiconductor layer with a predetermined layer thickness on the surface of the substrate or the surface the epitaxial growth of the uppermost layer on the substrate, whereby the epitaxial growth mode may be continuous, preferably by means of flow Modulation epitaxy (FME) or by atomic layer deposition

(atomic layer deposition (ALD).

19. The method according to claim 18, wherein the layer C) is grown in partial layers and wherein between the growth of two partial layers and / or after the growth of the last partial layer, a baking of the substrate to 550 ° C to 750 ° C, in particular to 600 ° C to 725 ° C, takes place.

20. The method according to claim 18 or 19, wherein are used as starting materials for the construction of the layers:

C1-C5 trialkylgallium, in particular

Triethyl gallium (Ga (C ₂ H 5) ₃ ) ₍ tritertiaryglyl gallium and / or trimethylgallium (Ga (0143) 3) as Ga starting material,

Diborane (B ₂ H ₆ ) or C1-C5 trialkylborane,

in particular tritertiarybutylborane and triethylborane (B (02 * 15) 3) and / or borane-amine adducts such as

Dimethylaminoborane as B-starting material,

Alan-amine adducts or C1-C5 trialkylaluminum, in particular trimethylaluminum (Al (0 * 3) 3),

Tri tertiarybutylaluminum and / or

Dimethylethylamine alane as Al reactant,

C1-C5 trialkyl indium, particularly trimethyl indium (In (CH ₃₎ ₃₎ as an in-reactant,

Phosphine (PH ₃ ) and / or C 1 -C 5 alkylphosphine, in particular tertiarybutylphosphine (t- (C 4 H 9) -PH ₂ ) as

P-Educt,

Arsine (AsH ₃ ) and / or C 1 -C 5 alkylarsine and / or trimethylarsine (As (0 3) 3), in particular

Tertiarybutylarsine (t - (C4H) -AsH ₂ ) as As starting material,

C1-C5 trialkyl antimony, in particular

Triethyl antimony (Sb (C ₂ H ₅ ) 3) and / or trimethyl antimony (Sb (CH ₃ ) ₃ ) as Sb starting material,

Ammonia (NH3), mono (C1-C8) alkylhydrazine, in particular tertiarybutylhydrazine (t- (C 4 H 9) H 2) and / or 1, 1-di (C 1 -C 5) -alkylhydrazine, in particular 1, 1-dimethylhydrazine ((CH ₃ ) ₂ -N-NH ₂ ) as N-reactant, where C ₃ -C5 alkyl groups can be linear or branched, and where used as starting materials for the dopants of the layers: diethyl tellurium (DETe),

Dimethylzinc (DMZn), diethylzinc (DEC),

Di-tertiarybutylsilane (DitButSi), silane,

Di-tertiary-butylsulphide, bis-cyclopentadienyl-magnesium, tetrabromomethane.

21. The method according to any one of claims 18 to 20,

wherein the total pressure of carrier gas and educts in the range of 10 to 1000 hPa, in particular 50 to 500 hPa, is set, wherein the ratio of the sum of the partial pressures of the educts to the partial pressure of the carrier gas is between l * 10E-6 to 0.5, and wherein the deposition rate 0.01 to 10 μιτι / h, in particular 0.05 to 5 μιτι / h, is.

22. Use of a semiconductor structure according to one of claims 1 to 15 for producing a III / V channel transistor or other III / V based devices such as laser, light emitting diode, detector and solar cell on a silicon substrate.

23. Semiconductor structure obtainable by a method

according to one of claims 16 to 21.