JPH0654761B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
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- JPH0654761B2 JPH0654761B2 JP26232587A JP26232587A JPH0654761B2 JP H0654761 B2 JPH0654761 B2 JP H0654761B2 JP 26232587 A JP26232587 A JP 26232587A JP 26232587 A JP26232587 A JP 26232587A JP H0654761 B2 JPH0654761 B2 JP H0654761B2
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- compound semiconductor
- semiconductor device
- intermediate layer
- gap
- silicon single
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Description
本発明はSi基板の主面上に化合物半導体をエピタキシャ
ル成長させて形成した半導体装置に関する。 特に、Si基板の主面上にGaPを成長させることにより逆
位相領域（アンチフェイズドメイン）の発生を抑制する
と共に、化合物半導体とGaPとの混晶とGaPの超格子及び
前記混晶と前記化合物半導体の超格子を介在させること
によりSiと化合物半導体の格子不整合を緩和し、格子欠
陥を少なくして素子特性を向上させた化合物半導体装置
に関する。The present invention relates to a semiconductor device formed by epitaxially growing a compound semiconductor on a main surface of a Si substrate. In particular, the growth of GaP on the main surface of the Si substrate suppresses the generation of antiphase regions (antiphase domains), and the mixed crystal of the compound semiconductor and GaP, the superlattice of GaP, and the mixed crystal and the compound. The present invention relates to a compound semiconductor device in which a lattice mismatch between Si and a compound semiconductor is relaxed by interposing a semiconductor superlattice to reduce lattice defects and improve device characteristics.
最近、有機金属化学気相成長法（MOCVD法）や分子線エ
ピタキシー法（MBE法）により、Si基板上に始めに低温
でGaAsを薄く成長させた後高温でGaAsを成長させて高品
質のGaAs層を成長させることが試みられ、発光ダイオー
ド（LED）やレーザダイオード（LD）等が試作されてい
る。 これにより、SiＩＣとGaAsの半導体素子をモノリシック
に集積した光電子集積回路（OEＩＣ）等への展開の可能
性が大きく期待されるようになった。 一方、化合物半導体は様々な元素の組み合せにより、バ
ンドギャップを広範囲に変えることが可能であり、それ
により作成される半導体素子も多岐に渡る。 そこで、Si基板上に各種の化合物半導体を高品質にエピ
タキシャル成長できれば、Siと化合物半導体との様々な
モノリシックハイブリッドデバイスが実現可能となる。Recently, metalorganic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) have been used to grow high-quality GaAs by first growing thin GaAs on a Si substrate at low temperature and then at high temperature. Attempts have been made to grow layers and prototype light emitting diodes (LEDs), laser diodes (LDs), etc. As a result, there has been a great expectation that it can be applied to an optoelectronic integrated circuit (OEIC) in which semiconductor elements of SiIC and GaAs are monolithically integrated. On the other hand, a compound semiconductor can change the bandgap in a wide range by combining various elements, and a wide variety of semiconductor devices can be produced. Therefore, if various compound semiconductors can be epitaxially grown on the Si substrate with high quality, various monolithic hybrid devices of Si and compound semiconductors can be realized.
しかし、一般的に、化合物半導体とSiとの格子定数の不
整合率は、化合物半導体として一般的なGaAsとSiとの格
子定数の不整合率4.1％よりも大きい。このため、従来
技術では特に大きな格子定数の不整合率を有する化合物
半導体をSi基板上に高品質に成長させることは困難であ
った。 即ち、大きな格子不整合のため、化合物半導体層内のミ
スフィット転位の発生やSi基板上に化合物半導体を成長
させることによる逆位相領域の発生が避けられなかっ
た。 上記問題点があるため、現実では、Si基板上に任意の化
合物半導体を結晶成長させて、その化合物半導体を能動
層とする半導体装置を作成できなかった。 本発明は、上記の問題点を解決するために成されたもの
であり、その目的とするところは、シリコン基板上に能
動層としての高品質な化合物半導体を成長させることに
より、上記化合物半導体の望ましい特性を用いた半導体
装置を提供することである。However, in general, the mismatch rate of the lattice constant between the compound semiconductor and Si is larger than the mismatch rate of the lattice constant of GaAs and Si which is generally 4.1% as a compound semiconductor. For this reason, it has been difficult in the prior art to grow a compound semiconductor having a particularly large lattice constant mismatch rate on a Si substrate with high quality. That is, due to the large lattice mismatch, the generation of misfit dislocations in the compound semiconductor layer and the generation of the antiphase region due to the growth of the compound semiconductor on the Si substrate cannot be avoided. Due to the above problems, in reality, it was not possible to grow a compound semiconductor on a Si substrate by crystal growth to prepare a semiconductor device having the compound semiconductor as an active layer. The present invention has been made to solve the above problems, and an object of the present invention is to grow a high-quality compound semiconductor as an active layer on a silicon substrate to obtain the above-mentioned compound semiconductor. It is to provide a semiconductor device using desirable characteristics.
上記問題点を解決するための発明の構成は、シリコン単
結晶基板と、前記シリコン単結晶基板の主面上にエピタ
キシャル成長させたGaPから成る第１中間層と、前記第
１中間層の上にエピタキシャル成長させた閃亜鉛鉱形結
晶構造を持つ化合物半導体とGaPとの混晶とGaPの超格子
から成る第２中間層と、前記第２中間層の上にエピタキ
シャル成長させた前記混晶と閃亜鉛鉱形結晶構造を持つ
前記化合物半導体の超格子から成る第３中間層と、前記
第３中間層の上にエピタキシャル成長させた閃亜鉛鉱形
結晶構造を持つ前記化合物半導体から成る基底層とから
成ることを特徴としている。 上記混晶閃亜鉛鉱形結晶構造を持つ前記化合物半導体及
びその化合物半導体とGaPとの混晶は、例えば、InP,GaI
nP；InAs,GaInAsP；GaSb,GaSbPである。 又、化合物半導体としては、その他III−Ｖ族元素の２
元，３元又は４元の化合物半導体でも良い。例えば、そ
の化合物半導体及びその化合物半導体とGaPとの混晶の
組合せとして、GaAsP,GaAsP；GaAlAs,GaAlAsP；InGaAs,
InGaAsP；InGaAsP,InGaAsP；GaAsSb,GaAsSbP；GaN,GaNP
が考えられる。 又、前記シリコン単結晶基板の主面の面方位を、（10
0）面に対し０〜10°の範囲とすることにより良質の化
合物半導体をエピタキシャル成長させることができた。 又、前記シリコン単結晶基板をPH3（ホスフィン）又はP
H3を含むガス気流中で加熱した後、GaPをエピタキシャ
ル成長させることにより、シリコン単結晶基板の主面上
の第１原子層をＰで形成することにより、更に、良質の
化合物半導体をエピタキシャル成長させることができ
た。The structure of the invention for solving the above problems is a silicon single crystal substrate, a first intermediate layer made of GaP epitaxially grown on the main surface of the silicon single crystal substrate, and an epitaxial growth on the first intermediate layer. A second intermediate layer consisting of a mixed crystal of GaP and a compound semiconductor having a zincblende crystal structure and a superlattice of GaP, and the mixed crystal and zinc blende type epitaxially grown on the second intermediate layer A third intermediate layer made of a superlattice of the compound semiconductor having a crystal structure, and a base layer made of the compound semiconductor having a zinc blende crystal structure epitaxially grown on the third intermediate layer. I am trying. The compound semiconductor having the mixed crystal zinc blende type crystal structure and the mixed crystal of the compound semiconductor and GaP are, for example, InP, GaI
nP; InAs, GaInAsP; GaSb, GaSbP. Further, as a compound semiconductor, 2 of other III-V group elements are used.
A ternary, ternary, or quaternary compound semiconductor may be used. For example, as a combination of the compound semiconductor and a mixed crystal of the compound semiconductor and GaP, GaAsP, GaAsP; GaAlAs, GaAlAsP; InGaAs,
InGaAsP; InGaAsP, InGaAsP; GaAsSb, GaAsSbP; GaN, GaNP
Can be considered. Further, the plane orientation of the main surface of the silicon single crystal substrate is (10
By setting the angle within the range of 0 to 10 ° with respect to the (0) plane, a good-quality compound semiconductor could be epitaxially grown. In addition, the silicon single crystal substrate is PH 3 (phosphine) or P
After heating in a gas flow containing H 3 , GaP is epitaxially grown to form the first atomic layer on the main surface of the silicon single crystal substrate with P, thereby further epitaxially growing a good-quality compound semiconductor. I was able to.
【発明の効果】 本発明の半導体装置は、シリコン単結晶基板の主面上に
GaPから成る第１中間層と、閃亜鉛鉱形結晶構造を持つ
化合物半導体とGaPの混晶とGaPの超格子から成る第２中
間層と、前記混晶と閃亜鉛鉱形結晶構造を持つ前記化合
物半導体の超格子から成る第３中間層とを順次形成して
いるので、前記第３中間層の上に形成される基底層及び
その他の能動層の化合物半導体の結晶性を向上させるこ
とができた。 従って、化合物半導体の望ましい特性を利用した各種の
化合物半導体onシリコン型の半導体装置の実現が可能と
なった。EFFECTS OF THE INVENTION The semiconductor device of the present invention is provided on the main surface of a silicon single crystal substrate.
A first intermediate layer made of GaP, a second intermediate layer made of a compound semiconductor having a zincblende crystal structure and a GaP mixed crystal, and a GaP superlattice; Since the third intermediate layer composed of a compound semiconductor superlattice is sequentially formed, the crystallinity of the compound semiconductor of the base layer and other active layers formed on the third intermediate layer can be improved. It was Therefore, various compound semiconductor on silicon type semiconductor devices can be realized by utilizing the desirable characteristics of the compound semiconductor.
以下、本発明を具体的な実施例に基づいて説明する。 第１実施例 本実施例は発光ダイオードに関するものである。第１図
に於いて、１０は主面が 〔１００〕方位に対してオフ
角２度で傾斜しているｎ型のシリコン単結晶基板であ
る。２０は中間層で、そのうち２１は、n-GaPの単層か
ら成る第１中間層、２２はGaPと混晶比0.5のIn0.5Ga0.5
Pとの５層の超格子から成る第２中間層、２３は混晶比
0.5のIn0.5Ga0.5PとInPの５層の超格子から成る第３中
間層である。 又、３０は発光ダイオード素子部で、そのうち３１はn-
InPから成るクラッド層でこの層が発光ダイオード素子
部の基底層を構成している。又、３２はn-InGaAsPから
成る活性層、３３はP-InPから成るクラッド層、３４はP
-InGaAsPから成るコンタクト層である。 又、４１はAlから成るｎ型電極であり、４２はAu-Znか
ら成るｐ型電極である。 尚、上記のｎ型のシリコン単結晶基板１０は厚さ300μ
ｍでエピタキシャル成長させた後は研磨により50μｍと
なっている。第１中間層２１の厚さは500Å、第２中間
層２２の厚さは0.1μｍで、GaPの１層が100Å、In0.5Ga
0.5Pの１層が100Åである。第３中間層２３の総合の厚
さ、各１層の厚さは第２中間層２２と同じである。クラ
ッド層３１は厚さ２μｍ、活性層３２は厚さ0.5μｍ、
クラッド層３３は厚さ２μｍ、コンタクト層３４は厚さ
0.1μｍである。 上記構成の発光ダイオードは次のようにして製造され
た。 ｎ型のシリコン単結晶基板１０をフッ化水素酸でエッチ
ングした後洗浄し乾燥した。次に、そのｎ型のシリコン
単結晶基板１０を有機金属熱分解気相成長法炉内にセッ
トし、PH3を含むH2気流中で1000℃で10分間アニールし
た。これにより、シリコン単結晶基板１０の主面の第１
原子層をＰとすることができた。 又、原料ガスにはトリメチルガリウム(Ga(CH3)3)，トリ
メチルインジウム(In(CH3)3)，水素ベース10％ホスフィ
ン(PH3)，水素ベース10％アルシン(AsH3)が用いられ
た。そして、ｐ型、ｎ型のドーパントには、それぞれジ
エチル亜鉛((CH2H5)2Zn)，水素ベース100ppmセレン化水
素(H2Se)を用いた。 その後、900℃でGaPをエピタキシャル成長させて第１中
間層２１を形成した。次に、800℃で超格子の第２中間
層２２及び第３中間層２３をエピタキシャル成長させ
た。次に、成長温度を800℃に保持して、順次、クラッ
ド層３１、活性層３２、クラッド層３３、コンタクト層
３４を形成した。 その後、上記のようにして結晶成長された結晶体を取り
出し、コンタクト層３４の上にAu-Znを150μｍφに蒸着
してＰ型電極４２を形成し、反対側のｎ型シリコン単結
晶基板１０の上にAlを蒸着してｎ型電極４１を形成し
た。 このようにして作成された発光ダイオードは第２図に示
す波長特性のものが得られた。 第２実施例 本実施例はホール素子に関するものである。 第３図に於いて、１０は第１実施例と同様に主面が〔１
００〕方位に対してオフ角２度で傾斜しているｎ型のシ
リコン単結晶基板である。２０は中間層で、そのうち２
１はノンドープGaPの単層から成る第１中間層、２４はG
aPと混晶比0.5のIn0.5Ga0.5As0.5P0.5の５層の超格から
成る第２中間層、２５は混晶比0.5のIn0.5Ga0.5As0.5P
0.5とInAs５層の超格子から成る第３中間層である。 又、５１はｎ−InAsから成る能動層であり、この層が基
底層となる。又、５２ａ、５２ｂ、５２ｃ、５２ｄはAu
-Geから成る電極である。 尚、上記のｎ型のシリコン単結晶基板１０は厚さ300μ
ｍである。第１中間層２１の厚さは500Å、第２中間層
２４の厚さは総合で0.1μｍで、GaPの１層が100Å、In
0.5Ga0.5As0.5P0.5の１層が100Åである。第３中間層２
５の総合の厚さは0.125μｍで、In0.5Ga0.5As0.5P0.5の
１層が100Å、InAsの１層の厚さが150Åである。n-InAs
から成る能動層５１の厚さは１μｍである。 上記構成のホール素子は第１実施例と同様にして製造さ
れた。 即ち、ｎ型のシリコン単結晶基板１０を有機金属熱分解
気相成長法炉内にセットし、PH3を含むH2気流中で1000
℃で10分間アニールした。これにより、シリコン単結晶
基板１０の主面の第１原子層をＰとした。又、原料ガス
にはトリメチルガリウム(Ga(CH3)3)，トリメチルインジ
ウム(In(CH3)3)，水素ベース10％ホスフィン(PH3)，水
素ベース10％アルシン(AsH3)が用いられた。そして、又
ｐ型、ｎ型のドーパントには、それぞれジエチル亜鉛
((CH2H5)2Zn)，水素ベース100ppmセレン化水素(H2Se)を
用いた。成長温度はGaPが900℃であり、第２中間層２
４、第３中間層２５、能動層５１が800℃である。 そして、Au-Geから成る電極５２ａ、５２ｂ、５２ｃ、
５２ｄを第４図に示すように形成してホール素子が作成
された。 このホール素子の印加電圧５Ｖ時における検出特性は、
第５図に示す特性となった。 第３図実施例 本実施例は赤外線検出器に関するものである。 第６図に於いて、１０は第１実施例と同様に主面が〔１
００〕方位に対してオフ角２度で傾斜しているｎ型のシ
リコン単結晶基板である。２０は中間層で、そのうち２
１はn-GaPの単層から成る第１中間層、２６はGaPと混晶
比0.5のGa0.5Sb0.5Pの５層の超格子から成る第２中間
層、２６は混晶比0.5のGa0.5Sb0.5PとGaSbの５層の超格
子から成る第３中間層である。 又、６１はn-GaSbから成る能動層、６２はp-GaSbから成
る能動層でありこの層が基底層となる。又、６３ａはAu
-Znから成る電極であり、６３ｂはAlから成る電極であ
る。 第１中間層２１の厚さは500Å、第２中間層２０の厚さ
は総合で0.1μｍで、GaPの１層が100Å、Ga0.5Sb0.5Pの
１層が100Åである。第３中間層２５の総合の厚さは0.1
25μｍで、Ga0.5Sb0.5Pの１層が100Å、GaSbの１層の厚
さが150Åである。又、n-GaSbから成る能動層６１の厚
さは２μｍであり、P-GaSbから成る能動層６２の厚さは
１μｍである。上記構成の赤外線検出器は第１実施例と
同様にして製造された。 即ち、シリコン基板１０の表面の第１原子層をＰとする
ため、シリコン基板１０をPH3を含むH2気流中で1000℃
で10分間アニールした。又、原料ガスには、トリメチル
ガリウム(Ga(CH3)3)，トリメチルアルチモン((CH3)3S
b)，水素ベース10％ホスフィン(PH3)，が用いられた。
そして、ｐ型、ｎ型のドーパントには、それぞれ、ジエ
チル亜鉛((CH2H5)2Zn)，水素ベース100ppmのセレン化水
素(H2Se)を用いた。成長温度はGaPが900℃でその他の層
が800℃である。 上記の方法で製造された赤外線検出器の分光感度特性は
第７図に示すものとなった。 本発明は、上記実施例の半導体装置の他、FET，発光及
び受光素子，信号処理回路，Siに形成された信号処理回
路と化合物半導体に形成された半導体素子との複合IC等
に応用できる。Hereinafter, the present invention will be described based on specific examples. First Embodiment This embodiment relates to a light emitting diode. In FIG. 1, reference numeral 10 denotes an n-type silicon single crystal substrate whose main surface is inclined at an off angle of 2 degrees with respect to the [100] orientation. Reference numeral 20 is an intermediate layer, 21 of which is a first intermediate layer composed of a single layer of n-GaP, and 22 is In 0.5 Ga 0.5 with GaP and a mixed crystal ratio of 0.5.
Second intermediate layer consisting of 5 layers of superlattice with P, 23 is mixed crystal ratio
It is a third intermediate layer composed of a superlattice composed of 0.5 layers of In 0.5 Ga 0.5 P and InP. Further, 30 is a light emitting diode element part, 31 of which is n-
This is a clad layer made of InP, and this layer constitutes the base layer of the light emitting diode element portion. 32 is an active layer made of n-InGaAsP, 33 is a clad layer made of P-InP, and 34 is P.
-A contact layer made of InGaAsP. Further, 41 is an n-type electrode made of Al, and 42 is a p-type electrode made of Au-Zn. The n-type silicon single crystal substrate 10 has a thickness of 300 μm.
After epitaxial growth at m, the thickness is 50 μm due to polishing. The thickness of the first intermediate layer 21 is 500Å, the thickness of the second intermediate layer 22 is 0.1 μm, one GaP layer is 100Å, In 0.5 Ga
One layer of 0.5 P is 100Å. The total thickness of the third intermediate layer 23 and the thickness of each one layer are the same as the second intermediate layer 22. The clad layer 31 has a thickness of 2 μm, the active layer 32 has a thickness of 0.5 μm,
The clad layer 33 has a thickness of 2 μm, and the contact layer 34 has a thickness.
It is 0.1 μm. The light emitting diode having the above structure was manufactured as follows. The n-type silicon single crystal substrate 10 was etched with hydrofluoric acid, washed, and dried. Next, the n-type silicon single crystal substrate 10 was set in a metalorganic pyrolysis vapor deposition furnace and annealed at 1000 ° C. for 10 minutes in a H 2 stream containing PH 3 . Thus, the first surface of the main surface of the silicon single crystal substrate 10
The atomic layer could be P. In addition, trimethylgallium (Ga (CH 3 ) 3 ), trimethylindium (In (CH 3 ) 3 ), hydrogen-based 10% phosphine (PH 3 ), hydrogen-based 10% arsine (AsH 3 ) are used as source gases. It was Diethyl zinc ((CH 2 H 5 ) 2 Zn) and hydrogen-based 100 ppm hydrogen selenide (H 2 Se) were used as the p-type and n-type dopants, respectively. Then, GaP was epitaxially grown at 900 ° C. to form the first intermediate layer 21. Next, the second intermediate layer 22 and the third intermediate layer 23 of the superlattice were epitaxially grown at 800 ° C. Next, while maintaining the growth temperature at 800 ° C., the cladding layer 31, the active layer 32, the cladding layer 33, and the contact layer 34 were sequentially formed. After that, the crystal body grown as described above is taken out, Au—Zn is vapor-deposited on the contact layer 34 to a thickness of 150 μm to form the P-type electrode 42, and the n-type silicon single crystal substrate 10 on the opposite side is formed. Al was vapor-deposited thereon to form the n-type electrode 41. The light emitting diode thus manufactured has the wavelength characteristic shown in FIG. Second Example This example relates to a Hall element. In FIG. 3, 10 is the main surface [1 as in the first embodiment.
[00] direction is an n-type silicon single crystal substrate inclined at an off angle of 2 degrees. 20 is the middle layer, of which 2
1 is the first intermediate layer consisting of a single layer of undoped GaP, 24 is G
The second intermediate layer consisting of five layers of a 0.5 and 0.5 mixed crystal ratio of In 0.5 Ga 0.5 As 0.5 P 0.5 , and 25 is In 0.5 Ga 0.5 As 0.5 P of mixed crystal ratio 0.5.
It is a third intermediate layer consisting of a superlattice of 0.5 and InAs 5 layers. Further, 51 is an active layer made of n-InAs, and this layer serves as a base layer. Also, 52a, 52b, 52c and 52d are Au.
-An electrode made of Ge. The n-type silicon single crystal substrate 10 has a thickness of 300 μm.
m. The thickness of the first intermediate layer 21 is 500 Å, the total thickness of the second intermediate layer 24 is 0.1 μm, and one GaP layer is 100 Å, In.
One layer of 0.5 Ga 0.5 As 0.5 P 0.5 has 100Å. Third middle layer 2
The total thickness of No. 5 is 0.125 μm, one layer of In 0.5 Ga 0.5 As 0.5 P 0.5 is 100 Å, and one layer of InAs is 150 Å. n-InAs
The thickness of the active layer 51 made of is 1 μm. The Hall element having the above structure was manufactured in the same manner as in the first embodiment. That is, set the silicon single crystal substrate 10 of n-type organometallic pyrolysis vapor deposition furnace, 1000 with H 2 in a gas flow containing PH 3
Annealed at ℃ for 10 minutes. Thereby, the first atomic layer on the main surface of the silicon single crystal substrate 10 was set to P. In addition, trimethylgallium (Ga (CH 3 ) 3 ), trimethylindium (In (CH 3 ) 3 ), hydrogen-based 10% phosphine (PH 3 ), hydrogen-based 10% arsine (AsH 3 ) are used as source gases. It was Diethyl zinc is used as the p-type and n-type dopants, respectively.
((CH 2 H 5 ) 2 Zn) and hydrogen-based 100 ppm hydrogen selenide (H 2 Se) were used. The growth temperature is 900 ° C. for GaP, and the second intermediate layer 2
4, the temperature of the third intermediate layer 25 and the active layer 51 is 800 ° C. Then, the electrodes 52a, 52b, 52c made of Au-Ge,
Hall elements were prepared by forming 52d as shown in FIG. The detection characteristics of this Hall element when the applied voltage is 5V are:
The characteristics are shown in FIG. FIG. 3 Example This example relates to an infrared detector. In FIG. 6, 10 is the main surface [1 as in the first embodiment.
[00] direction is an n-type silicon single crystal substrate inclined at an off angle of 2 degrees. 20 is the middle layer, of which 2
1 is a first intermediate layer composed of a single layer of n-GaP, 26 is a second intermediate layer composed of GaP and 5 layers of Ga 0.5 Sb 0.5 P with a mixed crystal ratio of 0.5, and 26 is Ga with a mixed crystal ratio of 0.5. It is a third intermediate layer composed of a superlattice composed of 5 layers of 0.5 Sb 0.5 P and GaSb. Further, 61 is an active layer made of n-GaSb, 62 is an active layer made of p-GaSb, and this layer serves as a base layer. 63a is Au
-Zn is an electrode, and 63b is an electrode made of Al. The thickness of the first intermediate layer 21 is 500 Å, the total thickness of the second intermediate layer 20 is 0.1 μm, one layer of GaP is 100 Å, and one layer of Ga 0.5 Sb 0.5 P is 100 Å. The total thickness of the third intermediate layer 25 is 0.1
At 25 μm, one layer of Ga 0.5 Sb 0.5 P is 100 Å and one layer of GaSb is 150 Å. The active layer 61 made of n-GaSb has a thickness of 2 μm, and the active layer 62 made of P-GaSb has a thickness of 1 μm. The infrared detector having the above structure was manufactured in the same manner as in the first embodiment. That is, since the first atomic layer on the surface of the silicon substrate 10 is P, the silicon substrate 10 is heated to 1000 ° C. in an H 2 stream containing PH 3.
Annealed for 10 minutes. In addition, trimethylgallium (Ga (CH 3 ) 3 ), trimethylartimon ((CH 3 ) 3 S
b), hydrogen-based 10% phosphine (PH 3 ), was used.
Diethyl zinc ((CH 2 H 5 ) 2 Zn) and hydrogen selenide (H 2 Se) having a hydrogen base of 100 ppm were used as the p-type and n-type dopants, respectively. The growth temperature is 900 ° C for GaP and 800 ° C for the other layers. The spectral sensitivity characteristics of the infrared detector manufactured by the above method are shown in FIG. The present invention can be applied to FETs, light emitting and receiving elements, signal processing circuits, composite ICs of signal processing circuits formed on Si and semiconductor elements formed on compound semiconductors, etc., in addition to the semiconductor devices of the above embodiments.
第１図は本発明の具体的な一実施例に係る発光ダイオー
ドの構成を示した断面図。第２図はその発光ダイオード
の発光波長特性を示した特性図。第３図は本発明の具体
的な一実施例に係るホール素子の構成を示した断面図。
第４図はそのホール素子の平面図。第５図はそのホール
素子の検出電圧と外部磁界との関係を示した特性図。第
６図は本発明の具体的な一実施例に係る赤外線検出器の
構成を示した断面図。第７図はその赤外線検出器の分光
感度特性を示した特性図である。 １０……シリコン単結晶基板、２０……中間層、 ２１……第１中間層、２２，２４，２６……第２中間
層、２３，２５，２７……第３中間層、３１，５１，６
１……基底層FIG. 1 is a sectional view showing the structure of a light emitting diode according to a specific embodiment of the present invention. FIG. 2 is a characteristic diagram showing the emission wavelength characteristic of the light emitting diode. FIG. 3 is a sectional view showing the structure of a Hall element according to a specific embodiment of the present invention.
FIG. 4 is a plan view of the Hall element. FIG. 5 is a characteristic diagram showing the relationship between the detected voltage of the Hall element and the external magnetic field. FIG. 6 is a sectional view showing the structure of an infrared detector according to a specific embodiment of the present invention. FIG. 7 is a characteristic diagram showing the spectral sensitivity characteristic of the infrared detector. 10 ... Silicon single crystal substrate, 20 ... Intermediate layer, 21 ... First intermediate layer, 22, 24, 26 ... Second intermediate layer, 23, 25, 27 ... Third intermediate layer, 31, 51, 6
1 ... Base layer
Claims (11)
させたGaPから成る第１中間層と、 前記第１中間層の上にエピタキシャル成長させた閃亜鉛
鉱形結晶構造を持つ化合物半導体とGaPとの混晶とGaPの
超格子から成る第２中間層と、 前記第２中間層の上にエピタキシャル成長させた前記混
晶と閃亜鉛鉱形結晶構造を持つ前記化合物半導体の超格
子から成る第３中間層と、 前記第３中間層の上にエピタキシャル成長させた閃亜鉛
鉱形結晶構造を持つ前記化合物半導体から成る基底層と から成る半導体装置。1. A silicon single crystal substrate, a first intermediate layer made of GaP epitaxially grown on the main surface of the silicon single crystal substrate, and a zincblende crystal structure epitaxially grown on the first intermediate layer. A second intermediate layer comprising a mixed crystal of a compound semiconductor having GaP and a GaP superlattice; and a compound semiconductor having a zincblende crystal structure and the mixed crystal epitaxially grown on the second intermediate layer. A semiconductor device comprising: a third intermediate layer made of a superlattice; and a base layer made of the compound semiconductor having a zincblende crystal structure epitaxially grown on the third intermediate layer.
体はInPであり、前記混晶はGaInPであることを特徴とす
る特許請求の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein the compound semiconductor having a zinc blende type crystal structure is InP, and the mixed crystal is GaInP.
体はInAsであり、前記混晶はGaInAsPであることを特徴
とする特許請求の範囲第１項記載の半導体装置。3. The semiconductor device according to claim 1, wherein the compound semiconductor having a zinc blende type crystal structure is InAs and the mixed crystal is GaInAsP.
体はGaSbであり、前記混晶はGaSbPであることを特徴と
する特許請求の範囲第１項記載の半導体装置。4. The semiconductor device according to claim 1, wherein the compound semiconductor having a zinc blende type crystal structure is GaSb and the mixed crystal is GaSbP.
体はIII−Ｖ族元素の２，３又は４元から成る化合物半
導体であり、前記混晶はその化合物半導体とGaPとの混
晶であることを特徴とする特許請求の範囲第１項記載の
半導体装置。5. The compound semiconductor having a zincblende crystal structure is a compound semiconductor composed of a III-V group element of 2, 3 or 4 elements, and the mixed crystal is a mixed crystal of the compound semiconductor and GaP. The semiconductor device according to claim 1, wherein the semiconductor device is present.
体はInP,InAs,GaSbのうち少なくとも２種以上の混晶か
ら成る化合物半導体であり、前記混晶はその化合物半導
体とGaPとの混晶であることを特徴とする特許請求の範
囲第１項記載の半導体装置。6. The compound semiconductor having a zinc blende type crystal structure is a compound semiconductor composed of a mixed crystal of at least two kinds of InP, InAs and GaSb, and the mixed crystal is a mixture of the compound semiconductor and GaP. The semiconductor device according to claim 1, wherein the semiconductor device is a crystal.
体はII−VI族元素の２，３又は４元から成る化合物半導
体であり、前記混晶はその化合物半導体とGaPとの混晶
であることを特徴とする特許請求の範囲第１項記載の半
導体装置。7. The compound semiconductor having a zinc blende type crystal structure is a compound semiconductor composed of a II-VI group element of 2, 3 or 4 elements, and the mixed crystal is a mixed crystal of the compound semiconductor and GaP. The semiconductor device according to claim 1, wherein the semiconductor device is present.
は、（100）面に対し０〜10°の範囲に存在することを
特徴とする特許請求の範囲第１項記載の半導体装置。8. The semiconductor device according to claim 1, wherein the main surface of the silicon single crystal substrate has a plane orientation in the range of 0 to 10 ° with respect to the (100) plane.
層のGaPをエピタキシャル成長するに先立ち、前記シリ
コン単結晶基板の主面上の第１原子層をＰ（燐）で形成
したことを特徴とする特許請求の範囲第１項記載の半導
体装置。9. The first atomic layer on the main surface of the silicon single crystal substrate is formed of P (phosphorus) prior to epitaxially growing GaP of the first intermediate layer on the silicon single crystal substrate. The semiconductor device according to claim 1.
間層のGaPをエピタキシャル成長するに先立ち、前記シ
リコン単結晶基板はPH3（ホスフィン）又はPH3を含むガ
ス気流中で加熱されることを特徴とする特許請求の範囲
第１項記載の半導体装置。10. Prior to epitaxially growing GaP of the first intermediate layer on the silicon single crystal substrate, the silicon single crystal substrate is heated in a gas stream containing PH 3 (phosphine) or PH 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.
属化学気相成長法であることを特徴とする特許請求の範
囲第１項記載の半導体装置。11. The semiconductor device according to claim 1, wherein the epitaxial growth method is a metal organic chemical vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26232587A JPH0654761B2 (en) | 1987-10-16 | 1987-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26232587A JPH0654761B2 (en) | 1987-10-16 | 1987-10-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01105527A JPH01105527A (en) | 1989-04-24 |
| JPH0654761B2 true JPH0654761B2 (en) | 1994-07-20 |
Family
ID=17374203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26232587A Expired - Lifetime JPH0654761B2 (en) | 1987-10-16 | 1987-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654761B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011107657A1 (en) * | 2011-07-12 | 2013-01-17 | Nasp Iii/V Gmbh | Monolithic integrated semiconductor structure |
-
1987
- 1987-10-16 JP JP26232587A patent/JPH0654761B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01105527A (en) | 1989-04-24 |
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