CN101192517A - Gallium arsenide substrate multiple layer deformation buffer layer manufacture method - Google Patents
Gallium arsenide substrate multiple layer deformation buffer layer manufacture method Download PDFInfo
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- CN101192517A CN101192517A CNA2006101443040A CN200610144304A CN101192517A CN 101192517 A CN101192517 A CN 101192517A CN A2006101443040 A CNA2006101443040 A CN A2006101443040A CN 200610144304 A CN200610144304 A CN 200610144304A CN 101192517 A CN101192517 A CN 101192517A
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- resilient coating
- gallium arsenide
- indium
- arsenide substrate
- aluminium arsenic
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Abstract
The invention relates to a method for manufacturing multilayer buffer layers with deformation on a gallium arsenide substrate. The invention is characterized in that the method comprises the following steps: step 1, one gallium arsenide substrate is extracted; step 2, the gallium arsenide substrate is processed by deoxidation; step 3, the buffer layers of the gallium arsenide are generated on the gallium arsenide substrate so as to obtain a flat surface; step 4, a buffer layer of indium aluminum arsenic is generated in a range of relatively low temperature, and the buffer layer of the indium aluminum arsenic has a one-layer, two-layer or multi-layer structure so as to achieve the change of lattice constant in the process of epitaxial growth; and step 5, after the buffer layer of the indium aluminum arsenic is generated, the temperature of the gallium arsenide substrate is increased, and high temperature annealing is carried out so as to release the stress of an epitaxial layer.
Description
Technical field
The present invention relates to the crystal epitaxy field, the manufacture method of the multilayer distortion resilient coating on particularly a kind of gallium arsenide substrate.
Background technology
GaAs (GaAs) substrate since its compared with similar products, price is low, good mechanical property, help advantages such as integrated, be widely used in microelectronics and optoelectronic areas, the light-emitting diode (LED) that is used to grow, laser diode (LD), optical communication active device, solar cell, microwave device etc. always.Recently, in order to handle the annual magnanimity information that increases with the triple speed degree rapidly, the optical-fibre communications of global high speed development, Internet, mobile communication require prepared material to develop to high-frequency, high bandwidth and high transmission speed direction.This material of growing with regard to requiring has higher mobility, but usually like this (all exist bigger lattice mismatch as between the indium gallium arsenic (InGaAs) of high indium component and GaAs (GaAs) substrate, the technology that therefore adds resilient coating between substrate and active area just becomes the key technology of the GaAs based semi-conducting material of making to the material of institute's extension.Mainly contain two effects as resilient coating, on the one hand, compensated the lattice mismatch between substrate and the active area, can filter on the other hand because the dislocation that lattice mismatch produced.So growth evenness degree height, defective is few, the accurate resilient coating of component is most important for the making of photoelectric semiconductor material.In addition, at the microelectronic component integration field, higher requirement is arranged for the insulation property of semiconductor device material therefor.This has just proposed being avoided of growing high resistant resilient coating because resilient coating leaks electricity to the integrated difficulty of bringing of device.The present invention proposes in order to satisfy above demand just.
Summary of the invention
The objective of the invention is to, the manufacture method of the multilayer distortion resilient coating on a kind of gallium arsenide substrate is provided, the quality that it can provide crystal helps the making of subsequent process steps.
The manufacture method of the multilayer distortion resilient coating on a kind of gallium arsenide substrate of the present invention is characterized in that, comprises the steps:
Step 1: get a gallium arsenide substrate;
Step 2: gallium arsenide substrate is carried out deoxidation treatment;
Step 3: the GaAs buffer layer of on gallium arsenide substrate, growing, to obtain even curface;
Step 4: growth one indium aluminium arsenic resilient coating in low temperature range, this indium aluminium arsenic resilient coating is one deck, two-layer or sandwich construction, to reach the change of epitaxial process lattice constant;
Step 5: behind the indium aluminium arsenic resilient coating of having grown, rising gallium arsenide substrate temperature is carried out high-temperature thermal annealing, discharges the stress of epitaxial loayer.
When wherein this indium aluminium arsenic resilient coating was one deck, this indium aluminium arsenic resilient coating was the structure that linear indium content gradually variational increases; When this indium aluminium arsenic resilient coating was two-layer, this indium aluminium arsenic resilient coating was that linear indium content gradually variational increase adds reverse buffer layer structure; When this indium aluminium arsenic resilient coating was multilayer, this indium aluminium arsenic resilient coating was a step indium content gradually variational structure.
Wherein the deoxidation treatment of step 2 is to carry out under 500-650 ℃.
Wherein the growth temperature of GaAs buffer layer is 550-700 ℃; Growth thickness is the 10-1000 nanometer, to obtain even curface.
Wherein the growth temperature of indium aluminium arsenic resilient coating is 250-420 ℃, the three dimensional growth that has stoped indium aluminium arsenic material to cause because of growth temperature is too high.
Wherein indium component x excursion changes between 1-30% to 30-100% in the indium aluminium arsenic resilient coating, guarantees the lattice match of the epitaxial material of subsequent growth.
Wherein the thickness of indium aluminium arsenic resilient coating is between 200 nanometers-5 micron, with the stress that reduces to be produced because of lattice mismatch.
During the multilayer of wherein growing indium aluminium arsenic resilient coating the method for growth of adopt pausing, promptly after each layer indium aluminium arsenic buffer growth is finished, pause 1-5 minute, growth one deck resilient coating down then.
Indium component difference between each layer of wherein said multilayer indium aluminium arsenic resilient coating is between 1-30%, and thickness is between the 10-500 nanometer.
When wherein said indium aluminium arsenic resilient coating was one deck, the thickness of indium aluminium arsenic resilient coating was the 1-5 micron.
When wherein said indium aluminium arsenic resilient coating was two-layer, the two-layer indium component difference of indium aluminium arsenic resilient coating was in the 1-50% scope.
Wherein said annealing temperature is 470 ℃-520 ℃, and annealing time is 0-60 minute.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is a first embodiment of the invention, and it shows the structural representation of multilayer indium aluminium arsenic resilient coating;
Fig. 2 is a second embodiment of the invention, and it shows the structural representation of one deck indium aluminium arsenic resilient coating;
Fig. 3 is a third embodiment of the invention, and it shows the structural representation of two-layer indium aluminium arsenic resilient coating;
Fig. 4 is the schematic diagram that adopts the distortion high electron mobility transistor structure of first embodiment of the present invention making;
Fig. 5 is three diffraction curve figure of indium aluminium arsenic resilient coating high-resolution X ray of the embodiment of the invention one.
Embodiment
At first see also Fig. 1, Fig. 2 and shown in Figure 3, the manufacture method of the multilayer distortion resilient coating on a kind of gallium arsenide substrate of the present invention is characterized in that, comprises the steps:
At first, get a gallium arsenide substrate 11, the molecular beam epitaxial growth of putting into ultra high vacuum is indoor.Rising sinks to the bottom temperature and under 500-650 ℃ gallium arsenide substrate 11 is carried out deoxidation treatment, to obtain smooth epitaxial surface.Under 550-700 ℃ underlayer temperature, the GaAs buffer layer 12 of growth 10-1000 nanometer thickness to obtain even curface, provides favourable epitaxial loayer then.In 250-420 ℃ temperature range, finish the growth of indium aluminium arsenic resilient coating 13 then.In this temperature range, promptly stoped the three dimensional growth of indium aluminium arsenic cushioning layer material when high temperature, promptly be grown to quantum-dot structure, guarantee again that in selected temperature range indium aluminium arsenic atom has sufficient surface migration and forms smooth epitaxial surface.Behind the indium aluminium arsenic resilient coating 13 of having grown, rising underlayer temperature to 470 ℃-520 ℃ carries out the high-temperature thermal annealing in the stove, and annealing time is 0-60 minute.The purpose of annealing is in the epitaxial loayer of growing in order to discharge because different caused stress with the substrate lattice constant.
The indium aluminium arsenic resilient coating 13 of being grown is one deck resilient coating 13 ' (Fig. 2) of indium content gradually variational, two buffer layer 13 " (Fig. 3) or multi-buffering-layer 13 (Fig. 1) structure.When wherein this indium aluminium arsenic resilient coating 13 ' was one deck, this indium aluminium arsenic resilient coating 13 ' was the structure that linear indium content gradually variational increases; This indium aluminium arsenic resilient coating 13 " when being two-layer, this indium aluminium arsenic resilient coating 13 " for increasing, linear indium content gradually variational adds reverse buffer layer structure; When this indium aluminium arsenic resilient coating 13 was multilayer, this indium aluminium arsenic resilient coating 13 was a step indium content gradually variational structure, and indium component x excursion changes between 1-30% to 30-100%, guarantees the lattice match of the epitaxial material of subsequent growth.The thickness altogether of indium aluminium arsenic resilient coating 13 is between 200 nanometers-5 micron, with the stress that reduces to be produced because of lattice mismatch, and filters the dislocation that is produced in the lattice mismatch epitaxial grown material is arranged.
When growing multilayer indium aluminium arsenic resilient coating 13 are the methods that adopt the growth that pauses, and promptly after 13 growths of each layer indium aluminium arsenic resilient coating are finished, pause 1-5 minute, guarantee that simultaneously the molecular beam epitaxial growth chamber leads to the arsenic line and protects the indium aluminium arsenic resilient coating of having grown.One deck resilient coating under growing then is until indium aluminium arsenic resilient coating 13 structures of having grown all.
When the indium aluminium arsenic resilient coating 13 of being grown was sandwich construction, the indium component difference between each layer was between 1-30%, and each layer thickness is between the 10-500 nanometer, and general thickness is the 1-5 micron.Guarantee that the indium aluminium arsenic resilient coating 13 of being grown has enough thickness with relieve stresses.When the indium aluminium arsenic resilient coating of being grown 13 when two-layer, its two-layer indium component difference is in the 1-50% scope, in order to change the suffered stress situation of epitaxial loayer.Because the lattice constant of indium aluminium arsenic resilient coating 13 is greater than the gallium arsenide substrate lattice constant, and along with the increase lattice constant of indium component in the resilient coating constantly becomes big, make the epitaxial loayer of being grown be subjected to the compression of substrate, the indium component descends when the growth second layer, and lattice constant reduces then to make second layer resilient coating to be subjected to the effect of ground floor resilient coating tensile stress.Comprehensive two kinds of different stress just can make whole resilient coating be in unstressed or the state that stress is less, to improve the crystal mass of resilient coating 13.
Be illustrated for an example below,
High Electron Mobility Transistor (MMHEMT) material with GaAs based distortion is an example, adopts the indium aluminium arsenic buffer layer structure of step indium content gradually variational, and channel layer is indium gallium arsenic (In0.52Ga0.48As) material.
As shown in Figure 4, on the Semi-insulating GaAs substrate, utilize molecular beam epitaxial method deposition one deck GaAs resilient coating 11, about 150 nanometers of this buffer layer thickness, growth temperature is 580 ℃.
As shown in Figure 4, next keep As source stove to open reducing underlayer temperature to 30 ℃, carry out InxAl
1-xAs buffer growth.
As shown in Figure 4, InxAl
1-xAs resilient coating 13 constitutes 41-45 by 5 layers.Wherein In change of component scope is 0.1-0.53, and every layer thickness is 100 nanometers, keeps As source stove to open after each layer growth is finished, and stops 5 minutes.
As shown in Figure 4, at InxAl
1Growth InGaAs quantum well HEMT structure 51-55 on the-xAs resilient coating, growth temperature is 480 ℃.Comprising In
0.52Ga
0.48As channel layer 51, In
0.53Al
0.47As separator 52, Si delta doping layer 53, In
0.52Al
0.48As barrier layer 54, In
0.52Ga
0.48As cap layer 55.
Be illustrated in figure 5 as multilayer InxAl
1Three diffraction curve figure of-xAs resilient coating high-resolution X ray can obviously tell each layer resilient coating and have separately diffraction maximum, illustrate that the multi-buffering-layer structure component that we grow is accurate, quality is better.
As shown in table 1, be multilayer InxAl
1The Hall test result analysis of-xAs resilient coating, resistivity at room temperature are 2.6 * 104 (ohm * centimetre).The cushioning layer material that proof is grown has higher electric resistivity, satisfies the integrated needs of device fully.
Table 1
| Growth temperature (℃) | Resistivity (Ω-cm) | The Hall factor | Carrier concentration (cm -3) | Mobility (cm 2/V.S) |
| 340 | 2.6×10 4 | 0.9946 | 5.319×10 10 | 4522 |
Claims (12)
1. the manufacture method of the distortion of the multilayer on gallium arsenide substrate resilient coating is characterized in that, comprises the steps:
Step 1: get a gallium arsenide substrate;
Step 2: gallium arsenide substrate is carried out deoxidation treatment;
Step 3: the GaAs buffer layer of on gallium arsenide substrate, growing, to obtain even curface;
Step 4: growth one indium aluminium arsenic resilient coating in low temperature range, this indium aluminium arsenic resilient coating is one deck, two-layer or sandwich construction, to reach the change of epitaxial process lattice constant;
Step 5: behind the indium aluminium arsenic resilient coating of having grown, rising gallium arsenide substrate temperature is carried out high-temperature thermal annealing, discharges the stress of epitaxial loayer.
2. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that when wherein this indium aluminium arsenic resilient coating was one deck, this indium aluminium arsenic resilient coating was the structure that linear indium content gradually variational increases; When this indium aluminium arsenic resilient coating was two-layer, this indium aluminium arsenic resilient coating was that linear indium content gradually variational increase adds reverse buffer layer structure; When this indium aluminium arsenic resilient coating was multilayer, this indium aluminium arsenic resilient coating was a step indium content gradually variational structure.
3. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that wherein the deoxidation treatment of step 2 is to carry out under 500-650 ℃.
4. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that wherein the growth temperature of GaAs buffer layer is 550-700 ℃; Growth thickness is the 10-1000 nanometer, to obtain even curface.
5. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that wherein the growth temperature of indium aluminium arsenic resilient coating is 250-420 ℃, the three dimensional growth that has stoped indium aluminium arsenic material to cause because of growth temperature is too high.
6. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1, it is characterized in that, wherein indium component x excursion changes between 1-30% to 30-100% in the indium aluminium arsenic resilient coating, guarantees the lattice match of the epitaxial material of subsequent growth.
7. the manufacture method of multilayer on the gallium arsenide substrate according to claim 1 distortion resilient coating is characterized in that, wherein the thickness of indium aluminium arsenic resilient coating is between 200 nanometers-5 micron, with the stress that reduces to be produced because of lattice mismatch.
8. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1, it is characterized in that, it during the multilayer of wherein growing indium aluminium arsenic resilient coating the method that adopts the growth that pauses, promptly after each layer indium aluminium arsenic buffer growth is finished, pause 1-5 minute, one deck resilient coating down of growing then.
9. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that the indium component difference between each layer of wherein said multilayer indium aluminium arsenic resilient coating is between 1-30%, and thickness is between the 10-500 nanometer.
10. the manufacture method of the multilayer distortion resilient coating on the gallium arsenide substrate according to claim 1 is characterized in that when wherein said indium aluminium arsenic resilient coating was one deck, the thickness of indium aluminium arsenic resilient coating was the 1-5 micron.
11. the manufacture method of the distortion of the multilayer on the gallium arsenide substrate according to claim 1 resilient coating is characterized in that when wherein said indium aluminium arsenic resilient coating was two-layer, the two-layer indium component difference of indium aluminium arsenic resilient coating was in the 1-50% scope.
12. the manufacture method of the distortion of the multilayer on the gallium arsenide substrate according to claim 1 resilient coating is characterized in that wherein said annealing temperature is 470 ℃-520 ℃, annealing time is 0-60 minute.
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| CN102194671A (en) * | 2011-05-11 | 2011-09-21 | 中国科学院半导体研究所 | Method for growing varied buffer layer on substrate |
| WO2013020423A1 (en) * | 2011-08-05 | 2013-02-14 | 苏州大学 | Manufacturing apparatus and manufacturing method for quantum dot material |
| CN103258722A (en) * | 2013-04-27 | 2013-08-21 | 中国电子科技集团公司第十三研究所 | Method adopting AlGaInN buffering layer to grow three-group nitride in GaAs substrate |
| WO2013143018A1 (en) * | 2012-03-26 | 2013-10-03 | 北京通美晶体技术有限公司 | Iiiα-va group semiconductor single crystal substrate and method for preparing same |
| CN104637941A (en) * | 2015-02-04 | 2015-05-20 | 桂林电子科技大学 | Composite channel MHEMT (Metamorphic High Electron Mobility Transistor) microwave oscillator and preparation method thereof |
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| CN108346556A (en) * | 2011-07-12 | 2018-07-31 | 纳斯普Ⅲ/Ⅴ有限责任公司 | Single-slice integrated semiconductor structure |
| CN109638085A (en) * | 2018-10-29 | 2019-04-16 | 中国电子科技集团公司第十三研究所 | GaAs base resonance tunnel-through diode and preparation method thereof |
| CN114758948A (en) * | 2022-06-14 | 2022-07-15 | 江苏能华微电子科技发展有限公司 | SiC substrate surface treatment method for semi-insulating GaN epitaxial layer growth |
| CN116724377A (en) * | 2020-12-01 | 2023-09-08 | 业纳光学系统有限公司 | Semiconductor device and method for producing a substrate for a semiconductor component and use of indium for the production thereof |
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2006
- 2006-12-01 CN CNA2006101443040A patent/CN101192517A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102194671B (en) * | 2011-05-11 | 2012-08-15 | 中国科学院半导体研究所 | Method for growing varied buffer layer on substrate |
| CN102194671A (en) * | 2011-05-11 | 2011-09-21 | 中国科学院半导体研究所 | Method for growing varied buffer layer on substrate |
| CN108346556A (en) * | 2011-07-12 | 2018-07-31 | 纳斯普Ⅲ/Ⅴ有限责任公司 | Single-slice integrated semiconductor structure |
| WO2013020423A1 (en) * | 2011-08-05 | 2013-02-14 | 苏州大学 | Manufacturing apparatus and manufacturing method for quantum dot material |
| US8969185B2 (en) | 2011-08-05 | 2015-03-03 | Soochow University | Manufacturing apparatus and manufacturing method for quantum dot material |
| WO2013143018A1 (en) * | 2012-03-26 | 2013-10-03 | 北京通美晶体技术有限公司 | Iiiα-va group semiconductor single crystal substrate and method for preparing same |
| CN103258722A (en) * | 2013-04-27 | 2013-08-21 | 中国电子科技集团公司第十三研究所 | Method adopting AlGaInN buffering layer to grow three-group nitride in GaAs substrate |
| CN104637941B (en) * | 2015-02-04 | 2017-05-10 | 桂林电子科技大学 | Composite channel MHEMT (Metamorphic High Electron Mobility Transistor) microwave oscillator and preparation method thereof |
| CN104637941A (en) * | 2015-02-04 | 2015-05-20 | 桂林电子科技大学 | Composite channel MHEMT (Metamorphic High Electron Mobility Transistor) microwave oscillator and preparation method thereof |
| CN106783613A (en) * | 2017-01-13 | 2017-05-31 | 桂林电子科技大学 | A kind of III V races semiconductor MOS HEMT device and preparation method thereof |
| CN109638085A (en) * | 2018-10-29 | 2019-04-16 | 中国电子科技集团公司第十三研究所 | GaAs base resonance tunnel-through diode and preparation method thereof |
| CN116724377A (en) * | 2020-12-01 | 2023-09-08 | 业纳光学系统有限公司 | Semiconductor device and method for producing a substrate for a semiconductor component and use of indium for the production thereof |
| CN114758948A (en) * | 2022-06-14 | 2022-07-15 | 江苏能华微电子科技发展有限公司 | SiC substrate surface treatment method for semi-insulating GaN epitaxial layer growth |
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