EP2701028B1 - Circuit intégré avec un réseau de résistances de références externes - Google Patents

Circuit intégré avec un réseau de résistances de références externes Download PDF

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Publication number
EP2701028B1
EP2701028B1 EP12175926.0A EP12175926A EP2701028B1 EP 2701028 B1 EP2701028 B1 EP 2701028B1 EP 12175926 A EP12175926 A EP 12175926A EP 2701028 B1 EP2701028 B1 EP 2701028B1
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integrated
integrated circuit
current
external
network
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EP12175926.0A
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German (de)
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EP2701028A1 (fr
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Rob Fronen
Adrian Joita
Adriana Butur
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Rohm Co Ltd
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Rohm Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Definitions

  • the invention relates to an integrated circuit comprising an integrated reference current generation circuit connected via network connection pins to an external reference resistor network.
  • an integrated circuit IC integrated on a chip comprises an integrated reference current generation circuit which is provided to generate a reference current for different circuits integrated on the chip.
  • An on-chip reference current is created in conventional integrated circuits by means of an external resistor across which the reference circuit maintains a constant and well-defined reference voltage V ref . This can be accomplished by means of a differential amplifier which regulates the gate voltage of a MOSFET in a closed loop manner.
  • the reference current I ref provided by the integrated reference current generation circuit connected to the external reference resistor can therefore be adjusted in a wide range of values by selecting the external resistor value R accordingly.
  • the generated reference current can be used within the integrated circuit for different functionalities such as adjusting a frequency, output current or a delay time etc.
  • the external resistor is partly damaged or broken with the consequence that the integrated circuit receives a reference current I ref generated by the integrated reference current generation circuit connected to the external reference resistor with a wrong current strength and operates outside specified parameter ranges. Moreover, a deviation of the generated reference current from a desired set reference current cannot be detected or diagnosed and no correction of the situation will be performed.
  • Fig. 1 shows a conventional circuit which is used in a conventional integrated circuit to avoid the above-mentioned disadvantages, in particular a situation where a reference current with a wrong reference current value is generated because an external reference resistor has been damaged or a wire to the external reference resistor has been cut.
  • the integrated circuit IC comprises the reference current generation circuit three times each circuit being connected to a corresponding external resistor R ref .
  • the reference current generation circuits in the conventional integrated circuit IC as shown in Fig. 1 are connected to an arbiter circuit which monitors if any of the three reference currents is deviating more than a preset percentage from the other two reference currents. If the arbiter circuit detects that one of the reference currents I ref is deviating too far from the other two reference currents, it selects one of the unaffected two other reference currents and outputs an error flag indicating that an error in one of the reference current generation circuits has occurred.
  • a disadvantage of the conventional integrated circuit IC shown in Fig. 1 is that three network connection pins have to be used to connect three external reference resistors R ref to the integrated circuit IC. Further, the space for providing pins connecting the integrated circuit IC to the external electronic circuitry is limited. Moreover, each network connection pin used for one of the integrated reference current generation circuits can not be used for other purposes so that the functionality of the integrated circuit IC is limited.
  • US 2008/0073976 A1 relates to a method for increasing the availability and redundancy of an analogue current output.
  • a first set of current sources is activated to generate an output current.
  • a current source of this first set of current sources is cyclically checked for serviceability, and a resulting output current is generated in equal parts by other current sources of the first set of current sources. If an unserviceability of a checked current source is determined, the respective current source is disconnected.
  • an object of the present invention to provide an integrated circuit having an integrated reference current generation circuit which provides a constant reference current even when one external resistor value deviates from a set value and which needs less connection pins for connecting external reference resistors to the integrated circuit.
  • the integrated circuit according to the present invention provides an integrated reference circuit that detects any deviation of a resistor value and compensates this deviation such that the value of the generated reference current I ref remains unaffected and unchanged.
  • a fourth integrated switch is adapted to interrupt a first external current flowing through an integrated transistor and a first network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fourth switch by said integrated control circuit.
  • a fifth integrated switch is adapted to interrupt a second external current flowing through an integrated transistor via a second network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fifth switch by said integrated control circuit.
  • said integrated control circuit detects a change from a predetermined ratio between the first and second external current it turns off consecutively the first external current and the second external current by controlling the fourth and fifth integrated switch and compares measured voltages at the first and second network connection pin of said integrated circuit with expected voltages at the first and second network connection pin of said integrated circuit to identify a failing resistor of said external reference resistor network.
  • control circuit is adapted to control the integrated switches such that the identified failing resistor of said external reference resistor network is shortened to maintain the reference current generated by said integrated reference current generation circuit constant.
  • the reference resistor network is connected via wires to the network connection pins of said integrated circuit and comprises resistors each having a predetermined reference resistance.
  • the external reference resistor network comprises three reference resistors in a ⁇ -configuration connected to a first and second network connection pin of said integrated circuit.
  • a first reference resistor of said external reference resistor network is connected between both network connection pins of said integrated circuit.
  • a second reference resistor of said external reference resistor network is connected between a first network connection pin of said integrated circuit and a reference potential.
  • a third reference resistor is connected between a second network connection pin of said integrated circuit and a reference potential.
  • the integrated reference current generation circuit comprises a first reference voltage source adapted to generate a first reference voltage and a second reference voltage source adapted to generate a second reference voltage being higher than the first reference voltage by a predetermined voltage ratio.
  • the integrated control circuit generates an error flag signal indicating that a failure has occurred in said external reference resistor network if such a failure is detected by said integrated control circuit.
  • the integrated circuit IC 1 comprises at least one integrated reference current generation circuit 2 generating an internal reference current I ref used by circuits of the integrated circuit IC for different functions such as adjusting a frequency, an output current or a delay time etc.
  • the reference current generation circuit 2 is connected to an integrated control circuit 3 of the IC 1.
  • the reference current generation circuit 2 of the IC 1 is connected via a first and second network connection pin 4-1, 4-2 to an external reference resistor network 5 comprising in the shown implementation three resistors 6-1, 6-2, 6-3 connected to each other in a ⁇ circuit configuration and having the reference resistor values R1, R2, R3, respectively.
  • the integrated reference current generation circuit 2 is adapted to generate a reference current I ref for the integrated circuit 1 and has reference voltage sources each supplying a reference voltage via a first and second integrated switch to a corresponding amplifier that is adapted to regulate a control voltage of an integrated transistor connected to the respective amplifier such that the generated reference current is a weighted sum of the external currents I 1 , I 2 each flowing through one of the integrated transistors via the network connections pins 4-1, 4-2 of the integrated circuit 1 to the external reference resistor network 5 connected to the integrated circuit 1 as shown in Fig. 2 .
  • the network connection pins 4-1, 4-2 are connectable to each other by means of a third integrated switch SW3 and to a reference potential GND by means of a first switch SW1 and second switch SW2 integrated in the integrated circuit IC 1 as shown in Fig. 3 .
  • the integrated control circuit 3 as shown in Fig. 2 is adapted to detect a failure in the external reference resistor network 5 on the basis of the monitored external currents I 1 , I 2 of the integrated switches IC such that the reference current I ref generated by said integrated reference current generation circuit 2 is maintained constant even if a failure occurs in said external reference resistor network 5.
  • Fig. 3 shows a possible embodiment of an integrated circuit 1 according to the present invention in more detail.
  • the integrated reference current generation circuit 2 comprises a first reference voltage source 7 connected by means of a connection pin 8 to a reference potential GND as shown in Fig. 3 .
  • the integrated circuit 1 comprises a second reference voltage source 9 generating a second reference voltage.
  • the first reference voltage source 7 is connected via first controllable switch SW1 of the IC 1 to a corresponding amplifier 10 being a differential amplifier that is adapted to regulate a control voltage of an integrated transistor 11 connected to the output of the respective differential amplifier 10 such that a first external current I 1 flows through the first network connection pin 4-1 to the external reference resistor network 5.
  • the second reference voltage source 9 supplies the generated reference voltage also to an input of a differential amplifier 12 whose output is connected to a second transistor 13.
  • the differential amplifier 12 is connected to regulate a control voltage of the integrated second transistor 13 connected to the differntial amplifier such that a second current I 2 flows through the second network connection pin 4-2 to the external reference resistor network 5.
  • transistor 11 is a MOSFET having a gate connected to the output of the operational amplifier 10 to which a similar transistor 11' is connected in parallel such that the external current I 1 flowing through the connection pin 4-1 is split according to a 1:1 ratio so that half of the amplitude of the external current I 1 is applied to integrated control circuit 3 if a fourth integrated switch SW4 of the IC 1 is closed.
  • the transistors 13', 13" are connected in parallel to the other transistor 13 so that the external current I 2 is split and a predetermined fraction of the current I 2 is applied to the integrated control circuit 3 if the switch SW5 of the IC 1 is closed.
  • the generated reference current I ref is output by the integrated reference current generation circuit 2 ??? is a weighted sum of the external currents I 1 , I 2 flowing through one of the integrated transistors 11, 13 and the network connection pins 4-1, 4-2 of said integrated circuit 1 to the external reference resistor network 5 connected to the integrated circuit 1.
  • the first and second network connection pin 4-1, 4-2 can be connected to each other by means of a third integrated switch SW3 controlled by the integrated control circuit 3. Moreover, the network connection pins 4-1, 4-2 can also be connected to a reference potential GND by means of the controlled first and second switch SW1, SW2 as shown in Fig. 3 .
  • the integrated circuit 1 further comprises a fourth integrated switch SW4 which is adapted to interrupt a first external current I 1 flowing through a first integrated transistor 11 of the first network connection pin 4-1 of said integrated circuit 1 to said external reference resistor network 5 in response to a control signal applied to the fourth switch SW4 by said integrated control circuit 3 as shown in Fig. 3 .
  • the fifth integrated switch SW5 is adapted to interrupt the second external current I 2 flowing through an integrated transistor 13 of the second network connection pin 4-2 of said integrated circuit 1 to said external reference resistor network 5 in response to a control signal applied to said fifth switch SW5 by said integrated control circuit 3.
  • the integrated control circuit 3 detects a change from a predetermined ratio between the first and second external current I 1 , I 2 it turns off consecutively the first external current I 1 and the second external current I 2 by controlling the fourth and fifth integrated switch SW4, SW5 and then compares the measured voltages at the first and second network connection pin 4-1, 4-2 of said integrated circuit IC 1 with expected voltages at the first and second network connection pin 4-1, 4-2 of said integrated circuit 1 to identify a failing resistor of the external reference resistor network 5.
  • the integrated control circuit 3 is further adapted to control the integrated switches SW1, SW2, SW3, SW4, SW5 such that the identified failing resistor of the external reference resistor network 5 is shortcut to maintain the reference current I ref generated by the integrated reference current generation circuit 2 constant.
  • the external reference resistor network 5 comprises three reference resistors 6-1, 6-2, 6-3 with a ⁇ configuration connected to the first and second network connection pin 4-1, 4-2 of the integrated circuit 1.
  • the first reference resistor 6-1 of said external reference resistor network 5 is connected between both network connection pins 4-1, 4-2 of the integrated circuit 1.
  • a second reference resistor 6-2 of said external reference resistor network is connected between a first network connection pin 4-1 of said integrated circuit 1 and a reference potential that can be formed by a ground potential GND.
  • a third reference resistor 6-3 of the reference resistor network 5 is connected between the second network connection pin 4-2 of said integrated circuit 1 and the reference potential GND as shown in Fig. 3 .
  • the third reference resistor 6-3 comprises a resistance value of 3/5 R wherein R is the resistance values of the two other reference resistors 6-1, 6-2 of the reference resistor network 5.
  • the control circuit 3 can identify the failing resistor by consecutively switching off I 1 and I 2 and by comparing the sensed voltage at the terminals with expected reference voltages. Accordingly, the integrated control circuit 3 is able to identify at each of the three resistors 6-1, 6-2, 6-3 within the external reference resistor network 5 an occurred malfunction and then to shortcut the identified faulty resistor such that the generated reference current I ref is maintained constant.
  • the control circuit 3 can deactivate the identified faulty resistor by controlling the integrated switches SW1, SW2, SW 3 accordingly.
  • the first resistor 6-1 is shortcut in case that its resistance value deviates from a preset value too much. Consequently, if a single faulty resistor within the external resistor network 5 is detected the control circuit 3 can perform a switching operation such that the generated reference current I ref is constant and is unaffected by the faulty resistor.
  • the reference current I ref generated by the integrated reference current generation circuit 2 is maintained constant and decreases by a predetermined percentage. Accordingly, in this scenario or situation the circuit according to the present invention operates such that a predetermined percentage of the reference current I ref is still generated although a wire has been cut. In a possible embodiment if a wire cut is detected this causes a decrease of the reference current I ref of less than 19%.
  • the control circuit 3 generates in case of a malfunction an error signal (ERROR) indicating that a malfunction of the external reference resistor network 5 has occurred.
  • This error signal can also indicate what type of malfunction has occurred, i.e. it can indicate whether there is a faulty resistor 6 in the reference resistor network 5 or a cut wire.
  • the ERROR signal also indicates which resistor 6-i is faulty or which wire has been interrupted to a higher software layer.
  • Fig. 4 shows a possible printed circuit board PCB design which can be used for connecting an integrated circuit 1 according to the present invention with an external reference resistor network 5.
  • the separation of wires for all three resistors 6-1, 6-2, 6-3 reduces the risk of a wire cut.
  • a wire cut error can only occur as a soldering error or a IC pin to the PCB. This is diagnosed and has an effect in reducing less than 19% of the reference current I ref generated by the reference current generation circuit 2. Further, a loss of ground wire is prevented by double ground wires via ground connection of the integrated circuit 1.
  • the integrated circuit 1 according to the present invention can be used in automotive applications.
  • the integrated circuit IC 1 is compliant with ISO 26262 being an automotive safety standard.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Claims (14)

  1. Circuit intégré, CI, (1) pouvant être connecté à un réseau de résistances externes (5) comprenant trois résistances (6-1, 6-2, 6-3) selon une configuration en n, le circuit intégré (1) comprenant :
    - un circuit intégré de production de courant de référence (2) conçu pour produire un courant de référence (Iref) destiné audit circuit intégré (1), et comportant une première de source tension de référence (7), un premier interrupteur intégré (SW1), un premier amplificateur (10), un premier transistor intégré (11), une première broche de connexion au réseau (4-1), une seconde source de tension de référence (9), un deuxième interrupteur intégré (SW2), un second amplificateur (12), un second transistor intégré (13) et une seconde broche de connexion au réseau (4-2),
    - dans lequel ladite première source de tension de référence (7) fournit une tension de référence (Vref1) par l'intermédiaire dudit premier interrupteur intégré (SW1) audit premier amplificateur (10) ;
    - ladite seconde source de tension de référence (9) fournit une tension de référence (Vref2) par l'intermédiaire dudit deuxième interrupteur intégré (SW2) audit second amplificateur (12) ;
    - le courant de référence produit (Iref) est une somme pondérée d'un premier courant (I1) circulant à travers ledit premier transistor intégré (11) par l'intermédiaire de ladite première broche de connexion au réseau (4-1), et d'un second courant (I2) circulant à travers ledit second transistor intégré (13) par l'intermédiaire de ladite seconde broche de connexion au réseau (4-2) dudit circuit intégré (1), vers ledit réseau de résistances étalons externes (5) pouvant être connecté audit circuit intégré, CI (1) ; et
    - lesdites broches de connexion au réseau (4-1, 4-2) peuvent être connectées l'une à l'autre au moyen d'un troisième interrupteur intégré (SW3) et à un potentiel de référence (GND) au moyen desdits premier et deuxième interrupteurs (SW1, SW2) ;
    - ledit circuit intégré (1) comprenant en outre un circuit intégré de commande (3) conçu pour détecter une défaillance dans ledit réseau de résistances étalons externes (5) sur la base des premier et second courants (I1, I2) et pour commander lesdits interrupteurs intégrés (SW1, SW2, SW3), de manière que le courant de référence (Iref) produit par ledit circuit intégré de production de courant de référence (2) soit maintenu constant si une défaillance survient dans ledit réseau de résistances étalons externes (5) ;
    - un quatrième interrupteur intégré (SW4) conçu pour interrompre le premier courant (I1) circulant à travers ledit premier transistor intégré (11) et ladite première broche de connexion au réseau (4-1) dudit circuit intégré (1) vers ledit réseau de résistances étalons externes (5), en réponse à un signal de commande appliqué audit quatrième interrupteur (SW4) par ledit circuit intégré de commande (3) ; et
    - un cinquième interrupteur intégré (SW5) conçu pour interrompre ledit second courant (I2) circulant à travers ledit second transistor intégré (13) par l'intermédiaire de ladite seconde broche de connexion au réseau (4-2) dudit circuit intégré (1) vers ledit réseau de résistances étalons externes (5), en réponse à un signal de commande appliqué audit cinquième interrupteur (SW5) par ledit circuit intégré de commande (3).
  2. Circuit intégré selon la revendication 1,
    dans lequel si le circuit intégré de commande (3) détecte une variation par rapport à un rapport prédéterminé entre le premier et le second courant externe (I1, I2), il coupe successivement le premier courant (I1) et le second courant (I2) en commandant les quatrième et cinquième interrupteurs intégrés (SW4, SW5) et compare des tensions mesurées au niveau des première et seconde broches de connexion au réseau (4-1, 4-2) dudit circuit intégré (1) avec des tensions attendues au niveau des première et seconde broches de connexion au réseau (4-1, 4-2) dudit circuit intégré (1) pour identifier une résistance défaillante (6-1) dudit réseau de résistances étalons externes (5).
  3. Circuit intégré selon la revendication 2,
    dans lequel le circuit intégré de commande (3) est conçu pour commander les interrupteurs intégrés (SW1, SW2, SW3, SW4, SW5), de manière que la résistance défaillante identifiée dudit réseau de résistances étalons externes (5) soit mise en court-circuit pour maintenir le courant de référence (Iref) produit par ledit circuit intégré de production de courant de référence (2) constant.
  4. Circuit intégré selon l'une des revendications 1 à 3 précédentes,
    dans lequel ledit réseau de résistances étalons (5) peut être connecté par l'intermédiaire de fils aux broches de connexion au réseau (4-1, 4-2) dudit circuit intégré (1) et comprend des résistances (6) ayant chacune une valeur de résistance de référence prédéterminée.
  5. Circuit intégré selon l'une des revendications 1 à 4 précédentes,
    dans lequel les trois résistances étalons (6-1, 6-2, 6-3) dudit réseau de résistances étalons externes (5) peuvent être connectées auxdites première et seconde broches de connexion au réseau (4-1, 4-2) dudit circuit intégré (1).
  6. Circuit intégré selon l'une des revendications 1 à 5 précédentes,
    - dans lequel une première résistance étalon (6-1) dudit réseau de résistances étalons externes (5) peut être connectée entre les deux broches de connexion au réseau (4-1, 4-2) dudit circuit intégré,
    - une deuxième résistance étalon (6-2) dudit réseau de résistances étalons externes (5) peut être connectée entre une première broche de connexion au réseau (4-1) dudit circuit intégré (1) et un potentiel de référence, et
    - une troisième résistance étalon (6-3) peut être connectée entre une seconde broche de connexion au réseau (4-2) dudit circuit intégré (1) et ledit potentiel de référence.
  7. Circuit intégré selon l'une des revendications 1 à 6 précédentes,
    dans lequel ladite seconde tension de référence (Vref2) est supérieure à la première tension de référence d'un rapport de tension prédéterminé (K).
  8. Circuit intégré selon l'une des revendications 1 à 7 précédentes,
    dans lequel ledit courant de référence (Iref) est une somme pondérée du premier courant (I1) circulant à travers un premier transistor intégré (11) et la première broche de connexion (4-1) dudit circuit intégré (1) vers ledit réseau de résistances étalons externes (5), et du second courant (I2) circulant à travers un second transistor intégré (13) et la seconde broche de connexion au réseau (4-2) dudit circuit intégré vers ledit réseau de résistances étalons externes (5) : I ref = I 1 + m ⋅ I 2 ,
    Figure imgb0013
     où m est un facteur de pondération prédéterminé.
  9. Circuit intégré selon la revendication 8,
    dans lequel le courant de référence (Iref) produit par ledit circuit intégré de production de courant de référence (2) au cours d'un fonctionnement normal est donné par : I ref = 1 R 2 + m − 1 K − 1 1 R 1 + m ⋅ K 1 R 3 ⋅ Vref 1 2
    Figure imgb0014
     où
    R1, R2, R3 sont des valeurs de résistance des première, deuxième et troisième résistances étalons (6-1, 6-2, 6-3) dudit réseau de résistances étalons (5),
    m est le facteur de pondération,
    K est le rapport de tension prédéterminé,
    Vref1 est la tension de référence produite par la première source de tension de référence (7).
  10. Circuit intégré selon la revendication 8 ou 9, dans lequel la somme du facteur de pondération (m) et du rapport de tension (K) est fixée à la valeur de 2 : m + K = 2
    Figure imgb0015
    le facteur de pondération (m) étant inférieur à 1 (m < 1), et
    le rapport de tension (K) étant supérieur à 1 (K > 1).
  11. Circuit intégré selon l'une des revendications 5 à 10 précédentes,
    dans lequel les valeurs de résistance (R1, R2) des première et deuxième résistances étalons (6-1, 6-2) dudit réseau de résistances étalons (5) sont égales (R1 = R2 = R).
  12. Circuit intégré selon la revendication 10 ou 11, dans lequel pour que le rapport de tension (K) soit réglé à K = 1,5 et que le facteur de pondération (m) soit réglé à m = 0,5, la troisième résistance étalon (6-3) a une valeur de résistance égale à 3/5 R, R représentant les valeurs de résistance des première et deuxième résistances étalons (6-1, 6-2) dudit réseau de résistances étalons (5).
  13. Circuit intégré selon l'une des revendications 1 à 12 précédentes,
    dans lequel si un fil connectant ledit réseau de résistances étalons externes (5) audit circuit intégré (1) est coupé, le courant de référence (Iref) produit par ledit circuit intégré de production de courant de référence (2) est maintenu et ne diminue pas d'un pourcentage prédéterminé.
  14. Circuit intégré selon l'une des revendications 1 à 13 précédentes,
    dans lequel ledit circuit intégré de commande (3) produit un signal indicateur d'erreur indiquant qu'une défaillance est survenue dans ledit réseau de résistances étalons externes (5) si une telle défaillance est détectée par ledit circuit intégré de commande (3).
EP12175926.0A 2012-07-11 2012-07-11 Circuit intégré avec un réseau de résistances de références externes Not-in-force EP2701028B1 (fr)

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