EP2676204B1 - Interface série - Google Patents

Interface série Download PDF

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Publication number
EP2676204B1
EP2676204B1 EP20120705392 EP12705392A EP2676204B1 EP 2676204 B1 EP2676204 B1 EP 2676204B1 EP 20120705392 EP20120705392 EP 20120705392 EP 12705392 A EP12705392 A EP 12705392A EP 2676204 B1 EP2676204 B1 EP 2676204B1
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EP
European Patent Office
Prior art keywords
slave
master
data
line
connection
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EP20120705392
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German (de)
English (en)
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EP2676204A1 (fr
Inventor
Vinayak Kariappa CHETTIMADA
Bjørn Tore TARALDSEN
Per Carsten SKOGLUND
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Nordic Semiconductor ASA
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Nordic Semiconductor ASA
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Definitions

  • This invention relates to a serial interface.
  • Serial interfaces are commonly used to allow one electrical component or device to communicate binary data to another, one bit at a time.
  • a microcontroller unit (MCU) and a radio chip mounted on a printed circuit board (PCB) may use a serial interface comprising tracks on the PCB to communicate data between each other.
  • MCU microcontroller unit
  • PCB printed circuit board
  • the use of a serial bus, rather than a parallel bus, in such a situation can be desirable as it does not require a large number of pins on the integrated-circuits, thereby saving space.
  • Serial Peripheral Interface This provides synchronous communication between a master device and a slave device. It uses a clock line, over which the master device can transmit a clock signal, and two data lines, one for each direction of data flow. Data exchange is synchronised by the clock signal.
  • SPI Serial Peripheral Interface
  • a problem with SPI is that it provides no mechanism whereby a slave device can initiate communication with the master device.
  • US 2006/0143348 describes an "extended" SPI in which a slave can issue an interrupt to a master. Data content can be transferred either from the master to the slave, or from the slave to the master.
  • the invention provides a data-exchange system according to claim 1.
  • the invention provides a master device according to claim 10.
  • the transmitting of both messages starts simultaneously, preferably with the least significant bit of each message being transmitted simultaneously at the first clock signal.
  • Some embodiments can be used in a method of full-duplex communication between a master device and a slave device over a serial interface comprising five separate lines, being a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line, the method comprising:
  • the master device in a first transaction, the master device sending a master transmission request signal to the slave device over the request line; the slave device receiving the master transmission request signal and, in response, sending a slave transmission accept signal to the master device over the ready line; the master device receiving the slave transmission accept signal and, in direct response, transmitting binary data to the slave device over the master-to-slave data line; and
  • the slave device in a second transaction, the slave device sending a slave transmission request signal to the master device over the ready line or over a slave-request line; the master device receiving the slave transmission request signal and, in response, sending a master transmission accept signal to the slave device over the request line or over a master-ready line; the slave device receiving the master transmission accept signal and, in direct response, transmitting binary data to the master device over the slave-to-master data line; wherein, in at least one of the first and second transactions, the master device transmits data over the master-to-slave at the same time as the slave device transmits binary data over the slave-to-master data line.
  • serial interface can allow either the slave device or the master device to initiate communication, while avoiding conflicts as to which is first to initiate the communication, and while supporting full-duplex communication between the two devices (i.e. simultaneous data flow in both directions).
  • Such an arrangement allows for the efficient flow of data in either or both directions, without, for example, the slave having to await a poll command from the master device before being able to send data. This can therefore result in faster response times by the master (or slave) device when an event occurs at the slave (or master) device.
  • the slave device when the slave device receives a radio packet, it can at once indicate its desire to convey the contents of the received packet to an MCU (master device), and can start transmitting the contents to the MCU as soon as the MCU acknowledges the slave transmission request signal, without needing to wait to be polled by the MCU.
  • MCU master device
  • the communication system comprises a master device, a slave device and a serial interface, wherein the serial interface comprises five separate lines, being a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line, wherein:
  • the master device comprises five serial interface connections, being a clock connection, a request connection, a ready connection, a master-to-slave data connection, and a slave-to-master data connection, wherein:
  • the slave device comprises five serial interface connections, being a clock connection, a request connection, a ready connection, a master-to-slave data connection, and a slave-to-master data connection, wherein:
  • the clock connection (e.g. a pin) may be connected to a clock line (e.g. a PCB track).
  • a clock line e.g. a PCB track.
  • any or all of the request connection, ready connection, master-to-slave data connection and slave-to-master data connection may be connected to respective lines.
  • the slave-request connection may be connected to a slave-request line
  • the master-response connection may be connected to a master-response line.
  • the clock connection, master-to-slave data connection and slave-to-master data connection may be connected to an SPI bus.
  • the master device preferably maintains the request line at one of two possible states. For convenience, these will be referred to as high and low states. They may correspond to high and low voltages, or to low and high voltages, respectively.
  • the master transmission request signal may comprise a toggling of the state of the request line. In some embodiments, the master transmission request signal comprises lowering the request line from high to low.
  • the slave device preferably maintains the ready line at one of two possible states. For convenience, these will be referred to as high and low states. They may correspond to high and low voltages, or to low and high voltages, respectively.
  • the slave transmission accept signal may comprise a toggling of the state of the ready line. In some embodiments, the slave transmission accept signal comprises lowering the ready line from high to low.
  • the slave transmission request signal may comprise a toggling of the state of the ready line.
  • the slave transmission request signal comprises lowering the ready line from high to low.
  • the master transmission accept signal may comprise a toggling of the state of the request line.
  • the master transmission accept signal comprises lowering the request line from high to low.
  • the master-to-slave data line and slave-to-master data line may operate independently of each other, or the system may be configured so that both lines are active together. In the latter case, if only one of the devices has data to transmit, the other device may transmit null or dummy data (e.g. all zero bits).
  • the master device may be configured to transmit the clock signal only when transmitting and/or receiving binary data.
  • the master device is capable of transmitting a message to the slave device at the same time as the slave device transmits a message to the master device where the messages are not of the same length as each other. If the slave-to-master and master-to-slave data lines are always activated together, then the device which has the shorter message to send may append dummy or null data to the end of the shorter message, e.g. to make it equal to the length of the longer message.
  • the slave device is configured to transmit a message containing information relating to its length.
  • Other messages may also contain information relating to their lengths.
  • a message may contain a length number which conveys the length of the whole message.
  • the first byte of the message may be the total number of bytes of the message or of a variable-length data portion of the message.
  • the master device is configured to receive message-length information from the slave device (e.g. over the slave-to-master data line) and to use the message-length information to determine when to end a transaction.
  • Embodiments of the invention may be used in a method of exchanging data between a master device and a slave device over a synchronous serial connection, comprising the slave device transmitting a binary message containing message-length information to the master device at the same time as the master device transmits a binary message to the slave device, wherein the master device sends a transmission end signal to the slave device once the master device has both (i) received a number of message bits from the slave device corresponding to the message-length information, and (ii) transmitted all the bits of the message the master device is transmitting to the slave device.
  • a transaction (i.e. a period of continuous or sustained communication) may be ended by the master device sending a master transmission end signal to the slave device over the request line or over an end-signal line.
  • a transaction may be ended by the master device stopping sending a clock signal over the clock line.
  • a master transmission end signal may comprise a toggling of the state of the request line.
  • the master transmission end signal comprises raising the request line from low to high.
  • the slave device may be configured to toggle the state of the ready line in response to receiving a master transmission end signal. In some embodiments, the slave device raises the ready line from low to high in response to receiving a master transmission end signal.
  • the master device may be configured to check the state of the ready or request line (or both) before sending a master transmission request signal, and to send the master transmission request signal only if the state of the line satisfies a master transmission condition.
  • the master transmission condition may be that the line is high.
  • the slave device may be configured to check the state of the ready or request line (or both) before sending a slave transmission request signal, and to send the slave transmission request signal only if the state of the line satisfies a slave transmission condition.
  • the slave transmission condition may be that the line is high.
  • the master device preferably comprises a transmit buffer and a receive buffer. These may be one and the same buffer (e.g. a single 8-bit buffer), in which case bits may be transmitted from one end of the buffer and received at the other end (a cyclic buffer). However, preferably, they are separate buffers.
  • the master device may comprise a plurality of transmit buffers and/or a plurality of receive buffers.
  • a controller in the master device (which might comprise hardware logic or software) may be configured to select one of the buffers to be an active transmit buffer, and the active buffer may be used for the current or next transmit operation.
  • An active receive buffer may be selected similarly.
  • the slave device may comprise a single transmit and receive buffer, but preferably comprises one or more transmit buffers and one or more separate receive buffers.
  • the slave device may comprise a controller configured to select an active transmit and/or receive buffer.
  • the buffers on the master and slave devices may all be the same size (e.g. 8 bits, or a constant number of bytes), or they may be of different sizes.
  • the buffer(s) of the master and/or slave device may be implemented in hardware or software.
  • the slave device may be configured to request retransmission of a message from the master device if the slave device determines that the master device has ended the transaction before the complete message has been received by the slave device.
  • the message may contain message-length information and the slave device may be configured to use this information to determine whether a corresponding number of message bits has been received when the slave device receives a master transmission end signal.
  • the retransmission request may be made using the ready line and/or the slave-to-master data line.
  • the slave device may send a slave transmission request signal over the ready line and then transmit a message to the master device which comprises a predetermined retransmission request.
  • the master device may be, or comprise, a microcontroller or central processor unit.
  • the slave device may be, or comprise, a microcontroller or central processor unit.
  • the present invention is particularly suited to software control of both the master and slave devices.
  • the slave device might be, or comprise, a hardware device, e.g. a connectivity chipset such as a radio-on-a-chip, or some other component not necessarily having a general-purpose processor.
  • connection lines of the interface may take any suitable form. They may be optical, but are preferably electrical.
  • a cable comprising at least five connection lines may connect between the master device and the slave device; however, in preferred embodiments, the connection lines are formed on a PCB.
  • the master device and slave device may be integrated on a single silicon chip, and the connection lines may comprise conductors on the silicon chip.
  • Data bits are preferably transmitted at the same rate as the clock signal; i.e. one bit per clock pulse. Data may be transmitted and read on the rising or falling edge of the clock signal. In some embodiments, data is captured on the rising edge of the clock and transmitted on the falling edge.
  • a slave select line may connect the master device to the slave devices and may be used to select one of the slave devices to be active, as is known from SPI. If the lines are shared between all the slave devices, an inactive slave device may be configured to ignore signals on the request and master-to-slave data connection lines, and not to transmit any signals on the ready and slave-to-master data connection lines.
  • each slave device can have its own ready line, and optionally its own request line, connecting with the master device.
  • a slave device is able to send a slave transmission request signal to the master device even during a transaction between the master device and another slave device, and to await a master transmission accept signal.
  • the clock line, master-to-slave data line and slave-to-master data lines may still be shared between a plurality of slave devices, thereby saving space compared with having entirely independent serial interfaces to each slave device.
  • Figure 1 shows an MCU 1 and an integrated single-chip radio transceiver 2. These may be separate packages mounted on a common PCB, for example.
  • the MCU 1 and radio have a five-line serial bus 3 between them, which may be formed from tracks on the PCB.
  • the serial lines are: a request line (REQN), a ready line (RDYN), a clock line (CLK), a master-out slave-in data line (MOSI) and a master-in slave-out data line (MISO).
  • MISO Input Output SPI Master In Slave Out MOSI Output Input SPI: Master Out Slave In CLK Output Input SPI: Serial data Clock REQN Output Input MCU to radio handshake signal RDYN Input Output Radio to MCU handshake signal
  • a software application running on the MCU 1 may use the serial connection to send data to the radio 2, such as commands and messages to be transmitted by the radio, and to receive data from the radio 2, such as status information and messages received by the radio.
  • FIG. 2 shows certain components within the radio 2 which are used for controlling the serial interface.
  • the clock line, request line and ready line connect to an Application Controller Interface (ACI) control component 4.
  • the master-out slave-in data line connects to a MOSI-to-buffer control component 5, while the master-in slave-out data line connects to a MISO-to-buffer control component 6.
  • the MOSI-to-buffer control component 5 can write to any of n receive (RX) buffers 7.
  • the MISO-to-buffer control component 6 can read from any of m transmit (TX) buffers 8.
  • the ACI control component 4, buffer control components 5, 6 and RX and TX buffers 7, 8 are all implemented in hardware.
  • the ACI control component 4 has connections to the two buffer control components 5, 6, the RX buffers 7, the TX buffers 8, and an Application Controller Interface (ACI) driver component 9, which may be implemented in hardware or software.
  • the ACI driver component 9 interfaces between the serial connection buffers and other components of the radio transceiver.
  • the MCU 1 may have a similar or identical arrangement to that shown in Figure 2 , albeit with the directions of each connection line reversed.
  • the MCU 1 can request communication with the radio 2 by placing the REQN line to ground.
  • the radio 2 if ready for communication, will place the RDYN line to ground; otherwise it will keep it high until it is ready.
  • the MCU 1 starts data transmission once it sees the RDYN line is placed to ground.
  • the radio 2 can request communication with the MCU 1 by placing the RDYN line to ground.
  • the MCU 1 responds by acknowledging by placing the REQN line to ground and starting the data transmission.
  • Data transmission is always coordinated by the MCU 1, which manages the clock signal on the CLK line.
  • the radio 2 When the radio 2 has lowered the RDYN line to ground to indicate its desire to transmit a message to the MCU 1, the radio 2 also places the least significant data bit of the message on the MISO line. If the MCU 1 also has data to send to the radio 2, it places the least significant data bit on the MOSI line and then raises the CLK line to high. The radio 2 receives the clock signal and reads the data bit from the MOSI line. At the same time, the MCU 1 reads the least significant data bit from the MISO line.
  • the MCU 1 then lowers the CLK line to ground and places the second-to-least significant data bit on the MOSI line.
  • the slave shifts the read data bit into an active RX buffer and places the second-to-least significant data bit on the MISO line.
  • Each data bit is transmitted on the falling edge of the clock and captured on the rising edge of the clock.
  • the ACI control component 4 handles flow control, negotiation, asymmetric data transmission and retransmission. It also supervises the buffer control components 5, 6 in connection with retransmission.
  • the ACI control component 4 is able to acknowledge on the RDYN line when the radio 2 is ready to receive a data transmission requested by the MCU 1. It can also indicate on the RDYN line when it has a request for the MCU 1 to initiate a data transmission when the radio 2 has data to transmit.
  • the ACI control component 4 has independent buffer control components 5, 6 for the MOSI line and the MISO line. If the ACI control component 4 detects a successful, complete transmission and/or reception, then it causes the MOSI buffer control component 5 to advance to the next receive and/or transmission buffer as the active buffer.
  • the ACI control component 4 checks with the MOSI and MISO buffer control components 5, 6 before sending a signal on the RDYN line to ensure that sufficient buffer space is available in either or both directions.
  • the buffer control components 5, 6 play the role of independent shift logic during data transmission.
  • the ACI control component 4 indicates from or to which buffer the shift or capture of data bits will occur.
  • the ACI driver component 9 has access to the ACI control component 4 and handles all incoming and outgoing data transmissions as requested by the MCU 1 and the radio chip 2.
  • Figure 3 shows the timing for a packet sent from the MCU 1 to the radio 2, relating to the following sequence of events:
  • the radio 2 If the radio 2 has data waiting to be sent to the MCU 1, it can transmit this concurrently with the transmission from the MCU 1.
  • Figure 4 shows the timing for a packet sent from the radio 2 to the MCU 1, relating to the following sequence of events:
  • the MCU 1 If the MCU 1 has data waiting to be sent to the radio 2, it can transmit this concurrently with the transmission from the radio 2.
  • the maximum length of a packet can be decided in the implementation based on the buffer size available.
  • the MCU 1 and radio 2 can receive and transmit data in full duplex mode.
  • Having the length of the message embedded in the transmission data allows the MCU 1 to clock the maximum of the lengths of concurrently-transmitted messages, thereby ensuring all data bits reach the radio 2 and the MCU 1.
  • the ACI control component 4 can detect an incomplete transmission. This can cause the radio 2 to request a retransmission.
  • Error detection may be implemented at a higher protocol level.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
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Claims (15)

  1. Système d'échange de données comprenant un dispositif maître (1) selon la revendication 10, un dispositif asservi (2) et une connexion sérielle synchrone (3) entre eux, dans lequel le dispositif asservi est configuré pour transmettre ledit message binaire esclave-maître, contenant des données et des informations de longueur de message se rapportant à la longueur du message binaire esclave-maître, au dispositif maître en même temps que le dispositif maître transmet ledit message binaire maître-esclave, contenant des données, au dispositif asservi.
  2. Système d'échange de données selon la revendication 1 configuré pour démarrer la transmission des deux messages simultanément.
  3. Système d'échange de données selon la revendication 1 ou la revendication 2, dans lequel la connexion sérielle (3) comprend cinq lignes séparées, à savoir une ligne d'horloge, une ligne de demande, une ligne de mode prêt, une ligne de données maître-esclave et une ligne de données esclave-maître, et dans lequel le dispositif maître (1) est configuré :
    pour transmettre un signal d'horloge au dispositif asservi (2) via la ligne d'horloge ; et
    pour envoyer un signal de demande de transmission de maître au dispositif asservi via la ligne de demande, pour recevoir un signal d'acceptation de transmission d'esclave de la part du dispositif asservi via la ligne de mode prêt et, en réponse directe, pour transmettre ledit message binaire maître-esclave contenant des données au dispositif asservi via la ligne de données maître-esclave.
  4. Système d'échange de données selon la revendication 1 ou la revendication 2, dans lequel la connexion sérielle (3) comprend cinq lignes séparées, à savoir une ligne d'horloge, une ligne de demande, une ligne de mode prêt, une ligne de données maître-esclave et une ligne de données esclave-maître, et dans lequel le dispositif asservi (2) est configuré :
    pour recevoir un signal d'horloge du dispositif maître (1) via la ligne d'horloge ; et
    pour envoyer un signal de demande de transmission d'esclave au dispositif maître via la ligne de mode prêt ou via une ligne de demande d'esclave, pour recevoir un signal d'acceptation de transmission de maître de la part du dispositif maître via la ligne de demande ou via une ligne en mode prêt de maître et, en réponse directe, pour transmettre ledit message binaire esclave-maître contenant des données et des informations de longueur de message au dispositif maître via la ligne de données esclave-maître.
  5. Système d'échange de données selon l'une quelconque des revendications précédentes, dans lequel le dispositif maître (1) est configuré pour utiliser les informations de longueur de message reçues pour déterminer quand terminer la transaction.
  6. Système d'échange de données selon l'une quelconque des revendications précédentes, dans lequel le message binaire maître-esclave contient des informations se rapportant à sa longueur.
  7. Système d'échange de données selon la revendication 6, dans lequel le dispositif asservi (2) est configuré pour utiliser les informations de longueur de message reçues du dispositif maître (1) pour déterminer si un nombre correspondant de bits de message maître-esclave a été reçu lorsque le dispositif asservi reçoit le signal de fin de transmission.
  8. Système d'échange de données selon la revendication 6 ou la revendication 7, dans lequel le dispositif asservi (2) est configuré pour demander la retransmission du message binaire maître-esclave issu du dispositif maître (1) si le dispositif asservi détermine que le dispositif maître a terminé la transaction avant que le message binaire complet maître-esclave n'ait été reçu par le dispositif asservi.
  9. Système d'échange de données selon l'une quelconque des revendications précédentes, dans lequel la connexion sérielle (3) comprend cinq lignes séparées, à savoir une ligne d'horloge, une ligne de demande, une ligne de mode prêt, une ligne de données maître-esclave et une ligne de données esclave-maître, dans lequel :
    le dispositif maître (1) est configuré pour transmettre un signal d'horloge au dispositif asservi (2) via la ligne d'horloge ;
    le dispositif maître est configuré, dans une première transaction, pour envoyer un signal de demande de transmission de maître au dispositif asservi via la ligne de demande ; le dispositif asservi est configuré pour recevoir le signal de demande de transmission de maître et, en réponse, envoyer un signal d'acceptation de transmission d'esclave au dispositif maître via la ligne en mode prêt ; le dispositif maître étant par ailleurs configuré pour recevoir le signal d'acceptation de transmission d'esclave et, en réponse directe, transmettre des données binaires au dispositif asservi via la ligne de données maître-esclave ;
    le dispositif asservi est configuré, dans une seconde transaction, pour envoyer un signal de demande de transmission d'esclave au dispositif maître via la ligne en mode prêt ou via une ligne de demande d'esclave ; le dispositif maître est configuré pour recevoir le signal de demande de transmission d'esclave et, en réponse, envoyer le signal d'acceptation de transmission de maître au dispositif asservi via la ligne de demande ou via une ligne de mode prêt du maître ; le dispositif asservi est par ailleurs configuré pour recevoir le signal d'acceptation de transmission de maître et, en réponse directe, transmettre des données binaires au dispositif maître via la ligne de données esclave-maître ; et
    le dispositif maître et le dispositif asservi sont capables de transmettre des données binaires en même temps l'un que l'autre dans au moins l'une des première et seconde transactions.
  10. Dispositif maître (1) configuré pour recevoir un message binaire esclave-maître d'un dispositif asservi (2), via une connexion sérielle synchrone (3), contenant des données et des informations de longueur de message se rapportant à la longueur du message binaire esclave-maître et, en même temps, pour transmettre un message binaire maître-esclave contenant des données au dispositif asservi via la connexion sérielle synchrone ; et encore configuré pour :
    déterminer une fois que le dispositif maître a à la fois (i) reçu un certain nombre de bits de message du dispositif asservi correspondant aux informations de longueur de message et (ii) transmis tous les bits du message binaire maître-esclave ; et
    envoyer un signal de fin de transmission au dispositif asservi en réponse à cette détermination.
  11. Dispositif maître (1) selon la revendication 10, dans lequel le dispositif maître comprend cinq connexions d'interface sérielle, à savoir une connexion d'horloge, une connexion de demande, une connexion de mode prêt, une connexion de données maître-esclave et une connexion de données esclave-maître, et est configuré :
    pour transmettre un signal d'horloge au dispositif asservi (2) via la ligne d'horloge ; et
    pour envoyer un signal de demande de transmission de maître au dispositif asservi par la connexion de demande, pour recevoir un signal d'acceptation de transmission d'esclave de la part du dispositif asservi par la connexion de mode prêt et, en réponse directe, transmettre ledit message binaire maître-esclave contenant des données au dispositif asservi par la connexion de données maître-esclave.
  12. Dispositif maître (1) selon la revendication 10 ou la revendication 11, dans lequel le dispositif maître comprend cinq connexions d'interface sérielle, à savoir une connexion d'horloge, une connexion de demande, une connexion de mode prêt, une connexion de données maître-esclave et une connexion de données esclave-maître, et est configuré :
    pour transmettre un signal d'horloge au dispositif asservi (2) via la ligne d'horloge ; et
    pour recevoir un signal de demande de transmission d'esclave du dispositif asservi par la connexion en mode prêt ou par une connexion de demande d'esclave et, en réponse, envoyer un signal d'acceptation de transmission de maître au dispositif asservi par la connexion de demande ou par une connexion de mode prêt de maître ; et pour recevoir ledit message binaire esclave-maître contenant des données et des informations de longueur de message de la part du dispositif asservi par la connexion de données esclave-maître.
  13. Dispositif maître (1) selon l'une quelconque des revendications 10 à 12, dans lequel le dispositif maître est configuré pour utiliser les informations de longueur de message reçues afin de déterminer quand terminer la transaction.
  14. Dispositif maître (1) selon l'une quelconque des revendications 10 à 13, dans lequel le message binaire maître-esclave contient des informations se rapportant à sa longueur.
  15. Dispositif maître (1) selon l'une quelconque des revendications 10 à 14, comprenant cinq connexions d'interface sérielle, à savoir une connexion d'horloge, une connexion de demande, une connexion de mode prêt, une connexion de données maître-esclave et une connexion de données esclave-maître, dans lequel le dispositif maître :
    est configuré pour transmettre un signal d'horloge au dispositif asservi (2) par la connexion d'horloge ;
    est configuré, dans une première transaction, pour envoyer un signal de demande de transmission du maître au dispositif asservi par la connexion de demande ; et pour recevoir un signal d'acceptation de transmission d'esclave de la part du dispositif asservi par la connexion de mode prêt et, en réponse directe, transmettre des données binaires au dispositif asservi par la connexion de données maître-esclave ;
    est configuré, dans une seconde transaction, pour recevoir un signal de demande de transmission d'esclave venant du dispositif asservi par la connexion de mode prêt ou par une connexion de demande de l'esclave et, en réponse, envoyer un signal d'acceptation de transmission de maître au dispositif asservi par la connexion de demande ou par une connexion de mode prêt de maître ; et pour recevoir des données binaires provenant du dispositif asservi par la connexion de données esclave-maître ; et
    est capable de transmettre des données binaires par la connexion de données maître-esclave en même temps qu'il reçoit des données binaires par la connexion de données esclave-maître dans au moins l'une des première et seconde transactions.
EP20120705392 2011-02-15 2012-02-14 Interface série Active EP2676204B1 (fr)

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GBGB1102594.7A GB201102594D0 (en) 2011-02-15 2011-02-15 Serial interface
PCT/GB2012/050324 WO2012110798A1 (fr) 2011-02-15 2012-02-14 Interface série

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EP2676204B1 true EP2676204B1 (fr) 2015-04-29

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JP (1) JP6061868B2 (fr)
KR (1) KR101812835B1 (fr)
CN (1) CN103460201B (fr)
GB (2) GB201102594D0 (fr)
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TWI507880B (zh) 2015-11-11
GB2488223B (en) 2014-01-01
WO2012110798A1 (fr) 2012-08-23
KR20140045324A (ko) 2014-04-16
EP2676204A1 (fr) 2013-12-25
US20140143461A1 (en) 2014-05-22
JP2014507035A (ja) 2014-03-20
GB2488223A (en) 2012-08-22
CN103460201B (zh) 2016-03-02
GB201102594D0 (en) 2011-03-30
JP6061868B2 (ja) 2017-01-18
CN103460201A (zh) 2013-12-18
KR101812835B1 (ko) 2017-12-27
GB201202504D0 (en) 2012-03-28
US9003089B2 (en) 2015-04-07
TW201234191A (en) 2012-08-16

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