Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
  • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
  • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier

Definitions

• TITLE An ECPR master electrode and a method for providing such ECPR master electrode
• the present invention relates to a master electrode and a method for providing such master electrode. More particularly, the present invention relates to a master electrode for use in electrochemical pattern replication processes.
• BACKGROUND ART WO 02/103085 and WO 2007058603 relate to an electrochemical pattern replication method, ECPR, and the construction of a master electrode for production of appliances involving micro and nano structures using ECPR.
• An etching or plating pattern which is defined by the master electrode, is replicated on an electrically conductive material, commonly denoted as a substrate.
• the master electrode is put in close contact with the substrate and the etching/plating pattern is directly transferred onto the substrate by an etching/plating process.
• the contact etching/plating process is performed in local etching/plating cells, which are formed in cavities between the master electrode and the substrate.
• the cavities are provided as electrochemical cells on the upper surface of the master electrode.
• the upper surface of the master electrode includes a topographical pattern defining at least one electrochemical cell, wherein the bottom of each cell is provided with an electrically conducting material.
• each cell is filled with an electrolyte solution, for allowing conducting ions to be transferred from the bottom of each cell to the substrate to be patterned.
• the area between the electrochemical cells i.e. the uppermost area of the topographical pattern of the master electrode is provided with an insulating layer for preventing unwanted parasitic currents during the ECPR process.
• ECPR will only provide pattern transfer at the positions being defined by the electrochemical cells.
• the master electrode may be made of a durable material, since the master electrode should be used for a plurality of processes of etching or plating.
• One such material is Si, which allows the master electrode to be manufactured by well established and high yield semiconductor processes.
• the master electrode has a conductive back side and a front side, i.e. the side of the master electrode facing the substrate, comprising said plurality of electrochemical cells.
• deposition of the electrically conducting material at the bottom of each electrochemical cell allows for transfer of electrically conducting material during the ECPR.
• every feature which eventually will be transferred during the ECPR must have well defined dimensions for ensuring high pattern transfer fidelity during the ECPR. After lithography and cell etching, the deposition of the conductive material at the bottom of the cells is therefore considered as a critical process step.
• An idea of the present invention is to provide an ECPR master electrode, of which the electrically conductive material at the bottom of each electrochemical cell is self aligned.
• an ECPR master electrode comprises a carrier element having an electrically conducting electrode surface on a back side and a topographical pattern with an at least partly electrically insulating top on a front side of said carrier element, said
• topographical pattern is forming at least one electrochemical cell in said carrier element, said electrochemical cell comprising a bottom and at least one side wall, said bottom having an electrically conducting surface being conductively connected to the electrically conducting electrode surface on the back side through the carrier element, wherein said at least one side wall in said carrier element is at least partly covered by an electrically insulating layer.
• At least one of said electrically insulating layer or said electrically insulating top may be a surface passivation layer, and at least one of said electrically insulating layer or said electrically insulating top may be made of silicon nitride.
• silicon nitride can be deposited with high conformality leading to smooth side walls, while also allowing the bottom electrode to be deposited by a self- aligned process.
• the thickness of said electrically insulating layer may be below 1 micron, and more preferably in the range of 100 to 300 nm. Hence, sufficient insulating properties are achieved while only affecting the dimensions of the electrochemical cells moderately.
• the roughness of said electrically insulating layer may be less than the roughness of said at least one side wall.
• Said at least one side wall may be completely covered by said electrically insulating layer, and said electrically insulating layer may extend to said at least partly insulting top, such that a continuous interface of an insulating layer is formed between said top and said side wall.
• This is advantageous in that an intact insulating layer is provided in a simple and fast process.
• the insulating layer as well as insulating top comprises silicon nitride, the master electrode will be further
• the master electrode is electrically insulating, impervious to chemical attacks as well as mechanically robust.
• a method for providing an ECPR master electrode from a conducting or semiconducting carrier element comprises the steps of providing an electrically conducting electrode surface on a back side of said carrier element, providing a topographical pattern on a front side of said carrier element, said front side having an at least partly electrically insulating top, such that said topographical pattern is forming at least one electrochemical cell in said carrier element, said at least one electrochemical cell comprising a bottom and at least one side wall, providing an electrically insulating layer at least partly covering said at least one carrier element side wall in said electrochemical cell, and providing an electrically conducting surface on said bottom, said electrically conducting surface being conductively connected to the electrically conducting electrode surface on the back side through the carrier element.
• the step of providing an electrically insulating layer at least partly covering said at least one side wall may be made by depositing silicon nitride by low pressure chemical vapor deposition.
• the step of providing an electrically conducting surface of said bottom may further include a step of removing an electrically insulating layer at said bottom.
• the step of removing the electrically insulating layer at said bottom may be performed by anisotropic reactive ion etching.
• Fig. 1 is a top view of an ECPR master electrode according to an embodiment
• Fig. 2 is a side view of a section of an ECPR master electrode according to an embodiment
• Fig. 3 is a method scheme of a manufacturing process of an ECPR master electrode according to an embodiment.
• the methods generally include: forming a master electrode that comprises a carrier element which is conducting and/or semiconducting in at least some parts; forming a conducting electrode layer which functions as anode in ECPR plating and cathode in ECPR etching on a front side of the master electrode; and forming an insulating pattern layer that defines the cavities in which ECPR etching or plating can occur in the ECPR process on said front side, such that conducting electrode surface(s) is/are obtained in the bottom of the cavities; in a way that makes possible electrical contact from an external power supply to the back side of the master electrode for allowing electron transfer through the master electrode to the front side thereof to the conducing electrode surface(s), such that said surface(s) will constitute anode(s) in ECPR plat
• a top view of a master electrode 10 is shown.
• the master electrode 10 is formed by an at least partly electrically conducting circular carrier element, such as a Si wafer.
• the size of the carrier element may vary depending on the dimensions of the ECPR equipment to be used, but is typically of the size of standard semiconducting wafers, such as 100, 150, 200, or 300 mm (4, 6, 8, 10, or 12 inches) in diameter.
• the upper surface 13 of the master electrode 10 is divided into a plurality of rectangular segments 15, each segment 15 defining a device pattern, such as a chip layer, to be transferred to a substrate during an ECPR process.
• a sectional side view of the master electrode 10 is shown.
• the carrier element 20 extends between a back side 21 and a front side 22, in such a way that electrical current is able to flow between the back side 21 and the front side 22.
• an electrode layer 23 of an electrically conducting material is arranged at the back side 21.
• the electrode layer 23 may be formed by Au, or any other material being suitable for ECPR.
• the front side 22 comprises a topographical pattern 30 with an at least partly electrically insulating top 32.
• the topographical pattern 30 is forming a plurality of electrochemical cells 34 in said carrier element 20. That is, the planar surface extending between two adjacent electrochemical cells 34 is covered by an electrically insulating layer 32.
• Each electrochemical cell in said carrier element 20 comprises a bottom 36 and at least one side wall 38 extending from the bottom 36 to the electrically insulating top 32.
• the bottom 36 in said electrochemical cells 34, in said carrier element 20, has an electrically conducting surface 40.
• the electrically conducting surface 40 is
• the electrically conducting surface 40 is conductively connected to the electrically conducting electrode surface 23 on the back side 21.
• the electrically conducting surface 40 is conductively connected to the electrically conducting electrode surface 23 on the back side 21 by means of the carrier element 20.
• the conductive surface 40 is formed by any material being suitable as an anode/cathode in the ECPR.
• the side walls 38 in the carrier element 20 of the master electrode 10 are covered by an electrically insulating layer 42, such that the conductive surface 40 may be formed by a self-aligned process.
• the conductive surface 40 is formed by a self-aligned silicidation process.
• the electrically insulating layer 42 is preferably a surface passivation layer, formed by deposition of silicon nitride, silicon oxide or both silicon nitride and oxide, and the thickness of said electrically insulating layer 42 is preferably below 1 micron, and even more preferably in the range between 100 and 300 nm. As is shown in Fig. 2, the electrically insulating layer 42 extends from the bottom 36 of each electrochemical cell 34 to the insulating top 32. That is, a continuous interface of an electrically insulating layer is formed between the top 32 of the master electrode 10 and the side walls 38.
• a method 100 for manufacturing an ECPR master electrode will be discussed. However, only details on the manufacturing of the front side of the master electrode, i.e. the side of the master electrode carrying the
• a carrier element such as a Si wafer, is provided with a layer of silicon nitride, silicon oxide or stack of silicon nitride and oxide on the top.
• the carrier element is thereafter transferred to a lithography station including resist spinning, mask alignment, exposure, and development. These steps, or any other lithography sequence, are performed as a lithography step 104.
• the resist mask is used for an etch process, which step transfers the lithography pattern to the silicon nitride and/or oxide layer(s).
• the resist layer on top of the silicon nitride and/or oxide layer(s) is stripped during step 108.
• the carrier element is thereafter subject to an etching step 110, in which a deep etch is performed for creating trenches in the carrier element.
• etching step 110 the silicon nitride and/or oxide layer(s) on the front side of the carrier element is used as an etch mask.
• the semi-finished master electrode is thereafter subject to a step 112, in which a layer of silicon nitride is formed on the inner surface of each trench.
• This step is preferably made by a chemical vapor deposition process, such as Low Pressure
• LPCVD Chemical Vapor Deposition
• the carrier element is arranged within an etching chamber, for removing the silicon nitride at the bottom of each trench. Since this etching process is anisotropic, e.g. made by a reactive ion etch, the silicon nitride on the walls will remain intact. Consequently, after this step the raw material of the carrier element will be exposed only at the bottom of each trench.
• the electrode layer is formed at the bottom of each trench. This step may be made as a self-aligned process, in which a bottom layer of silicide is formed, on top of which further conductive materials are grown.
• the master electrode is provided with a topographical pattern in which the trenches are forming electrochemical cells during ECPR.
• silicon nitride as a side wall cover is advantageous in that it allows for a self-aligned process of providing the electrode layer at the bottom of each electrochemical cell. Further, silicon nitride has proven high mechanical strength, excellent chemical and diffusion barrier properties, high conformal deposition, and good compatibility with state of the art CMOS processes.
• silicon nitride, silicon oxynitride, and silicon carbide materials may however also be envisaged. Such materials could be described as Si x N y , Si x ON y (oxynitrides), Si x C y , Si x OC y (silicon carbides), Si x OCN y (carbon doped oxynitrides), where x and y are continuous variables and are a function of the film deposition conditions and source gases.

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• Manufacturing & Machinery (AREA)
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• Microelectronics & Electronic Packaging (AREA)
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• 2010
  • 2010-12-23 WO PCT/EP2010/070646 patent/WO2012084047A1/en active Application Filing
  • 2010-12-23 EP EP10795731.8A patent/EP2655700A1/de not_active Withdrawn

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