EP2599222A1

EP2599222A1 - Circuit arrangement and method for limiting the current level and/or flank gradient of electrical signals

Info

Publication number: EP2599222A1
Application number: EP11724182.8A
Authority: EP
Inventors: Ingo Koehler
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2010-07-29
Filing date: 2011-06-03
Publication date: 2013-06-05
Also published as: CN103004091A; WO2012013402A1; US8975931B2; US20130187695A1; DE102010038623A1

Abstract

A circuit arrangement (100) for limiting the current level and/or flank gradient of electrical signals, having a voltage source (116) and a switching element (102), connected to the voltage source (116) and designed for switching the voltage source (116), wherein the switching arrangement (100) furthermore has a limiting unit (120), wherein the limiting unit (120) is functionally arranged between the switching element (102) and the voltage source (116) and wherein the limiting unit (120) is designed to limit a current level and/or flank gradient of an electrical signal, using the switching element (102), during a switching process of the voltage source (116).

Description

Circuit arrangement and method for limiting the current intensity and / or edge steepness of electrical signals

State of the art

The present invention is based on a circuit arrangement or a method for limiting the current intensity and / or edge steepness of electrical signals as generically defined by the independent claims.

Electrical switching elements, such as driver blocks, usually have a fixed, unchangeable edge steepness, which may not be optimally adapted to a desired application to this. For example, it may not always be possible to influence an internal drive current of the respective standard element when using standard components or modules or components. Even a predetermined short-circuit current limit, insofar as a switching element used has such a, may not always be optimally adapted to a specific, desired application.

Excessively high edge steepness of a switching operation or clocked signals may exceed, for example, E MV emission limits (electromagnetic compatibility), thus violating them.

Furthermore, too high a set or even missing current limit in the case of a fault, for example in a short circuit condition, may cause an overload of a component or an assembly, thereby potentially damaging or even destroying it.

Disclosure of the invention

Accordingly, a circuit arrangement is provided for limiting the current intensity and / or edge steepness of electrical signals, comprising a voltage source and a switching element which is connected to the voltage source and which is set up for switching the voltage source, characterized in that the switching arrangement furthermore has a limiting unit, wherein the limiting unit is arranged functionally between the switching element and the voltage source, and wherein the limiting unit is adapted to limit a current intensity and / or a flank of an electrical signal in a switching operation of the voltage source using the switching element.

The circuit arrangement with the features of the independent claims may on the one hand provide a current limit and on the other hand a flank boundary. The circuit arrangement may in particular be realized with a few standard components, and thus may be inexpensive and low

Space requirement, for example, be realized on a printed circuit board. Known driver circuits may be extended, in particular without major system interventions, by a circuit arrangement for limiting current intensity and / or edge steepness in accordance with the present invention. This may be realized in particular in that internal drive signals of a driver circuit need not be influenced.

The limitation of short-circuit current and edge steepness for a desired application may be easily parameterizable to the desired application by selecting suitable component values of the circuit arrangement. A ready-developed standard layout of an electronic circuit may be adaptable to a particular application by simply repackaging the respective component values to the desired requirements. Thus, a desired short-circuit current or a required edge steepness and thus an EMC limit value can be selected simply and flexibly by selecting the

Component values can be set.

Such a flexibility, for example in the case of an EMC optimization to be carried out, allows an occurring edge steepness to be adapted very quickly and in a simple manner to a required edge steepness. In particular, it may not be necessary to extensively reshape an already existing or developed switching assembly in order to comply with a changed EMC emission limit for a new application. Thus, a lengthy or costly and risky revision of a switching module may be omitted. However, the circuit arrangement may also be used as a driver stage itself, so that it can be controlled, for example, to save space or cost effectively directly via a logic signal. In particular, the circuit arrangement may provide a targeted influencing of a steep falling signal edge at low-side outputs, without grinding a rising signal edge. Furthermore, the circuit arrangement according to the present invention may provide a small voltage drop in the switched-on state of the switching element at this.

The circuit arrangement of the present invention may generally be used in conjunction with a switching element, for example realized as an open-collector output, an open-drain output or a relay. In particular, it may provide current strength and / or slew rate limitation for both slowly varying and clocked signals.

The measures listed in the dependent claims advantageous refinements and improvements of the independent claim device are possible.

It may be particularly advantageous to limit the current intensity and / or the edge steepness of the output voltage of the voltage source. Due to the possibly large amplitudes associated therewith, a limiting unit acting on the voltage source may be particularly suitable for complying with required E MV limit values.

Between limiting element and voltage source may further be arranged a capacitive element and / or a diode element, which is arranged parallel to switching element, limiting element and voltage source.

By such an element, a slope may be further improved adjustable, at the same time it may serve as a protective circuit or a protective element for the limiting element. Embodiments of the invention are illustrated in the drawings and explained in more detail in the following description. Show it:

1 shows a first exemplary embodiment of a circuit arrangement for limiting the current intensity and / or edge steepness of electrical signals according to the present invention;

Figure 2 shows another exemplary embodiment of a circuit arrangement for limiting the current intensity and / or edge steepness of electrical signals according to the present invention;

FIG. 3 shows an exemplary embodiment of a circuit arrangement for limiting an edge steepness of an electrical signal according to the present invention;

FIG. 4 shows an exemplary signal curve of the circuit arrangement according to FIG. 1; and

FIG. 5 shows an exemplary embodiment of a method for limiting the current intensity and / or edge steepness of electrical signals according to the present invention.

Embodiments of the invention

FIG. 1 shows a first exemplary embodiment of a circuit arrangement for limiting the current intensity and / or edge steepness of electrical signals according to the present invention.

The circuit arrangement 100 consists here by way of example of an npn transistor 118 whose base is connected to a fixed potential 108. The connection may for example be made via the resistor 106 or via a voltage divider. The emitter of the element 118 is connected to the switching element 102 via a resistive component 104. The switching element 102 is the element in conjunction with the resistive element 114 and voltage source 116, which is to be extended by the current and / or edge slope limitation using the limiting unit 120.

Optionally, a capacitive element 110a, b may be provided at the base of the limiting element 118 of the limiting unit 120 of the circuit arrangement 100. The capacitive element 110a may herebetween base and Lector of the transistor element 118, the capacitive element 110b be connected between the base and emitter. The collector terminal of the transistor element 118 may represent the output of the circuit arrangement, in FIG. 1 an example being connected to the voltage source 116 via a resistive element 114.

Furthermore, capacitive elements 112a, b may be present at the circuit output. Capacitive element 112b may be formed, for example, as a capacitor, capacitive element 112a, for example, as an ESD diode. In the event that an ESD diode is provided, this, depending on the configuration of the circuit arrangement 100, may be set up at the same time to protect the base emitter diode of the transistor element 118, for example in the case of an npn transistor 118 from a breakthrough in a reverse polarity case.

The electrical resistance of the element 114 may advantageously be significantly greater than that of the electrical resistance of the element 104. This results in switched-on switching element 102, only a low voltage at the circuit output. A ratio of 10: 1 or greater than 10: 1 is preferred. Thus, a voltage dropping at the output when the switching element is switched on, without consideration of a small voltage drop across the elements 118 and 102, results in less than 10% of the value of the voltage source 116.

As a switching element 102, for example, a transistor element, a relay element, a switching contact may be used.

The operation of the edge slope limitation of the circuit arrangement according to Figure 1 is as follows: Without the limiting unit 120, which ultimately includes each element except switching element 102, resistive element 114 and voltage source 116, depending on their respective configuration and thus provided optionally optional elements, may Turning on the switching element 102 result in a steep falling voltage edge at the output of the circuit 100, since this relatively low-impedance, directly via switching element 102, is pulled to low potential. The flank which arises when the switching element 102 is switched off passes through the electrical resistance of the resistance element 114 in FIG Connection with the available capacity at the output significantly flatter. The output capacitance may be present either as a capacitive component or only as a parasitic capacitance. The aim of limiting the steepness of the slope may therefore be in particular to flatten the falling edge of the output signal, in particular without, however, excessively grinding the rising edge so that in particular signal integrity may be maintained. The switching on of the switching element 102 causes a lowering of the emitter potential of the limiting element 118, so that the limiting element 118 also turns on. Parasitic capacitances and possibly existing capacitive components 112a, b now discharge via limiting element 118, resistance element 104 and switching element 102. This results in a voltage drop across resistance element 104 and switching element 102. This

Voltage drop in turn leads to a reduction of the available base-emitter voltage of the limiting element 118, thus to a current negative feedback. This results in a constriction of limiting element 118, thus limiting the discharge current. The falling edge at the output runs flatter due to this limitation.

When the switching element 102 is switched off, parasitic capacitances and optionally available capacitive components 112a, b are charged comparatively slowly via the resistance element 114. However, such a charging current does not limit the limiting unit 120, so that the already flat rising edge at the output is not additionally ground.

When using an optional capacitive component 110a, b, the falling edge may additionally be ground if necessary.

In particular, element 110a may represent an artificial magnification of a miller capacitance of the limiting element 118, causing it to switch more slowly. When the switching element 102 is switched on, the limiting element 118 also begins to conduct, as a result of which the potential at the collector begins to drop. By a capacitive coupling of the collector to the base, by capacitive element 110a, this in turn counteracts the control of element 118, so that the activation of limiting element 118 is delayed. velvet. The switch-on process is only completed after capacitive element 110a has been completely transferred.

Although the additional capacity may also be reloaded when the switching element 102 is switched off. Nevertheless, the rising edge at the output may still be only slightly influenced since relatively small capacitance values for the capacitive element 110a may already be sufficient in practice.

The preferred, but not exclusive, values or ranges of values of the individual elements can be assumed as follows:

Voltage source 116: IV to 50V;

Element 112b: 10pF to 100nF;

Element 112a: Zener voltage <60V;

Element 118, 102: to select according to the required limiting current, typically 0.1 mA to 100 mA, with power outputs also> 1A;

Element 104: is preferably selected such that at limiting current sufficient for the negative feedback voltage drop is applied (for example in the range 0.5V to 3V).

Element 114: factor 10> as element 104 so that when switching element 102, a meaningful voltage difference occurs at the output;

Element 108: minimum value approx. 2x base-emitter voltage of element 118, in the case of a bipolar transistor thus at least approx. 1.2 V. Maximum value significantly smaller than element 116, so that there is a limitation of the falling edge or of the current in the event of a short circuit. For example, the voltage of element 108 is smaller in the range of 1: 5 to 1:20 than the voltage of element 116;

Element 106 is used to limit the base current of element 118. Typically, the base current is selected from about 10x to 200x <the limiting current of the circuit. The factor (10 to 200) depends on the current gain of the selected transistor;

Elements 110a, 110b: lOpF to 22 nF. If a wiping of the rising edge is to be avoided, a value in the lower region will tend to be used for element 110a, ie generally a smaller value than for element 112b.

The optional capacitive element 110b may also be used to slow the turn-on operation of the limiter 118. Once switching element 102 turns on, thus in a conductive state, the basis of the Element 118 capacitive pulled to ground, so that element 118 blocks first. Only by reloading element 110b via resistance element 106 does limiting element 118 begin to conduct. The operation of a current limit of the circuit according to

Figure 1 is as follows. With element 102 energized, the current in the output line results in a voltage drop across resistive element 104. In normal operation, however, this voltage drop is so small that the base-emitter voltage on restrictor 118 is sufficient, element 118 itself, for example Use of a transistor to aufzusteuern, but advantageously not necessarily in the saturation. If the output line is now connected to positive potential with low resistance, for example in the event of a short circuit, then the current in the output line increases only until the voltage drop across the resistive element 104 and switching element 102 is so great that the base-emitter voltage of the limiting element 118 does not more is sufficient to control the transistor fully. The voltage drop across the collector emitter path of the limiting element 118 thus increases, the current in the output line is limited. In this case, a sufficient power dissipation, thus cooling of the limiting element 118 may be necessary.

The output voltage of the voltage source 116 may in particular be assumed to be the voltage of the series connection of the voltage source 116 and of the resistor element 114.

With continued reference to FIG. 2, another exemplary embodiment of a circuit arrangement for limiting the current intensity and / or edge steepness of electrical signals according to the present invention is shown.

As an alternative to a series connection of limiting unit and switching element 102, as shown in FIG. 1, a parallel connection of limiting element 118 and switching element 102 may also be realized. The switching element 102 controls the limiting element 118 at its base, the output signal is thereby inverted. Optionally, the current gain of the limiting element 118 may be used, so that for switching element 102, a switching element with low power is used. In this case, for example, a direct control of limiting element 118 from an open-drain output of a microcontroller may be possible. This may be a separate amplifier stage can be saved.

The mode of operation of the circuit arrangement according to FIG. 2 is analogous to the circuit arrangement according to FIG. 1.

If a MOSFET is used as the switching element 102, then its parasitic body diode may protect the base emitter diode of the limiting element 118 from a breakdown in reverse polarity of the circuit. In this case, however, the body diode must have a sufficiently high current carrying capacity.

Still referring to FIG. 3, an exemplary embodiment of a circuit arrangement for limiting a slew rate of an electrical signal in accordance with the present invention is illustrated.

The circuit arrangement according to FIG. 3 may be understood in particular as a pure edge limitation. When switching element 102 is switched off, capacitive element 302 is charged to the potential of voltage source 116 via resistance element 106, limiting element 118 and resistance element 114. When switching element 102 now turns on, limiting element 118 is initially blocked. Now, capacitive element 302 discharges via resistance element 300 and switching element 102, so that the base potential of limiting element 118 slowly drops. This begins to conduct, and the output voltage level follows the progression of the base voltage of limiting element 118. Once switching element 102 turns off again, capacitive element 302 is charged via resistance element 106, limiting element 118 and resistance element 114, whereby the output potential rises again to the value of voltage source 116. If there is an element 112a, b, the capacitance of capacitive element 302 may be chosen to be small relative to the capacitance of element 112a, b, which will only slightly affect the rising edge of the circuit.

At the moment of activation of element 102, the behavior of a controlled edge may in particular be realized at the circuit output. For the circuit arrangements of Figures 1 and 2 may continue to be implemented a variable current limit. For this purpose, the limiting element 118 should be connected to a variable potential on the base side. The amount of this potential may be able to adjust the current limit.

The bipolar transistor for limiting element 118 illustrated by way of example may, in all circuit arrangements of FIGS. 1 to 3, alternatively also be embodied by other transistor types, for example MOSFET or JFET, as an operational amplifier or tube element. The connections should then be selected according to the component used.

In the event that a self-conducting n-channel FET for limiting element 118 is selected in the circuit arrangements of FIGS. 1 to 2, its gate connection may, for example, also be at ground potential, so that no auxiliary voltage may be required.

If the switching element 102 is missing in the circuit arrangement according to FIG. 2 or is replaced by a short circuit in the circuit arrangement according to variant 1, the result is a pure current limiter circuit arrangement in the respective circuit arrangements.

Deviating from the implementations shown in the figures, which are also to be understood schematically, all circuit arrangements can be used completely or partly also in integrated form.

FIG. 4 shows an exemplary signal course of the circuit arrangement according to FIG. 1.

At the time animal follows in the circuit arrangement according to Figure 1, a switching off of the switching element 102. This increases the output voltage

V (collector) to the exemplary value of 16V. At time t ₂ takes a Einschaltevorgang of the switching element 102. In the case that only one switching element 102 and the elements 114 and 116 are provided, a circuit is performed with a slope of the edge 400, in essence, by way of example, directly. In the case of the arrangement of the limiting unit 120, the falling edge 402 is limited in its steepness, whereby this falls more slowly and only at time t3 to its lower value, which is determined substantially by the ratio of the electrical resistances of the resistive elements 114 and 104.

The method 500 for limiting current magnitude and / or slew rate of electrical signals includes the steps of performing 502 a switching operation of the voltage source using the switching element and limiting 504 a current magnitude and / or a slew rate of an electrical signal, in particular the output voltage, using a limiting unit.

Claims

claims

Circuit arrangement (100) for limiting the current intensity and / or edge steepness of electrical signals, comprising a switching element (102) which can be connected to a voltage source (1 16) and which is set up for switching the voltage source (1 16);

characterized in that the circuit arrangement (100) further comprises a limiting unit (120); wherein the limiting unit (120) is operatively disposed between the switching element (102) and the voltage source (1 16); and wherein the limiting unit (120) is arranged to limit a current intensity and / or a slope of an electrical signal during a switching operation of the voltage source (1 16) using the switching element (102).

Circuit arrangement according to the preceding claim, further comprising a voltage source (1 16); wherein the electrical signal is formed as an output voltage of the voltage source (1 16); and wherein the switching of the voltage source (1 16) comprises the switching on and off of the voltage source.

Circuit arrangement according to one of the preceding claims, wherein the limiting unit (120) has a limiting element (1 18), which is arranged in series between the voltage source (1 16) and switching element (102).

Circuit arrangement according to one of claims 1 or 2, wherein the limiting unit (120) has a limiting element (1 18) which is arranged parallel to the voltage source (1 16) and switching element (102).

Circuit arrangement according to one of claims 3 and 4, wherein the limiting unit (120) further comprises at least a first capacitive element (1 12a, b) selected from the group consisting of capacitor, diode and ESD diode; and wherein the first capacitive element (1 12a, b) is arranged parallel to the voltage source (1 16). Circuitry according to one of claims 3 to 5, wherein the limiting element (1 18) is an element is selected from the group consisting of transistor element, transistor, bipolar transistor, field effect transistor, MOSFET, JFET, operational amplifier and tube element; and / or wherein the switching element (102) is an element selected from the group consisting of transistor element, transistor, bipolar transistor, field effect transistor, MOSFET, JFET, operational amplifier, tube element; Relay element and switching contact.

Circuit arrangement according to one of the preceding claims, wherein the edge slope limit is formed as a current negative feedback in the limiting unit (120) or as a controlled edge; and / or wherein the current limiting is designed as current negative feedback in the limiting unit (120).

Circuit arrangement according to one of claims 3 to 7, wherein the limiting unit (120) further comprises at least one second capacitive element (1 10a, b); and wherein the at least one second capacitive element (1 10a, b) between the base and collector and / or between the base and emitter or the corresponding terminals of the limiting element (1 18) is arranged.

9. Circuit arrangement according to one of claims 3 to 8; wherein on the base or the corresponding terminal of the limiting element (1 18) further comprises a first resistance element (106) is arranged; wherein a voltage source (108) is further disposed on the resistive element (106); and wherein at the collector or the corresponding terminal of the limiting element (1 18) further comprises a second resistance element (104) is arranged.

10. A method for limiting the current intensity and / or edge steepness of electrical signals, wherein a limiting unit is arranged functionally between a switching element and a voltage source, which limiting unit is set, in a switching operation of the voltage source using the switching element, a current strength and / or a slope of an electrical Limiting signals, comprising conducting a switching operation of the power source using the switching element; and limiting a current intensity and / or a slope of an electrical signal, in particular the output voltage of the voltage source, using a limiting unit; wherein the edge steepness limit is formed using a current negative feedback or a controlled edge, and / or wherein the current limit is formed as a current negative feedback.