DE102010032717A1 - Method for operating of power semiconductor component e.g. insulated gate bipolar transistor (IGBT) , involves limiting gate-emitter voltage of power semiconductor component to critical voltage during starting phase of component - Google Patents

Abstract

The control voltage e.g. gate-emitter voltage of power semiconductor component (12) is limited to a critical voltage during a starting phase of the power semiconductor component. The gate-emitter during starting phase of component is smaller than in steady-state operation of the component. Independent claims are included for the following: (1) electric circuit; and (2) electrical power converter.

Description

The invention relates to a method and an electrical circuit for operating a power semiconductor device.

From the DE 102 44 266 A1 For example, it is known to arrange, in the vicinity of a power semiconductor component, a Rogowski coil, with which the current change in the power semiconductor component can be monitored. If an overcurrent or a short-circuit current is detected in the power semiconductor device, the same is turned off. The cost of implementing the known procedure is relatively high, in particular due to the required Rogowski coil.

This results in the object of the invention to provide a method and an electrical circuit that allows monitoring of over- or short-circuit currents with less effort.

The invention achieves this object by a method according to claim 1 and by an electrical circuit according to claim 2.

In the case of the invention, it is provided that the control voltage or the gate-emitter voltage of the power semiconductor component is limited to a critical voltage during a switch-on phase of the power semiconductor component.

During the power up phase, the power semiconductor device is in a non-saturated, non-steady state, pass-through state. In this state, there is a direct relationship between the collector current and the gate-emitter voltage of the power semiconductor device. In particular, the larger the gate-emitter voltage in the switch-on phase, the more the collector current increases. If, therefore, the invention limits the gate-emitter voltage to a critical upper voltage, this has the consequence that the rise of the collector current is also limited. By means of this limitation of the collector current according to the invention, an overcurrent or a short-circuit current, which may be critical for the power semiconductor component, can thus not arise at all. Such an overcurrent or short-circuit current is instead limited in its formation in the manner explained.

The invention thus has the significant advantage that it does not wait as in the prior art, until an overcurrent or a short-circuit current is generated, to then detect this overcurrent or short-circuit current, and then turn off the power semiconductor device and before a To preserve destruction. Instead, the emergence of an overcurrent or a short-circuit current is thereby not allowed at all that the collector current is limited in the manner according to the invention.

Thus, on the one hand, a substantially greater protection of the power semiconductor component against overcurrent or short-circuit currents is achieved with the invention, since these are limited from the outset. On the other hand, the implementation of the invention requires little effort compared to the prior art, since a monitoring of overcurrents, for example by means of a Rogowski coil is not required.

In a particularly advantageous development of the invention, during the switch-on phase of the power semiconductor component, the gate-emitter voltage is compared with a reference gate-emitter voltage, and the power semiconductor component is switched off when the gate-emitter voltage is the same size or greater than the reference gate-emitter voltage. By this measure, in addition to the inventive limitation of the collector current, it is achieved that the power semiconductor component is switched off when the gate-emitter voltage reaches the predetermined reference gate-emitter voltage. This reference gate-emitter voltage can be specified in such a way that the achievement of this reference value is equivalent to an existing overcurrent or short-circuit current.

Alternatively or additionally, it is possible that, for example, the current flowing in the voltage limiting circuit is evaluated for the purpose of detecting an overcurrent or a short-circuit current.

Overall, it is thus achieved that, on the one hand, an overcurrent or short-circuit current, as explained, is limited according to the invention, and, on the other hand, this overcurrent or short-circuit current can still be detected and the power semiconductor component can then be switched off.

It is particularly advantageous if the power semiconductor device is switched off via an existing turn-off resistor. This ensures that in connection with the invention, no special effort is required to turn off the power semiconductor device in an overcurrent or a short-circuit current. Instead, in this case, those components that are already present for the "normal" shutdown of the power semiconductor device can be used.

In a further particularly advantageous embodiment of the invention, the gate-emitter Voltage during the switch-on phase temporarily a substantially constant plateau voltage, which is smaller than that voltage which has the gate-emitter voltage in the stationary state of the power semiconductor device, and it is the critical voltage only slightly larger than the plateau Voltage and smaller than the stationary state voltage of the power semiconductor device.

On the one hand, these specifications for the critical voltage ensure that the power semiconductor component can be operated "normally", provided that there is no overcurrent or short-circuit current, that is to say in particular without additional effort with regard to the control of the power semiconductor component. On the other hand, it is achieved by the stated specifications that a possible overcurrent or short-circuit current is detected and thus the power semiconductor component can be switched off.

In a first advantageous refinement of the invention, the limitation of the gate-emitter voltage of the power semiconductor component during the switch-on phase is achieved with the aid of a zener diode connected to the gate of the power semiconductor component. This provides a simple and reliable way to limit the gate-emitter voltage and thus also the collector current during the switch-on phase.

In a second advantageous embodiment of the invention, the limitation of the gate-emitter voltage of the power semiconductor device is achieved in that the gate of the power semiconductor device is driven during the switch-on with a voltage which is smaller than the voltage of the stationary state of the power semiconductor component. This special control ensures that the gate-emitter voltage can not rise to higher values. As has been explained, this has the consequence that the collector current is also limited. The advantage of this embodiment is that only a very small effort is required for their realization.

The circuit according to the invention can be used particularly advantageously in an electric power converter which has a plurality of power semiconductor components.

Other features, applications and advantages of the invention will become apparent from the following description of embodiments of the invention, which are illustrated in the figures of the drawing. All described or illustrated features, alone or in any combination form the subject matter of the invention, regardless of their summary in the claims or their dependency and regardless of their formulation or representation in the description or in the drawing.

1 shows a schematic block diagram of an embodiment of an inventive electrical circuit for driving a power semiconductor device, 2 shows a schematic timing diagram of waveforms of signals of the circuit of 1 . 3 shows a schematic electrical circuit diagram of a first embodiment of a drive of the power semiconductor device of 1 . 4 shows a schematic timing diagram of waveforms of signals of the circuit of 3 at a short-circuit, and 5 shows a schematic electrical circuit diagram of a second embodiment of a control of the power semiconductor device of 1 ,

In the 1 is a circuit 10 shown, which is a series circuit of two power semiconductor devices 12 . 13 each with a diode connected in parallel in parallel 14 . 15 having. For the two power semiconductor components 12 . 13 they may be any kind of voltage-controlled, turn-off components, in particular IGBTs (IGBT = insulated gate bipolar transistor). The following are the two power semiconductor devices 12 . 13 for the sake of brevity only as IGBTs 12 . 13 designated. However, this is not meant to limit the present embodiment to IGBTs only.

The two IGBTs 12 . 13 are each with a drive 17 . 18 connected, namely, on the one hand, the respective gate of the two IGBTs 12 . 13 from the associated control 17 . 18 with a current i _{G are} applied and on the other hand, the respective emitter of the two IGBTs 12 . 13 with the associated control 17 . 18 connected, so that the respective gate-emitter voltage u _GE of the associated control 17 . 18 can be determined.

At the gate and the emitter of the two IGBTs 12 . 13 these are the control terminals of the same and the gate-emitter voltage u _GE are their control voltages. For the sake of brevity, in the following, the control terminals and the control voltage will always only be the gate, emitter and gate-emitter voltage u _{GE of} the IGBTs 12 . 13 designated. However, this is not meant to limit the present embodiment to IGBTs only.

The two controls 17 . 18 in each case an ON / OFF signal is supplied, on whose Basis of the associated IGBT 12 . 13 is switched to the conductive or locked state. In the conducting state flows over the respective IGTB 12 . 13 the collector current i _C and there is the voltage u _CE .

To the series connection of the two IGBTs 12 . 13 is a series circuit of an inductance 20 and a capacity 21 connected in parallel. At the inductance 20 it is usually a structurally rather small inductance and capacity 21 it is a usually rather large, so-called support capacity. At the capacity 21 is usually a DC voltage U _d . At the connection point of the two IGBTs 12 . 13 or the two diodes 14 . 15 a load can be connected so that a current i _L flows through this point.

In the 2 are exemplary of a switch-on of the IGBT 12 the gate-emitter voltage u _GE , the current i _G , and the collector current i _C and the voltage u _{CE applied} over the time t, wherein in the 2 it is assumed that there is no short circuit.

At time t _on becomes the gate of the IGBT 12 due to the ON / OFF signal with the current i _G acted upon. As a result, the gate-emitter voltage U _GE rises from a negative voltage U _n and, at a time t1 _, exceeds a threshold value U _{GE, th} . From this time t1, the collector current i _C starts flowing ^g s. During the following switch-on phase, the IGBT is located 12 in a non-saturated and non-stationary on-state, which can also be seen in the course of the voltage u _CE , in particular its drop to a steady state voltage u _{CE, sat} .

After time t1, the gate-emitter voltage u _GE drops to a substantially constant plateau voltage U _{GE, pl} , which is significantly smaller than the voltage U _{p +} , the gate-emitter voltage u _GE in the steady state of the IGBT 12 having. By way of example, the plateau voltage U _{GE, pl may be} about 10 V to about 12 V. Starting from the time t _on , the gate-emitter voltage u _GE remains approximately at the expiration of a time T _on at this plateau voltage U _{GE, pl} . The time duration T _on can be, for example, about 3 μsec to about 8 μsec.

After expiration of the time period T _on , the gate-emitter voltage u _GE rises to the voltage U _{p +} for the stationary state of the IGBT 12 at. The voltage U _{p +} is about 15 V to about 18 V.

As already mentioned, the IGBT is located 12 during its power up phase in a non-saturated and nonstationary on-state. In this state, the collector current i _{C is} directly dependent on the value of the gate-emitter voltage u _GE . In particular, the equation essentially applies here: i _C (t) = g _fs * (u _GE (t) _{-U GE, th} ) with U _{GE, th} ≈ constant and g _fs = f (i _C )
wherein g _{f s is} the transconductance and transconductance of the IGBT 12 represents.

This formal relationship shows that the larger the gate-emitter voltage u _GE , the larger the collector current i _C. With a corresponding limitation of the gate-emitter voltage u _GE , an increase of the collector current i _C can thus be limited.

Will be so during the switch-on of the IGBT 12 the gate-emitter voltage u _GE limited to a critical voltage U _{GE, crit} , which is only slightly larger than the usually existing plateau voltage U _{GE, pl} , so in an error case inevitably only a short-circuit collector current i _{SC, max} , which is also only slightly larger than the usually flowing collector current i _C. As a result of the aforementioned limitation to the critical voltage U _{GE, crit} , a limitation of a possible short-circuit collector current can be achieved.

In the 3 is an example of the control 17 for the IGBT 12 shown in detail. The control 17 has a driver 25 on which the ON / OFF signal is supplied in a manner not shown. There are two series-connected voltage sources 27 . 28 provided that generate the voltages U _{p +} , U _n- . The connection point of the two voltage sources 27 . 28 is at ground or 0 V. With this connection point is also the emitter of the IGBT 12 connected.

The positive voltage U _{p +} is via a first switch 31 and a first resistance 32 with the gate of the IGBT 12 connected and the negative voltage U _n- is via a second switch 33 and a second resistor 34 with the gate of the IGBT 12 connected. The two switches 31 . 33 are alternatively from the driver 25 switched to their closed or opened state. The two resistors represent the switch-on and the switch-off, which are usually present in such a control.

Between the gate and the emitter of the IGBT 12 is a series circuit of a Zener diode 37 and a zener diode switch 38 switched, wherein the forward direction of the zener diode 37 to the gate of the IGBT 12 is directed. The breakdown voltage of the Zener diode 37 lies at the critical tension U _{GE, crit} . The zener diode switch 38 is from the driver 25 in his closed or opened state. It is understood that instead of the Zener diode 37 also different types of voltage limiting devices can be used.

It is a comparator 41 provided, on the one hand, the gate-emitter voltage u _GE and on the other hand, a reference gate-emitter voltage U _{GE, ref are} supplied. The gate-emitter voltage u _GE is thereby at the gate of the IGBT 12 tapped and the reference gate-emitter voltage U _{GE, ref} is from the driver 25 specified. The reference gate-emitter voltage U _{GE, ref} is greater than the plateau voltage U _{GE, pl} , but less than / equal to the critical voltage U _{GE, crit} . Depending on the two mentioned input signals, the comparator generates 41 a short-circuit signal KS, which is the driver 25 applied.

For purposes of explanation, it is assumed that the first switch 31 opened and the second switch 33 closed is. During the switch-on phase of the IGBT 12 becomes the first switch 31 from the driver 25 closed. The second switch 33 is then open. Should the IGBT 12 be switched off again, then the first switch 31 opened and the second switch 33 is from the driver 25 closed.

During the switch-on phase of the IGBT 12 during the period T _on , the Zener diode switch becomes 38 from the driver 25 closed. Thus, the gate-emitter voltage u _GE during the period T _on to the Zener diode 37 at. This has the consequence that the gate-emitter voltage u _GE during the period T _on due to the Zener diode 37 can rise to a maximum of the critical voltage U _{GE, crit} and then in the event of an error to this critical voltage U _{GE, crit} limited or "clamped" is.

The comparator 41 is activated only during the time T _on , otherwise the comparator 41 off. During the time period T _on , the gate-emitter voltage u _GE and the reference gate-emitter voltage U _{GE, ref} are compared with each other. If the gate-emitter voltage u _{GE is} greater than the reference gate-emitter voltage U _{GE, ref} , the short-circuit signal KS is set by the comparator, for example, to "1". Otherwise, the short-circuit signal KS is equal to "0". Occurs during the switch-on of the IGBT 12 , Strictly speaking, during the period T _on no short circuit, the gate-emitter voltage u _GE remains smaller than the reference gate-emitter voltage U _{GE, ref} and the short-circuit signal KS remains equal to "0". The driver 41 takes no action in this respect. After expiration of the time T _on the Zener diode switch 38 opened and the gate-emitter voltage u _GE can without a limitation by the zener diode 37 increase to the voltage U _{p +} and the IGBT 12 to go to the stationary state.

In the 4 are exemplary for the IGBT 12 the gate-emitter voltage u _GE , the current i _G , and the collector current i _C and the voltage u _CE plotted against the time t. In the 4 a short circuit occurs at a time t _sc , for example due to a defect in the diode 14 , The diode 14 can, for example, even before switching on the IGBT 12 may have been defective or it may also be related to turning on the IGBT 12 initiated shutdown of the diode 14 be destroyed.

This short circuit with the result that the gate-emitter voltage u _GE practically at the time t _sc is at least equal to the reference gate-emitter voltage U _{GE, ref.} The short-circuit signal KS becomes "1". The driver 41 then switches the IGBT 12 Immediately after that he made the first switch 31 opens and the second switch 33 closes. This switch-off process takes about a period T _sc , so that the IGBT 12 is switched _off at the time t _off . Time is the IGBT 12 thus usually switched off before the expiration of the time T _on .

During the entire time period T _on, and thus also during the short circuit, the gate-emitter voltage u _GE through the Zener diode 37 limited to the critical tension U _{GE, crit} . This is equivalent to the fact that the collector current i _{C is} limited, namely to the already mentioned short-circuit collector current i _{SC, max} . After switching off the IGBT 12 the collector current i _C goes to zero and the gate-emitter voltage u _GE goes back to the voltage U _n- .

In the 5 is an alternative to using the 3 explained control 17 for the IGBT 12 shown. This alternative control is in the 5 with the reference number 17 ' characterized.

A plurality of components of 5 agrees with components of 3 match. These components carry in the 5 the same reference numerals as in the 3 , Such matching components are associated with the 5 not explained again, but it is based on the description of 3 directed.

In contrast to 3 is in the 5 no series connection consisting of a zener diode and a zener diode switch. Instead, the drive indicates 17 ' of the 5 a third switch 45 on that to the first switch 31 is connected in parallel, and applied to a positive voltage U _{p (tone)} , which is smaller than the voltage _{Up +} . The third switch 45 is from the driver 25 switched to its open or closed state.

During the switch-on phase of the IGBT 12 , ie during the time T _on , is used in the control 17 ' first the third switch 45 closed and the first switch 31 stays open. Thus, only the voltage U _{p (tone) is present} at the gate of the IGBT 12 at. Since the voltage U _{p (tone) is} smaller than the voltage U _{p +} , the gate-emitter voltage u _{GE is} inevitably limited to this smaller voltage. If the voltage U _{p (tone)} of 5 about as large as the critical voltage U _{GE, crit} the 3 , this means that the gate-emitter voltage u _GE at the 5 during the time period T _{on, it} can not _{substantially} rise above this critical voltage U _{GE, crit} . The gate-emitter voltage u _GE is therefore across the third switch 45 limited to the critical tension U _{GE, crit} .

After the time T _on the third switch 45 reopened and it becomes the first switch 31 from the driver 25 closed. Thus, the voltage U _{p + is} at the gate of the IGBT 12 at. As a result, the IGBT 12 into its saturated state.

If a short circuit occurs during the time T _on , then this short circuit will be from the comparator 41 as related to the 3 explained, recognized. The short-circuit signal KS becomes equal to "1" and the driver 25 turns on the IGBT 12 , as also related to the 3 was explained immediately. At the same time during the period T _on and thus during the short circuit, the gate-emitter voltage u _GE and thus also the collector current i _{C is} limited.

It is understood that the limitation of the gate-emitter voltage u _GE to the critical voltage U _{GE, crit can} also be realized in other ways. This limitation always ensures that the collector current i _C dependent on the gate-emitter voltage u _{GE is} also limited to a short-circuit collector current i _{SC, max} in the event of a short circuit. Due to this limitation of the short-circuit collector current i _{SC, max} , the IGBT can then be switched off, in spite of the existing short-circuit, via the existing switch-off resistor.

QUOTES INCLUDE IN THE DESCRIPTION

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Cited patent literature

• DE 10244266 A1 [0002]

Claims (13)

Method for operating a power semiconductor component, in particular an IGBT ( 12 . 13 ), wherein the power semiconductor component has two control terminals, in particular a gate and an emitter, characterized in that the control voltage of the power semiconductor device, in particular the gate-emitter voltage (u _GE ) during a switch-on of the power semiconductor device to a critical voltage (U _{GE, crit} ) is limited. Electrical circuit ( 10 ) for operating a power semiconductor device, in particular an IGBT ( 12 . 13 ), wherein the power semiconductor component has two control terminals, in particular a gate and an emitter, characterized in that the control voltage of the power semiconductor device, in particular the gate-emitter voltage (u _GE ) during a switch-on of the power semiconductor device to a critical voltage (U _{GE, crit} ) is limited. Method according to Claim 1 or circuit ( 10 ) according to claim 2, wherein the gate-emitter voltage (u _GE ) during the switch-on phase temporarily has a substantially constant plateau voltage (U _{GE, pl} ) which is smaller than the voltage (U _{p +} ) which causes the gate Emitter voltage (u _GE ) in the stationary state of the power semiconductor device, and wherein the critical voltage (U _{GE, crit} ) is only slightly greater than the plateau voltage (U _{GE, pl} ) and is smaller than the voltage (U _{p +} ) of the steady state of the power semiconductor device. Method or circuit ( 10 ) according to claim 3, wherein the plateau voltage (U _{GE, pl} ) is about 10 V to about 12 V, and wherein the voltage (U _{p +} ) of the stationary state of the power semiconductor device is about 15 V to about 18 V. Method or circuit ( 10 ) according to one of claims 1 to 4, wherein the limitation of the gate-emitter voltage (u _GE ) of the power semiconductor device during the switch-on using a Zener diode connected to the gate of the power semiconductor device ( 37 ) is achieved. Method or circuit ( 10 ) according to one of claims 1 to 4, wherein the limitation of the gate-emitter voltage (u _GE ) of the power semiconductor device is achieved in that the gate of the power semiconductor device during the switch-on with a voltage (U _{p (sound)} ) which is smaller than the voltage (U _{p +} ) of the stationary state of the power semiconductor device. Method according to one of claims 1 to 6, wherein during the switch-on phase of the power semiconductor device, the gate-emitter voltage (u _GE ) with a reference gate-emitter voltage (U _{GE, ref} ) is compared, and wherein the power semiconductor Device is turned off when the gate-emitter voltage (u _GE ) is equal to or greater than the reference gate-emitter voltage (U _{GE, ref} ). Circuit ( 10 ) according to one of claims 1 to 6, wherein a comparator ( 41 ) is provided which compares the gate-emitter voltage (u _GE ) with a reference gate-emitter voltage (U _{GE, ref} ) during the switch-on phase of the power semiconductor component, and wherein a driver ( 25 ) is provided, which turns off the power semiconductor device when the gate-emitter voltage (u _GE ) is equal to or greater than the reference gate-emitter voltage (U _{GE, ref} ). Method or circuit ( 10 ) according to claim 7 or 8, wherein the reference gate-emitter voltage (U _{GE, ref} ) is greater than the plateau voltage U _{GE, pl} . Method or circuit according to one of claims 7, 8 or 9, wherein the reference gate-emitter voltage (U _{GE, ref} ) is less than the critical voltage (U _{GE, crit} ) or equal to the critical voltage (U _{GE, crit} ). Method according to one of claims 7, 9 or 10 or circuit ( 10 ) according to any one of claims 8, 9 or 10, wherein the power semiconductor device is switched off, in particular in the event of a short circuit via an existing turn-off resistor. Method or circuit ( 10 ) according to one of the preceding claims, wherein the turn-on phase of the power semiconductor device substantially at a time (t _on ) begins in which the gate-emitter voltage (u _GE ) exceeds a threshold value (U _{GE, th} ), and wherein the The switch-on phase ends approximately before the gate-emitter voltage (u _GE ) becomes greater than the temporarily existing, essentially constant plateau voltage (U _{GE, pl} ). Electric power converter with a plurality of power semiconductor components, characterized in that; that a circuit ( 10 ) according to one of claims 2 to 12 is present.

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