EP2591498A1 - Verfahren zur chipmontage bei einem flexiblen substrat - Google Patents

Verfahren zur chipmontage bei einem flexiblen substrat

Info

Publication number
EP2591498A1
EP2591498A1 EP11746593.0A EP11746593A EP2591498A1 EP 2591498 A1 EP2591498 A1 EP 2591498A1 EP 11746593 A EP11746593 A EP 11746593A EP 2591498 A1 EP2591498 A1 EP 2591498A1
Authority
EP
European Patent Office
Prior art keywords
substrate
chip
zone
wire
electrically conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11746593.0A
Other languages
English (en)
French (fr)
Inventor
Jean Brun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP2591498A1 publication Critical patent/EP2591498A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
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    • H05K2201/10545—Related components mounted on both sides of the PCB
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Definitions

  • the invention relates to a method of assembling an electronic chip on a substrate.
  • WO 2005/067042 several chips formed on a rigid substrate are connected to a fabric having electrical wires.
  • the interest of the conductive flexible substrate is lost because the assembly is finally rigid because of the substrate connecting the different chips.
  • a rigid substrate is formed by a fabric bonded to a holding plate. The fabric has lead wires that are used to power light emitting diodes. Again, the benefits of the soft substrate are lost due to the rigid holding plate.
  • FIG. schematically, in top view, two chips mounted on a substrate
  • FIGS. 2 to 4 show, schematically, in section, a method of assembling a chip on a substrate
  • FIGS. 5 and 6 show, schematically, in section, a second method of assembling a chip on a substrate
  • FIG. 7 schematically represents, in section, a step of an alternative embodiment of an assembly method
  • FIGS. 8 and 9 show schematically, in section, the steps of another variant embodiment of an assembly method
  • FIGS. 10 and 11 show schematically, in section, steps
  • FIG. 12 shows schematically, in top view, another embodiment of two chips mounted on a substrate.
  • the substrate 1 on which the chip 2 must be assembled is a flexible substrate which comprises at least one electrically conductive wire 3.
  • the wire 3 is totally or partially embedded in an electrically insulating material.
  • the electrically conductive wire 3 is not encapsulated by an electrically insulating material.
  • the substrate 1 comprises a plurality of electrically conductive wires 3
  • the electrically conductive wires 3 may be contained in a single plane inside the substrate, but it is also conceivable to have wires 3 distributed in several parallel shots.
  • the substrate 1 comprises two series of wires which represent two parallel planes inside the substrate 1.
  • the substrate 1 also comprises a plurality of electrically nonconductive wires.
  • the son used are woven or not. Electrically conductive wires can all be oriented in the same direction. It is also conceivable that the conductive son are distributed in several directions and organized for example matrix.
  • the substrate 1 is a fabric having threads 3 woven between them within which there is at least one electrically conductive wire.
  • the substrate 1 comprises a support film which is covered by a conductive wire 3.
  • the substrate 1 is still a film of electrically insulating material inside which one or more son 3 are embedded. The mechanical maintenance between the wires (conductors or not) can be achieved by the support film or by means of the different mechanical connections that exist between the different wires.
  • the electrically conductive wire 3 may be sheathed in the electrically insulating material, the whole retaining the shape of a wire, or it may be in a layer of insulating material.
  • the conductive wire 3 When the conductive wire 3 is encapsulated by an insulating material and retains the shape of a wire, the conductive wire which is electrically insulated from the other wires may be used in a woven structure as a weft or warp wire.
  • the electrically conductive wire is, for example, covered by an electrical insulator. It is also conceivable to incorporate an electrically conductive wire covered with an insulating layer inside a substrate itself electrically insulating. When the electrically conductive wire is integrated without insulation, the insulation is obtained by the structure of the substrate.
  • a reception zone 5 is then formed on the substrate so as to receive the chip 2.
  • the reception zone 5 for the chip 2 represents a more rigid zone of the substrate 1. This increased rigidity makes it possible to place more easily the chip in its home area and thus avoid excessive deformation of the substrate and the conductive wire relative to the chip. In this way, it is easier to align the chip with the substrate. This is particularly effective when the chip is embedded on a flexible substrate.
  • the stiffening of a portion of the substrate to form the reception zone can be obtained by different techniques, for example by means of a polymerizable material 4 which will react to stiffen the reception area. It is also possible to use an external reinforcement which stiffens the substrate by preventing too much deformation during the placement of the chip. It is also conceivable to modify the mechanical behavior of the reception area temporarily or permanently by means of an optical, magnetic and / or electrical stimulus.
  • the flexible substrate has a rigid zone which is adjacent to a flexible zone or surrounded by a flexible zone. Both zones have different mechanical properties. This difference in behavior may be due, for example, to a difference in Young's modulus between the material forming the rigid reception zone and the material of the adjacent flexible substrate.
  • the Young's modulus of the reception zone is higher than the Young's modulus of the remainder of the flexible substrate.
  • the rigid zone makes it possible to facilitate the precise positioning of the chip with respect to the electrically conductive wire and the flexible zone makes it possible to preserve the advantages of the original substrate.
  • the reception zone 5 is associated with a deformation of the substrate. This deformation makes it easier to place the chip in relation to its environment, for example with respect to one or more wires 3. If the substrate 1 is deformed in order to form the reception zone 5 for the electronic chip 2, this reception zone 5 may be in depression or protrude from the rest of the substrate 1. According to the embodiments, the zone of FIG. home 5 in depression or projecting corresponds to the surface of the chip 2, or represents a larger area than the chip 2 which can facilitate its positioning or allow the assembly of two chips side by side. The reception area may also correspond to a smaller area than the chip, if the reception area is projecting.
  • the deformation of the substrate 1 can be obtained by any suitable technique. As illustrated in FIG. 2, the deformation can be obtained by means of a stamping of the substrate between two half-matrices 6.
  • the opposite faces of the substrate 1 may have protruding or depressed areas with any shapes.
  • the formation of a reception zone 5 projecting or depression is performed in a conventional manner according to conventional mastering techniques.
  • the substrate 1 has a depression zone, two depression zones facing each side of the substrate or a depression zone facing a projecting zone. In the example illustrated in Figure 3, two depressed areas face each other.
  • the substrate 1 is a flexible substrate, it hardly retains a predefined shape of the reception zone 5. It is then advantageous to use a substrate comprising a polymerizable material 4 or any other material that can locally stiffen the substrate.
  • the polymerizable material may be an intrinsic constituent of the substrate or it may be added to the substrate, for example by impregnation or by depositing a polymerizable material on the substrate. Impregnation or deposit can be generalized or only localized to the future welcome area of the chip. During the polymerization of the polymerizable material, the latter sees its mechanical properties evolve so as to make it more rigid. The transformation of the polymerizable material makes it possible to stiffen the substrate. The same is true of other materials that can be used.
  • the substrate 1 can be modified locally in its chemical composition and in its mechanical strength. Otherwise, the polymerizable material 4 may form a rigid layer on the surface of the flexible substrate 1 so as to avoid posterior deformation.
  • the polymerizable material 4 is treated so as to make it react.
  • the substrate 1 is then stiffened at least at the receiving zone 5 of the chip 2.
  • the polymerization of the polymerizable material 4 may be obtained by any suitable technique, for example, by means of a heat treatment or by means of an illumination under electromagnetic or electronic radiation.
  • the stiffening of the reception zone 5 is preferably carried out as soon as possible after its deformation in order to avoid a change of shape.
  • the transformation of the polymerizable material 4 is carried out, at least partially, during pressing, stamping, in order to maintain an impression as close as possible to that desired in the substrate 1.
  • the chip 2 is disposed on the reception area 5.
  • the main face of the chip 2 is brought into contact with the substrate and they are made integral.
  • This solidarity of the chip 2 with the substrate 1 is carried out by any suitable technique, for example by gluing, by embedding the chip in its reception area or by a mechanical holding between the chip and a cooperation member disposed on the opposite face of the substrate.
  • FIGS. 5 and 6 it is also possible to compress the substrate 1 directly by means of the chip 2.
  • the main surface of the chip 2 is brought into contact with the main surface of the substrate 1 and a pressure is applied.
  • the substrate 1 then deforms to conform to the shape of the chip 2.
  • a counter plate 7 is used to better control the deformation of the reception zone 5. This deformation can be final or temporary.
  • the applied pressure is advantageous for ensuring an effective mechanical contact between the substrate 1 and the chip 2.
  • the substrate 1 is at least locally stiffened by a polymerizable material 4 or the like, so as to maintain the shape of the receiving zone 5 once the pressing step is complete.
  • the stiffening of the reception area is related to the use of a counterplate 7. It is then not necessary to use a polymerizable material.
  • the counterplate 7 is associated with the substrate which has the effect of defining a more rigid zone, the reception zone 5.
  • the chip is then placed on the substrate at the level of the reception zone 5.
  • the chip 2 and the back plate 7 are separated by the substrate 1.
  • the chip 2 is electrically connected to the substrate 1.
  • An electrical connection zone 8 disposed on the main face of the chip 2 is in electrical contact with an electrically conductive wire 3 of the substrate 1.
  • the electrical connection zone 8 of the chip 2 is, for example, an area projecting from the main face of the chip 2 or, conversely, a zone in depression relative to to that same face.
  • the zone 8 of electrical connection can be made by micro-inserts, by balls of fuse metal material (bumps in English) or by stud-bumps, that is to say beads of particular shape.
  • the electrical connection can also be made by a conductive adhesive, preferably an anisotropic conductive adhesive.
  • the conductive wire 3 of the substrate 1 allows the supply and / or the communication of the chip 2 with another element electrically connected to the substrate 1, a chip or a passive element.
  • the pressure exerted by the chip on the substrate makes it possible to ensure the electrical contact between an electrically conductive wire 3 and the electrical connection zone 8.
  • the projecting connection areas make it possible to pierce the insulating material encapsulating the conductive electrical wire and thus to strip it at least partially.
  • the electrical connection zones which project from the main face of the chip have a pointed shape and / or a diameter of less than or equal to 30 microns which facilitates the penetration of the protruding zone 8 to the wire 3 driver.
  • an additional step of chemical, ionic or mechanical etching is performed in order to form the contact zones without exposing the wire 3.
  • a vacuum connection zone that is to say inside the chip may also connect an electrically conductive wire 3 taking advantage of the deformation of the conductive wire generated by the plate against-7.
  • an electrical connection zone 8 and an electrically conductive wire 3 it is necessary to locate the reception zone 5 as a function of the electrically conductive wires and the electrical connection areas of the chip.
  • access to the electrically conductive wire may be achieved by means of an additional step which consists of etching and / or ion etching and / or mechanical etching. insulating material located next to the future electrical connection area.
  • the access to the conductive wire 3 is made by passing through the substrate and stopping at the level of the plate 7. It is also possible not to use a backplate 7 or to also etch the plate against 7 to obtain an opening contact.
  • the conductive wire is eliminated together with the rest of the substrate 1 and the connection zone 8 fills the empty zone created.
  • the electrical contact is then obtained by means of the lateral face of the electric wire and the connection zone ensures the continuity of the signal in the rest of the electric wire.
  • the conductive wire 3 is not completely or completely removed with the substrate 1.
  • the insulating layer encapsulating the conductive wire is mainly eliminated.
  • the chip 2 may include one or more additional electrical connection zones 8 (FIG. 1).
  • the pitch between two zones 8 of active electrical connection is free and function of the existing pitch between the son.
  • the substrate 1 comprises several electrically conductive wires 3, the distance between two parallel conductor wires 3 or substantially parallel must be compatible with the distance between two zones 8 of electrical connection.
  • the wire 3 conductor can be cut between two chips or between two connection areas of the same chip to avoid short circuit ( Figure 1).
  • the yarn is cut by any suitable technique, for example by means of a punch or laser radiation.
  • the backplate 7 serves only for the step of deforming the substrate and, in this case, it is not present in the final device. In other embodiments, it can also serve as a mechanical reinforcement to the chip 2 and / or the substrate 1, the counter-plate 7 is then secured to the electronic chip. The counterplate 7 and the chip 2 are on either side of the substrate 1.
  • the counter plate 7 is formed by an additional electronic chip 2 which is mechanically connected to the substrate 1 and the first chip 2.
  • the two chips 2 are electrically connected to each other.
  • This electrical connection can be made directly by zones 8 of electrical connection having complementary shapes that face each other. There is no, in this case, passage through the wire 3 for the connection between the two chips.
  • This electrical connection can also be achieved by passing through one or more electrically conductive wires 3.
  • the electrical connections between the two chips 2 are then advantageously located in the surface opposite the two chips 2.
  • the mechanical connection between the electronic chip 2 and the backplate 7 can be achieved by any suitable means, for example by means of an adhesive or structures fitting forcibly.
  • the receiving area 5 of the chip 2 is made by means of the counterplate 7, pressing the counter - plate on the substrate.
  • the substrate is deformed and the counterplate defines a projecting zone on the face opposite to that comprising the counterplate (FIG. 8).
  • the backplate has one or more protruding patterns.
  • the shape of the projecting reception area is arbitrary. It may have the same design as that of the counterplate.
  • protruding patterns of the counter-plate 7 pass through the substrate 1 or print on the reception zone 5 relief patterns which act as polarizers imposing the position and orientation of the chip 2 to be assembled subsequently ( Figure 9).
  • the alignment of the chip 2 with respect to the counterplate 7 can be achieved with a reception zone projecting from the substrate 1 (FIG. 9) or in the volume of the substrate ( Figure 10).
  • the counter-plate can also be used to form a reception zone associated with two adjacent chips.
  • the counterplate 7 may advantageously be used to align the two chips 2 with respect to each other and with respect to the wires 3.
  • the plate against 7 can be removed by any suitable technique.
  • the counter-plate 7 can also be preserved.
  • the polarizer can also form an electrical connection zone.
  • the pressing of the backplate causes the deformation of the substrate either to form a projecting reception area or for the passage of one or more polarizers through the substrate.
  • the chip 2 is preferable to align the chip 2 with respect to the wire 3 conductor. This alignment can be achieved during the definition of the reception area 5 or while placing the chip 2 in the reception area 5.
  • two chips 2 each having a plurality of connection zones 8 are integrated on the substrate 1.
  • zones of electrical connections of these two chips are connected to the same conductor wire.
  • the conducting wire 3 and the electrical connection contact 8 are not shown in the sectional view. They can be represented in a similar way to previous views, but it is also possible that the connection takes place in another plane not shown. In this second case, the deformations present in the reception zone 5 serve as a key.
  • the electrically conductive son 3 are organized in matrices, that is to say that there are at least two sets of son oriented differently, preferably in perpendicular directions.
  • One or more chips have a plurality of electrical connection areas 8. Some connections 8 are electrically associated with wires oriented in a first direction while other connections of the same chip are electrically associated with wires oriented in a second direction.
  • the electrically conductive wires 3 that face the chip 2 can be connected or left free.
  • the same wire 3 can be connected to several connection areas 8 of the chip 2. If different signals must pass in different areas of the same wire, the wire is cut to avoid the creation of spurious signals. For example, the electrical wire is cut at the chip between two consecutive connection zones 8 if the signal entering the chip by a first zone 8 is reinjected after treatment with a second 8 on the same wire 3 in the direction another chip.
  • the substrate comprises a plurality of electrically conductive wires arranged in two parallel planes.
  • the arrangement of the wires in each plane is arbitrary.
  • Each series of son can be oriented in one direction, these two directions being parallel or not. It is also conceivable to have a matrix organization of the son 3 of each plane.
  • an electrical connection zone 8 chip 2 performs the simultaneous connection of two son 3 present on two different planes at a superposition area.
  • the chip comprises means for making an interconnection between two superposed wires.
  • the realization of an interconnection can be achieved by means of a pressure exerted on two superimposed wires in order to force their electrical connection.
  • the interconnection can also be obtained by means of an electrical contact which comes from the chip and which directly touches the two electrically conductive wires 3.
  • This interconnection between two wires 3 may or may not be electrically connected to the chip 2.
  • the method is particularly advantageous in the case of the use of a tissue-type substrate because the latter is particularly sensitive to deformation when placing the wire. chip.
  • the stiffening of the reception area makes it possible to reduce the deformations and thus to control the alignment of the chip with respect to the conducting wire.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)
EP11746593.0A 2010-07-06 2011-07-05 Verfahren zur chipmontage bei einem flexiblen substrat Withdrawn EP2591498A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1002846A FR2962593B1 (fr) 2010-07-06 2010-07-06 Procede d'assemblage d'une puce dans un substrat souple.
PCT/FR2011/000395 WO2012007655A1 (fr) 2010-07-06 2011-07-05 Procédé d'assemblage d'une puce dans un substrat souple

Publications (1)

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EP2591498A1 true EP2591498A1 (de) 2013-05-15

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EP11746593.0A Withdrawn EP2591498A1 (de) 2010-07-06 2011-07-05 Verfahren zur chipmontage bei einem flexiblen substrat

Country Status (6)

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US (1) US9179586B2 (de)
EP (1) EP2591498A1 (de)
JP (1) JP5951602B2 (de)
CN (1) CN102971841A (de)
FR (1) FR2962593B1 (de)
WO (1) WO2012007655A1 (de)

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FR2986372B1 (fr) * 2012-01-31 2014-02-28 Commissariat Energie Atomique Procede d'assemblage d'un element a puce micro-electronique sur un element filaire, installation permettant de realiser l'assemblage
GB2500380A (en) 2012-03-18 2013-09-25 Effect Photonics B V Arrangement and method of making electrical connections
EP2957154B1 (de) * 2013-02-15 2018-11-07 IMEC vzw Integration von elektronischen schaltungen in textilien
US9801277B1 (en) * 2013-08-27 2017-10-24 Flextronics Ap, Llc Bellows interconnect
CN107113960A (zh) 2014-12-08 2017-08-29 株式会社藤仓 伸缩性基板
JP2018514071A (ja) * 2015-01-27 2018-05-31 ネーデルランドセ・オルガニサティ・フォール・トゥーヘパスト−ナトゥールウェテンスハッペライク・オンデルズーク・テーエヌオー 繊維層アセンブリ用の可撓性デバイスモジュールおよび作製方法
CN105047676A (zh) 2015-09-06 2015-11-11 京东方科技集团股份有限公司 一种封装用柔性基板及封装体
EP3483929B1 (de) * 2017-11-08 2022-04-20 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Bauelementträger mit elektrisch leitenden und isolierenden schichten und einem darin eingebetteten bauelement sowie herstellungsverfahren dafür
US11022580B1 (en) 2019-01-31 2021-06-01 Flex Ltd. Low impedance structure for PCB based electrodes
EP3735111A1 (de) 2019-05-03 2020-11-04 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Komponententräger mit verformter schicht zur aufnahme von komponenten
US11668686B1 (en) 2019-06-17 2023-06-06 Flex Ltd. Batteryless architecture for color detection in smart labels
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Also Published As

Publication number Publication date
FR2962593A1 (fr) 2012-01-13
US9179586B2 (en) 2015-11-03
US20130074331A1 (en) 2013-03-28
FR2962593B1 (fr) 2014-03-28
JP5951602B2 (ja) 2016-07-13
JP2013531897A (ja) 2013-08-08
CN102971841A (zh) 2013-03-13
WO2012007655A1 (fr) 2012-01-19

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