EP2568500A1 - Dispositif de protection ESD avec tension de fixation réduite - Google Patents

Dispositif de protection ESD avec tension de fixation réduite Download PDF

Info

Publication number
EP2568500A1
EP2568500A1 EP11180790A EP11180790A EP2568500A1 EP 2568500 A1 EP2568500 A1 EP 2568500A1 EP 11180790 A EP11180790 A EP 11180790A EP 11180790 A EP11180790 A EP 11180790A EP 2568500 A1 EP2568500 A1 EP 2568500A1
Authority
EP
European Patent Office
Prior art keywords
esd
bipolar junction
junction transistor
emitter
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11180790A
Other languages
German (de)
English (en)
Inventor
Ramses Pierco
Johan Bauwelinck
Xin Yin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universiteit Gent
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Universiteit Gent
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universiteit Gent, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Universiteit Gent
Priority to EP11180790A priority Critical patent/EP2568500A1/fr
Priority to JP2012197513A priority patent/JP2013062502A/ja
Priority to EP20120183709 priority patent/EP2568501B1/fr
Priority to US13/607,959 priority patent/US8873210B2/en
Publication of EP2568500A1 publication Critical patent/EP2568500A1/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • the invention relates to an ESD protection circuit, in particular to an on-chip ESD protection circuit for integrated electronic circuits.
  • the circuit may be used as ESD diode or as ESD power clamp.
  • ESD electrostatic discharge
  • this series connection of diodes can also be implemented by means of bipolar transistors, which also leads to a low leakage current.
  • the clamping voltage over the diode chain is increased to N times the built-in junction voltage Vbe(on) of a base-emitter junction.
  • this clamping voltage N x Vbe(on) is too high because of the low collector-emitter breakdown voltage of the bipolar transistors and the possibly low oxide breakdown voltage of the gate dielectric of the MOSFETS in the circuitry to be protected by this diode-chain.
  • the aforementioned aim is achieved with the ESD protection circuit having the technical characteristics of the first claim.
  • the ESD protection circuit of the invention comprises a plurality of bipolar junction transistors, namely a plurality of ESD current conducting transistors in a main ESD current conducting path between a first and a second terminal, and further comprises at least one driving transistor parallel to at least one of the ESD current conducting transistors and provided for conducting a driving current to one or more of the ESD current conducting transistors on occurrence of an ESD event.
  • the driving transistor(s) supply a driving current to the base(s) ESD current conducting transistor(s) which are connected thereto. This triggers these ESD current conducting transistors, so that the ESD current I ESD can flow through their collector-emitter junction.
  • ESD current conducting transistors is implied that these transistors are adapted to be able to sustain ESD currents. In particular, these transistors are adapted to conduct ESD currents while in saturation, so that their on-resistance is low.
  • the base current for the bipolar junction transistor(s) in the main ESD current path i.e. those which are connected to the at least one driving transistor
  • the base-emitter voltage of each driving transistor is much smaller than the base-emitter voltage of an ESD current conducting transistor which conducts the full ESD current I ESD . Since the driving transistor(s) are in parallel over one or more of the ESD current conducting transistor(s), the total voltage over the terminals can be significantly reduced.
  • the capacitance of the circuit according to the invention may also be lower as compared to a conventional diode-string, even for a circuit with the same total circuit area as the diode-string, while the ESD stress level (e.g. TLP failure current level) of the circuit of the invention is substantially the same as for the diode-string.
  • the ESD stress level e.g. TLP failure current level
  • the leakage current for which the substrate leakage current is a dominant part of the total leakage current will be lower. Also the leakage current in function of the voltage shows a steeper curve. This results in a device with a lower leakage current at the same absolute voltage below the clamping voltage.
  • the plurality of ESD current conducting transistors comprises a first bipolar junction transistor having its base and collector connected to the first terminal and a second bipolar junction transistor having its collector connected to the emitter of the first bipolar junction transistor; and the group of driving transistors comprises a third bipolar junction transistor having its base and collector connected to the first terminal and its emitter connected to the base of the second bipolar junction transistor.
  • the plurality of ESD current conducting transistors further comprises a fourth bipolar junction transistor having its collector connected to the emitter of the second bipolar junction transistor; and the group of driving transistors further comprises a fifth and a sixth bipolar junction transistor, the fifth bipolar junction transistor having its base and collector connected to the first terminal and having its emitter connected to the base of the sixth bipolar junction transistor, the collector of the sixth bipolar junction transistor being connected to the emitter of the third bipolar junction transistor and the emitter of the sixth bipolar junction transistor being connected to the base of the fourth bipolar junction transistor.
  • the ESD current conducting transistors are sized for conducting the ESD current I ESD
  • the driving transistor(s) is/are sized for conducting only the driving current, i.e. the driving transistor(s) can be much smaller than the ESD current conducting transistors, e.g. half the area or smaller.
  • the driving transistor(s) in the circuit of the present invention only need to deliver the base current for the ESD current conducting transistor(s), and do not need to be able to sustain the full ESD current I ESD as they are parallel over part of the main ESD current conducting path. Reducing the size also reduces the capacity of the driving transistor, but slightly increases the base to emitter voltage together with a drop in the sustainable current and subsequent ESD-level. The skilled person can thus find a suitable trade-off between a lower clamp voltage and a higher ESD-protection level versus a lower capacitance.
  • the circuit comprises a top row connected to the first terminal, in which row the bipolar junction transistors - an ESD current conducting transistor or driving transistor - are configured as diodes for limiting leakage currents.
  • the ESD protection circuit of the invention can be used as one of the ESD double diodes between an input/output terminal and a source voltage terminal of the electronic circuit it needs to protect.
  • an ESD-device with a low capacitance together with a low clamping voltage and high ESD-robustness are preferred, which is achievable by means of the ESD protection circuit of the invention.
  • the ESD protection circuit of the invention can also be used as ESD power clamp between the source voltage terminals (VDD, VSS) of the electronic circuit it needs to protect. For this use, a low leakage current together with a high sustainable ESD-level are preferred, which is achievable with the ESD protection circuit of the invention.
  • the first ESD current conducting transistor i.e. the one in the top row of which the base and collector are connected to the same terminal and which is configured as a diode
  • the invention also encompasses an ESD protection circuit having in its main ESD current conducting path this diode followed by one or more of the ESD current conducting bipolar junction transistors, and at least one driving bipolar junction transistor in parallel for supplying a driving current to the base of one or more of the ESD current conducting bipolar junction transistors.
  • top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments of the invention described herein can operate in other orientations than described or illustrated herein.
  • ESD protection circuits according to embodiments of the invention, in particular to an on-chip ESD protection circuit for integrated RF devices implemented in SiGe BiCMOS technology of 250 nm and beyond, because in this technology the collector-emitter breakdown voltage is relatively low.
  • the ESD protection circuit may also be used in other technologies which comprise bipolar transistors.
  • Fig 1 shows a schematical ESD-protection configuration for protecting in-or outputs, and/or ground and supply rails of an electronic device. It has "ESD diodes”, shows as diodes in reverse mode (i.e. non-conducting mode) as ESD protection between the I/O terminals IO1, IO2 and the source voltage terminals VDD, VSS. It further has an “ESD power clamp” between the source voltage terminals VDD and VSS.
  • ESD diodes shows as diodes in reverse mode (i.e. non-conducting mode) as ESD protection between the I/O terminals IO1, IO2 and the source voltage terminals VDD, VSS. It further has an “ESD power clamp” between the source voltage terminals VDD and VSS.
  • a reverse biased diode-string with a number of (e.g. two or three or four or more) diodes connected in series is used.
  • diodes instead of diodes also bipolar junction transistors (BJT) configured as diodes by connecting their collector and emitter, as shown in Fig 2 , may be used.
  • BJT bipolar junction transistors
  • the clamping voltage of the circuit can be increased in steps of Vbe(on).
  • the value for Vbe(on) depends on the technology, and may e.g. be a value in the range of 0.85 - 0.90V in 130 nm BiCMOS technology.
  • this diode-string has a certain capacitance, which should be as low as possible for high frequency circuits. Lowering the capacitance can be achieved by increasing the number of N, but has the disadvantage that the clamp voltage also increases linearly with the number N.
  • Fig 3 shows a first preferred embodiment of an ESD circuit according to the present invention, consisting of three transistors, as an alternative for the conventional diode-string with two diodes ( Fig 2 ).
  • the ESD protection circuit consists of a first, second and third bipolar junction transistor q1, q2, q3, whereby the first and second transistor q1, q2 are connected in series between the first and second terminal T1, T2 for forming the main ESD current path, whereby the collector of the first transistor q1 is connected to the first terminal T1, the emitter of the first transistor q1 is connected to the collector of the second transistor q2, and the emitter of the second transistor q2 is connected to the second terminal T2; the transistors in the top row, in this case the first and third transistor q1, q3 are connected with their collector and their base to the first terminal T1 and functioning as diodes which limit the substrate leakage current of the ESD protection circuit; the emitter of the third transistor q3 is connected to the base of the second transistor q
  • the base current for the switch (second transistor) q2 is provided by the third transistor q3 in a diode configuration, and located in parallel to the main ESD path formed by q1 and q2. Because this base current is typically an order of magnitude smaller than the ESD current I ESD (by the well known factor ⁇ F ), the base-emitter voltage Vbe3 of the third transistor q3 is lowered, and thus the total clamping voltage between the terminals T1, T2 is also lowered as compared to a conventional diode string with two diodes ( Fig 2 ).
  • the transistors in the main ESD current path q1, q2 are stacked, i.e. the emitter of one transistor q1 is connected to the collector of the next transistor q2. This leads to a low parasitic capacitance, which is beneficial for high-frequency circuits. In this way an ESD circuit is created with the advantage of the diode string (low capacitance) but with a lower clamping voltage.
  • the ESD protection circuit of embodiments of the present invention can consist solely of transistors, without the need for any resistor or capacitor (apart from the parasitic resistors or capacitors). This can lead to a smaller layout area in comparison to ESD-devices using resistors and capacitors (with typically high values).
  • Fig 5 shows a graph comparing the clamping voltage for the classical diode-string and for the circuit of the present invention. Both simulations and measurements are plotted and show good agreement. From the graph it can be seen that the clamping voltage of the "2-stage" circuit of Fig 3 is about 1.50V whereas the clamping voltage of the 2-stage diode-string of Fig 2 is about 1.70V. This effect becomes even more pronounced for a circuit according to the present invention with 3 or 4 stages, which will be described further.
  • Fig 4 shows a preferred embodiment of the circuit of the present invention corresponding to the "3-stage" diode-string.
  • the circuit of Fig 4 comprises six bipolar junction transistors.
  • the transistors in the top row namely the first, third and fifth transistor q1, q3, q5 are configured as diodes for limiting substrate leakage-current.
  • the first, second and fourth transistors q1, q2, q4 are stacked to form the main ESD current path, whereby the second and fourth transistor q2, q4 function as two switches in series. These switches are controlled either directly or indirectly by the "diodes" q3, q5 that are not part of the main ESD current path.
  • the switch formed by the second transistor q2 is (directly) controlled by the third transistor q3 configured as diode via the first drive connection dr1
  • the switch formed by the fourth transistor q4 is (indirectly) controlled by the fifth transistor q5 configured as diode via a second drive connection dr2a.
  • the current to be delivered by the fifth transistor q5 is further decreased by the sixth transistor q6, which turns on/off the fourth transistor q4 via a third drive connection dr2b.
  • Fig 8 and Fig 9 show the relative areas of the diodes and the transistors that were used for this comparison, but these relative areas are only an example, and the person skilled in the art may use other relative sizes.
  • the size of the first transistor q1 is also smaller than the size of the second transistor q2, despite that the same ESD current I ESD will run through both. This has no negative effect on the behaviour of the circuit, because during the initial ESD current peak, a significant part of the current is conducted through the transistor q3 and the base-emitter junction of q2.
  • Fig 10 and Fig 11 I showing the capacitance equivalent of the circuits of Fig 2 and Fig 3 respectively.
  • the capacitances to the substrate are not considered.
  • the capacitor C CB (q2) is typically very small w.r.t. C BE (q1)
  • the total capacitance of the circuit in Fig 11 can be approximated by the series configuration of capacitor C BE (q3) and C BE (q2).
  • transistor q3 can be made a lot smaller (e.g. 2.0 or 3.0 times smaller) than q2 (it has to conduct a much smaller current), its capacitance is lower and the series combination has a lower capacitance than that of the conventional diode string.
  • Fig 12 shows a comparison between the simulated capacitance of a conventional diode-string versus preferred embodiments of the circuit of the present invention using the relative areas indicated in Figures 8-11 for the 2-stage and 3-stage circuits respectively. From this graph it can be seen that the capacitance of the 2-stage diode-string ( Fig 6 ) is about 41 fF, as compared to 32 fF for the circuit of an embodiment of the present invention ( Fig 7 ). The resulting (simulated) capacitance of the "3-stage" diode-string ( Fig 8 ) is about 30 fF, which is reduced to about 22 fF for the "3-stage" circuit of an embodiment of the present invention ( Fig 9 ). Lowering the capacitance allows to increase the frequency and/or bandwith, which can be of prime importance in RF applications.
  • Fig 5 and Fig 12 shows that the circuits of the present inventions can enable to decrease the capacitance and the clamping voltage at the same time.
  • stages need to be added, but the clamping voltage increases in a linear way.
  • the capacitance is lowered, but the clamping voltage increases sub-linearly. This is very advantageous.
  • the number of "stages" of preferred embodiments ( Fig 3, Fig 4 , Fig 16 ) of the circuit of the present invention can be seen as the number of parallel transistors (horizontally), or as the number of stacked transistors (vertically). But the invention is not limited to these preferred embodiments. Several variations are possible.
  • Fig 13 shows an embodiment of the circuit of the present invention, having four transistors, herein referred to as "first variant". Structurally it can be seen as a variant of the first preferred embodiment with three transistors ( Fig 3 ) where a fourth transistor q4 is added, or it can also be seen as a variant of the second preferred embodiment with six transistors ( Fig 4 ) wherein the fifth and sixth transistor q5, q6 are removed.
  • the operation of this circuit is very similar to that of Fig 3 , but instead of one switch in the main ESD current path, there are two switches q2, q4 connected in series. Both switches need to be closed in order to allow ESD current I ESD to flow between the terminals T1, T2.
  • the third transistor q3 is configured to control both switches q2, q4.
  • Fig 15 shows a graph comparing the clamping voltage and capacitance of the "first variant" circuit ( Fig 13 ) with the first preferred embodiment of the circuit of the present invention ( Fig 3 ), assuming the relative transistor-sizes of Fig 9 , but with a different circuit area.
  • the clamping voltage is increased because of the extra collector-emitter saturation voltage, and the capacitance is also increased.
  • Fig 14 shows another embodiment of the circuit of the present invention, having five transistors, herein referred to as "second variant".
  • the fifth transistor q5 is configured as a diode, for limiting leakage current, and its emitter is connected to the base of the fourth transistor q4 for providing the base current for closing the switch q4 during an ESD event.
  • Fig 16 shows a third preferred embodiment of the circuit of the present invention, having four stages. It comprises ten transistors q1-q10.
  • This circuit is proposed as an alternative for a conventional diode-string with four diodes, i.e. has four stages.
  • the graph of Fig 5 shows that the clamping voltage of this circuit is approximately 0.9V smaller than that of the four-stage diode-string, and Fig 12 shows that the capacity is approximately 25% smaller than that of the four-stage diode-string, for a circuit with the same area.
  • Fig 17 shows the measured non-substrate leakage current for a 2-stage and 4-stage version of a conventional diode string and preferred embodiments of the circuit of this invention.
  • the area of the individual diodes in the 2-stage and 4-stage diode string are assumed the same.
  • the total area of the circuit of the embodiments of the present invention is the same as that of the corresponding diode-string, but the circuit with 4 stages is twice as large as the circuit with 2 stages.
  • the circuit of the present invention can also be used as a power clamp.
  • One of the main requirements for a power clamp is a low leakage current together with the possibility to sustain a high ESD level in a small silicon area. Since the bipolar transistors are used in their forward active area (no breakdown of a junction is occurring) this last requirement is fulfilled.
  • the leakage current of the device can be divided in substrate and non-substrate leakage current. The substrate leakage is determined by the transistors connected to the anode. Since these have their base connected to the collector, the base-emitter voltage of the parasitic pnp transistor to substrate is zero.
  • the circuit of the present invention has the same low substrate leakage current as a regular diode string in a BiCMOS process.
  • the non-substrate leakage current is plotted in Fig 17 versus voltage applied. This shows that before the device turns on, the leakage current is significantly lower for the circuit of the present invention as compared to the diode-string. For the 4-stage version this is almost one order of magnitude smaller. For these reasons (low substrate current and low inherent leakage current) the proposed ESD protection circuit also makes a good power clamp.
  • Table 1 shows the results for both transmission line pulse (TLP) and human body model (HBM) testing. Table 1 shows that similar ESD-levels are obtained for the conventional diode string and for the circuits of the present invention.
  • Table 1 2-stage diode string 2-stage this invention 4-stage diode string 4-stage this invention TLP failure current level 677mA 667mA 1.34A 1.38A HBM failure voltage level 1.9kV 1.7kV 5.1kV 4.5kV
  • the bipolar transistor circuits described above can thus be used as an ESD protection device for protecting input nodes against ESD events, or can be used as a power clamp.
  • the ESD circuit is inserted between the power supply line VDD and ground GND.
  • the number of stages will in this case be chosen high enough to get a clamping voltage sufficiently higher than the supply voltage.
  • the size is to be chosen according to the required ESD protection level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
EP11180790A 2011-09-09 2011-09-09 Dispositif de protection ESD avec tension de fixation réduite Withdrawn EP2568500A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP11180790A EP2568500A1 (fr) 2011-09-09 2011-09-09 Dispositif de protection ESD avec tension de fixation réduite
JP2012197513A JP2013062502A (ja) 2011-09-09 2012-09-07 低減したクランプ電圧を有するｅｓｄ保護デバイス
EP20120183709 EP2568501B1 (fr) 2011-09-09 2012-09-10 Dispositif de protection ESD avec tension de limitation réduite
US13/607,959 US8873210B2 (en) 2011-09-09 2012-09-10 ESD protection device with reduced clamping voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP11180790A EP2568500A1 (fr) 2011-09-09 2011-09-09 Dispositif de protection ESD avec tension de fixation réduite

Publications (1)

Publication Number Publication Date
EP2568500A1 true EP2568500A1 (fr) 2013-03-13

Family

ID=46785319

Family Applications (2)

Application Number Title Priority Date Filing Date
EP11180790A Withdrawn EP2568500A1 (fr) 2011-09-09 2011-09-09 Dispositif de protection ESD avec tension de fixation réduite
EP20120183709 Active EP2568501B1 (fr) 2011-09-09 2012-09-10 Dispositif de protection ESD avec tension de limitation réduite

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP20120183709 Active EP2568501B1 (fr) 2011-09-09 2012-09-10 Dispositif de protection ESD avec tension de limitation réduite

Country Status (3)

Country Link
US (1) US8873210B2 (fr)
EP (2) EP2568500A1 (fr)
JP (1) JP2013062502A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5970604B2 (ja) 2013-03-25 2016-08-17 ジヤトコ株式会社 自動変速機の制御装置及び制御方法
US10476263B2 (en) * 2015-12-31 2019-11-12 Novatek Microelectronics Corp. Device and operation method for electrostatic discharge protection
US11579645B2 (en) * 2019-06-21 2023-02-14 Wolfspeed, Inc. Device design for short-circuitry protection circuitry within transistors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774318A (en) * 1996-11-27 1998-06-30 Raytheon Company I.C. power supply terminal protection clamp
US6600356B1 (en) * 1999-04-30 2003-07-29 Analog Devices, Inc. ESD protection circuit with controlled breakdown voltage
WO2003063203A2 (fr) * 2002-01-18 2003-07-31 The Regents Of The University Of California Circuit de protection des incorpore pour circuits rf a transistor bipolaire a heterojonction a composes semiconducteurs
US20040057172A1 (en) * 2002-09-25 2004-03-25 Maoyou Sun Circuit for protection against electrostatic discharge
US20070075373A1 (en) * 2005-09-30 2007-04-05 International Business Machines Corporation Radiation tolerant electrostatic discharge protection networks

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11284130A (ja) * 1998-03-27 1999-10-15 Mitsumi Electric Co Ltd 保護回路
US20050083618A1 (en) * 2003-10-21 2005-04-21 Steinhoff Robert M. ESD protection for integrated circuits
JP2006005266A (ja) * 2004-06-21 2006-01-05 Toshiba Corp Ｅｓｄ保護回路
JP5396124B2 (ja) * 2009-03-30 2014-01-22 新日本無線株式会社 半導体静電保護装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774318A (en) * 1996-11-27 1998-06-30 Raytheon Company I.C. power supply terminal protection clamp
US6600356B1 (en) * 1999-04-30 2003-07-29 Analog Devices, Inc. ESD protection circuit with controlled breakdown voltage
WO2003063203A2 (fr) * 2002-01-18 2003-07-31 The Regents Of The University Of California Circuit de protection des incorpore pour circuits rf a transistor bipolaire a heterojonction a composes semiconducteurs
US20040057172A1 (en) * 2002-09-25 2004-03-25 Maoyou Sun Circuit for protection against electrostatic discharge
US20070075373A1 (en) * 2005-09-30 2007-04-05 International Business Machines Corporation Radiation tolerant electrostatic discharge protection networks

Also Published As

Publication number Publication date
EP2568501A1 (fr) 2013-03-13
US20130063846A1 (en) 2013-03-14
JP2013062502A (ja) 2013-04-04
EP2568501B1 (fr) 2014-07-02
US8873210B2 (en) 2014-10-28

Similar Documents

Publication Publication Date Title
US7283342B1 (en) High-voltage tolerant power rail electrostatic discharge clamp circuit
US9634483B2 (en) Electrostatic discharge (ESD) protection circuit with EOS and latch-up immunity
US7589945B2 (en) Distributed electrostatic discharge protection circuit with varying clamp size
US5991134A (en) Switchable ESD protective shunting circuit for semiconductor devices
US10026712B2 (en) ESD protection circuit with stacked ESD cells having parallel active shunt
US7291888B2 (en) ESD protection circuit using a transistor chain
US6690066B1 (en) Minimization and linearization of ESD parasitic capacitance in integrated circuits
US20060044714A1 (en) Substrate-triggered esd circuit by using triple-well
US8305719B2 (en) Electrostatic discharge protection device for high voltage operation
EP3116026B1 (fr) Redresseur commandé au silicium
US9451669B2 (en) CMOS adjustable over voltage ESD and surge protection for LED application
Quittard et al. ESD protection for high-voltage CMOS technologies
US9379098B2 (en) Electrostatic discharge protection circuit including a distributed diode string
JP2006080160A (ja) 静電保護回路
EP2568501B1 (fr) Dispositif de protection ESD avec tension de limitation réduite
Peng et al. Low-capacitance SCR for on-chip ESD protection with high CDM tolerance in 7nm bulk FinFET technology
US10381826B2 (en) Integrated circuit electrostatic discharge protection
US6894881B1 (en) ESD protection methods and devices using additional terminal in the diode structures
US7405914B2 (en) Electrostatic discharge protection circuit
US20150076556A1 (en) Integrated circuit device and a method for providing esd protection
EP3751608A1 (fr) Pinces de blocage à relance pour la protection contre les décharges électrostatiques comportant un schéma de déclenchement centralisé et limité en tension
KR100783641B1 (ko) 트리거 전압을 낮춘 실리콘 제어 정류기
US9142953B2 (en) Electrostatic discharge protection apparatus and associated method
Won et al. The novel SCR-based ESD protection device with high holding voltage
Dai et al. ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20130914