EP2557472B1 - Signalgenerator und Verfahren zur Signalerzeugung - Google Patents

Signalgenerator und Verfahren zur Signalerzeugung Download PDF

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Publication number
EP2557472B1
EP2557472B1 EP11177486.5A EP11177486A EP2557472B1 EP 2557472 B1 EP2557472 B1 EP 2557472B1 EP 11177486 A EP11177486 A EP 11177486A EP 2557472 B1 EP2557472 B1 EP 2557472B1
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EP
European Patent Office
Prior art keywords
signal
source
transistor
buffer
terminal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP11177486.5A
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English (en)
French (fr)
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EP2557472A1 (de
Inventor
Weixun Yan
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Ams Osram AG
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Ams AG
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Priority to EP11177486.5A priority Critical patent/EP2557472B1/de
Priority to PCT/EP2012/065627 priority patent/WO2013023998A1/en
Publication of EP2557472A1 publication Critical patent/EP2557472A1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Claims (10)

  1. Signalgenerator, Folgendes umfassend:
    - eine Signalquelle (11), die dazu ausgelegt ist, ein Source-Signal (SO) zu generieren, bei dem es sich um ein zur Absoluttemperatur proportionales (PTAT) Signal handelt;
    - einen Puffer (12, 56), der dazu ausgelegt ist, ein internes Signal (SI), bei dem es sich um ein zur Absoluttemperatur komplementäres (CTAT) Signal handelt, und ein Referenzsignal (SREF, SBG) zu generieren, indem das interne Signal(SI) und das Source-Signal (SO) oder ein vom Source-Signal (SO) abgeleitetes Signal (SO') aufsummiert werden; und
    - einen Stromspiegel (18), der die Signalquelle (11) mittels eines ersten und eines zweiten Stromspiegeltransistors (29, 30) auf einen Versorgungsspannungsanschluss (19) aufschaltet, und der den Puffer (12) mittels eines dritten Stromspiegeltransistors (31) auf den Versorgungsspannungsanschluss (19) aufschaltet;
    wobei die Signalquelle (11) umfasst:
    - einen ersten Source-Transistor (20) mit einem ersten Anschluss, der auf den ersten Spiegeltransistor (29) und auf einen Steueranschluss des Stromspiegels (18) aufgeschaltet ist, und mit einem zweiten Anschluss, der mittels eines ersten Widerstands (21) auf einen Bezugspotentialanschluss (23) aufgeschaltet ist;
    - einen zweiten Source-Transistor (25) mit einem ersten Anschluss, der auf den zweiten Spiegeltransistor (30) und auf jeweilige Steueranschlüsse des ersten und des zweiten Source-Transistors (20, 25) aufgeschaltet ist, und mit einem zweiten Anschluss, der auf den Bezugspotentialanschluss (23) aufgeschaltet ist, wobei der zweite Source-Transistor (25) im Vergleich zum ersten Source-Transistor (20) eine geringere Stromtreiberfähigkeit hat; und
    - einen Ausgang (13) zum Bereitstellen des Source-Signals (SO), der auf einen Eingang (14) des Puffers (12) aufgeschaltet ist,
    dadurch gekennzeichnet, dass
    - der Stromspiegel (18) einen vierten Spiegeltransistor (32) umfasst; und
    - die Signalquelle (11) einen zweiten Widerstand (24) umfasst, der den zweiten Anschluss des ersten Source-Transistors (20) auf den vierten Spiegeltransistor (32) und auf den Ausgang (13) der Signalquelle (11) aufschaltet.
  2. Signalgenerator nach Anspruch 1,
    wobei es sich bei dem Source-Signal (SO) und dem internen Signal (SI) um Spannungssignale und bei dem Referenzsignal (SREF, SBG) um die Summe aus dem Source-Signal (SO) und dem internen Signal (SI) oder die Summe aus dem vom Source-Signal (SO) abgeleiteten Signal (SO') und dem internen Signal (SI) handelt.
  3. Signalgenerator nach Anspruch 1 oder 2,
    wobei der Puffer (12, 56) einen Puffertransistor (27, 57) umfasst, der in einer Source-Nachläuferauslegung oder einer Emitter-Nachläuferauslegung arbeitet.
  4. Signalgenerator nach Anspruch 3,
    wobei der Puffertransistor (27, 57) verfügt über
    - einen Steueranschluss, der an den Eingang (14, 14') des Puffers (12, 56) angeschlossen ist, und
    - einen ersten Anschluss, der auf den dritten Spiegeltransistor (31) und auf einen Ausgang (17, 64) des Puffers (12, 56) aufgeschaltet ist, an dem das Referenzsignal (SREF, SBG) bereitgestellt wird, und
    wobei es sich bei dem internen Signal (SI) um eine Spannung zwischen dem Steueranschluss und dem ersten Anschluss des Puffertransistors (27, 57) handelt.
  5. Signalgenerator nach einem der Ansprüche 1 bis 4,
    ein Tiefpassfilter (15) umfassend, das zwischen dem Ausgang (13) der Signalquelle (11) und dem Eingang (14, 14') des Puffers (12, 56) angeordnet ist.
  6. Signalgenerator nach einem der Ansprüche 1 bis 5,
    einen weiteren Puffer (16) umfassend, der zwischen dem Ausgang (13) der Signalquelle (11) und dem Eingang (14, 14') des Puffers (12, 56) angeordnet ist.
  7. Signalgenerator nach einem der Ansprüche 1 bis 6,
    wobei der Puffer (12) einen Ausgang (17) zum Bereitstellen des Referenzsignals (SREF), einen ersten Ausgang (74) zum Bereitstelen eines ersten Referenzsignals (SREF1) und einen Spannungsteiler (71) umfasst, wobei der Spannungsteiler (71) an den Ausgang (17) des Puffers (12) angeschlossen ist, und der erste Ausgang (74) des Puffers (12) an einen Abgriff des Spannungsteilers (71) angeschlossen ist.
  8. Signalgenerator nach einem der Ansprüche 1 bis 7, Folgendes umfassend:
    - einen Stromgenerator (84) zum Generieren eines ersten Signals (I1), und
    - eine Stromquelle (80) zum Generieren eines zweiten Signals (I2),
    wobei das Vorzeichen des Temperaturkoeffizienten des ersten Signals (I1) zum Vorzeichen des Temperaturkoeffizienten des zweiten Signals (I2) entgegengesetzt ist und ein Referenzausgangssignal (IREF) bereitgestellt wird, indem das erste und das zweite Signal (I1, I2) aufsummiert werden.
  9. Verfahren zur Signalgenerierung, Folgendes umfassend:
    - Generieren eines Source-Signals (SO), bei dem es sich um ein zur Absoluttemperatur proportionales (PTAT) Signal handelt, und das an einem Ausgang (13) einer Signalquelle (11) bereitgestellt wird;
    - Generieren eines internen Signals (SI), bei dem es sich um ein zur Absoluttemperatur komplementäres (CTAT) Signal handelt; und
    - Generieren eines Referenzsignals (SREF, SBG), indem das interne Signal(SI) und das Source-Signal (SO) oder das interne Signal (SI) ein vom Source-Signal (SO) abgeleitetes Signal (SO') aufsummiert werden, wobei ein Puffer (12, 56) das interne Signal (SI) und das Referenzsignal (SREF, SBG) generiert;
    wobei die Signalquelle (11) umfasst:
    - einen ersten Source-Transistor (20) mit einem ersten Anschluss, der auf einen ersten Spiegeltransistor (29) eines Stromspiegels (18) und auf einen Steueranschluss des Stromspiegels (18) audgeschaltet ist, und mit einem zweiten Anschluss, der mittels eines ersten Widerstands (21) auf einen Bezugspotentialanschluss (23) aufgeschaltet ist;
    - einen zweiten Source-Transistor (25) mit einem ersten Anschluss, der auf einen zweiten Spiegeltransistor (30) des Stromspiegels (18) und auf jeweilige Steueranschlüsse des ersten und des zweiten Source-Transistors (20, 25) aufgeschaltet ist, und mit einem zweiten Anschluss, der auf den Bezugspotentialanschluss (23) aufgeschaltet ist, wobei der zweite Source-Transistor (25) im Vergleich zum ersten Source-Transistor (20) eine geringere Stromtreiberfähigkeit hat;
    dadurch gekennzeichnet, dass die Signalquelle (11) einen zweiten Widerstand (24) umfasst, der den zweiten Anschluss des ersten Source-Transistors (20) auf einen vierten Spiegeltransistor (32) des Stromspiegels (18) und auf den Ausgang (13) der Signalquelle (11) aufschaltet.
  10. Verfahren nach Anspruch 9,
    wobei es sich bei dem Source-Signal (SO) um eine Spannung mit Bezug auf den Bezugspotentialanschluss (23) und beim internen Signal (SI) um eine Spannung handelt, die zum Source-Signal (SO) oder zu dem vom Source-Signal (SO) abgeleiteten Signal (SO') hinzuaddiert wird.
EP11177486.5A 2011-08-12 2011-08-12 Signalgenerator und Verfahren zur Signalerzeugung Not-in-force EP2557472B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP11177486.5A EP2557472B1 (de) 2011-08-12 2011-08-12 Signalgenerator und Verfahren zur Signalerzeugung
PCT/EP2012/065627 WO2013023998A1 (en) 2011-08-12 2012-08-09 Signal generator and method for signal generation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP11177486.5A EP2557472B1 (de) 2011-08-12 2011-08-12 Signalgenerator und Verfahren zur Signalerzeugung

Publications (2)

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EP2557472A1 EP2557472A1 (de) 2013-02-13
EP2557472B1 true EP2557472B1 (de) 2017-04-05

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WO (1) WO2013023998A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024091584A1 (en) * 2022-10-28 2024-05-02 Texas Instruments Incorporated Reference voltage generation within a temperature range

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3021189B1 (de) 2014-11-14 2020-12-30 ams AG Spannungsreferenzquelle und Verfahren zur Erzeugung einer Referenzspannung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242897B1 (en) * 2000-02-03 2001-06-05 Lsi Logic Corporation Current stacked bandgap reference voltage source

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Publication number Priority date Publication date Assignee Title
US5126653A (en) * 1990-09-28 1992-06-30 Analog Devices, Incorporated Cmos voltage reference with stacked base-to-emitter voltages
US6181121B1 (en) * 1999-03-04 2001-01-30 Cypress Semiconductor Corp. Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture
US6362612B1 (en) * 2001-01-23 2002-03-26 Larry L. Harris Bandgap voltage reference circuit
US6614209B1 (en) * 2002-04-29 2003-09-02 Ami Semiconductor, Inc. Multi stage circuits for providing a bandgap voltage reference less dependent on or independent of a resistor ratio
US7224210B2 (en) 2004-06-25 2007-05-29 Silicon Laboratories Inc. Voltage reference generator circuit subtracting CTAT current from PTAT current
US7436245B2 (en) * 2006-05-08 2008-10-14 Exar Corporation Variable sub-bandgap reference voltage generator

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Publication number Priority date Publication date Assignee Title
US6242897B1 (en) * 2000-02-03 2001-06-05 Lsi Logic Corporation Current stacked bandgap reference voltage source

Non-Patent Citations (2)

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Title
CHRISTIAN JÃ Â CR SUS B FAYOMI ET AL: "Sub 1 V CMOS bandgap reference design techniques: a survey", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, KLUWER ACADEMIC PUBLISHERS, BO, vol. 62, no. 2, 18 August 2009 (2009-08-18), pages 141 - 157, XP019766237, ISSN: 1573-1979 *
REFEREX, XP040426082 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024091584A1 (en) * 2022-10-28 2024-05-02 Texas Instruments Incorporated Reference voltage generation within a temperature range

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WO2013023998A1 (en) 2013-02-21

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