EP2478551A1 - Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches - Google Patents

Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches

Info

Publication number
EP2478551A1
EP2478551A1 EP10776926A EP10776926A EP2478551A1 EP 2478551 A1 EP2478551 A1 EP 2478551A1 EP 10776926 A EP10776926 A EP 10776926A EP 10776926 A EP10776926 A EP 10776926A EP 2478551 A1 EP2478551 A1 EP 2478551A1
Authority
EP
European Patent Office
Prior art keywords
growth
group iii
iii nitride
semiconductor layers
wurtzitic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP10776926A
Other languages
German (de)
English (en)
Inventor
Armin Dadgar
Alois Krost
Roghaiyeh Ravash
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azzurro Semiconductors AG
Original Assignee
Azzurro Semiconductors AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azzurro Semiconductors AG filed Critical Azzurro Semiconductors AG
Publication of EP2478551A1 publication Critical patent/EP2478551A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation

Definitions

  • the invention relates to semi-polar wurtzitic group III nitride based
  • Group III nitride layers typically grow on substrates in the polar c-axis orientation.
  • GaN grow polarization-reduced or non-polar.
  • a planar polarization-reduced layer directly on silicon substrates without complex structuring.
  • a polarization-reduced alignment of the group III nitride layer can be achieved by using a planar substrate with a zincblende or diamond structure and a (111) surface> 9 ° misoriented surface as recited in claim 1.
  • Such surfaces exist z.
  • silicon usually from a sequence of stable (1 1 1) surfaces alternating with (OOl) -like steps or surfaces.
  • GaN with c-planar orientation grows on the (111) surfaces by suitable process control and is thus inclined to the surface by the corresponding angle. This succeeds particularly well with weak inclination, as for example with Si (21 1), since here the (11 1)
  • Pretreatment of the substrate i. the creation of broad steps with (111) surfaces by treatment with physical or chemical processes, whereby the resulting (1 1 1) terraces have a threefold surface symmetry.
  • Corresponding pretreatment allows for higher levels and thus wider (1 1 1) levels, where the group III nitride layer grows almost exclusively with c-axis orientation. You can do this, ideally, to the substrate
  • Suitable temperatures be it in the MOVPE or better in the MBE. Accordingly, the statements also apply to growth on germanium at lower growth temperatures.
  • Silicon surfaces which have a high proportion of Si (l 11) terraces, are suitable for this purpose. Important are, as described in claim 9, terraces with broad steps with (111) surfaces, the resulting (111) terraces having at least a width corresponding to two monolayers, ie that these terraces are not mere step edges, but is at least three adjacent surface atoms in a plane and thus the threefold symmetry of this surface is recognizable. Higher indicated areas, such. B. (411) and (511), but are also suitable depending on the growth temperature and pretreatment, since here also broader (111) surface sections can form and thus also suitable Ankeim consult are given. It turns out, however, that the growth becomes more difficult as the angle increases, because the crystallites twist and tilt more strongly due to the less well-oriented nucleation of the crystallites or the decreasing density of well-oriented nuclei.
  • Figure 2 shows a possible surface arrangement schematically.
  • possible steps (201) are to be seen, and in between the terraces of the (111) surfaces, which show either no (202) or (203) threefold symmetry of the surface atoms.
  • the steps should be at least 0.3 nm or, according to claim 9, two monolayers wide.
  • the growth of the Group III nitride layer is not monocrystalline or textured in one orientation, which is indispensable for a closed, high quality layer.
  • the seed layer high Al-containing, such. A1N, AlGaN, AlInN or AlGalnN.
  • the layer and the substrate destructive meltback etching
  • the growth of the layer generally generally begins with a pretreatment of the substrate surface to clean it of organic residues and to deoxygenate it.
  • a pretreatment of the substrate surface for this purpose, on the one hand there are wet-chemical methods or bake-out processes, the latter preferably being carried out in a high-purity chamber in the case of a group IV substrate, in order to prevent undesired contamination of the surface.
  • Wet-chemical methods are often based on a targeted oxidation of the surface, for. B. with H 2 S0 4 , and subsequent removal of the oxide by means of HF.
  • a hydrogen-terminated surface can be achieved which makes the desired step formation possible, since oxidized surfaces generally have no desired crystalline arrangement.
  • the prepared substrate is then placed in the test chamber and brought to Bekeimung as quickly as possible to the seeding temperature.
  • the growth of the germ layer begins
  • Nitrogen precursor is stabilized, adjusting the growth temperature necessary for high-quality thicker layers and the growth of a
  • Component buffer layer This is followed by the growth of the active or
  • Carrier gas flow (H 2 or N 2 ) is baked out and thereby the surface is changed.
  • the surface must be stabilized during such a process to prevent degradation, such.
  • care must be taken, at least in MOVPE processes, that heating does not cause any desorption of deposits of the reactor.
  • MOVPE reactor connected to the additional chamber for pretreatment, which ideally allows a transfer of the still hot substrate.
  • nitridation of at least one monolayer of the surface of the substrate may be achieved by passing ammonia, a nitrogen releasing compound or nitrogen radicals before the beginning of the Group III nitride growth, as described in claim 10.
  • ammonia a nitrogen releasing compound or nitrogen radicals
  • III-V zinc blende substrates such.
  • As GaAs by nitriding the upper substrate layers in the case of GaAs converted into GaN. Such processes are usually started by the introduction of ammonia or nitrogen radicals at temperatures> 350 ° C.
  • the temperature is then typically further increased to the optimum temperature for Group III nitride growth and growth of the device layer begun.
  • a single-crystal growth can be achieved even without forcing wide (11 1) terraces.
  • the process can also be carried out with initial stabilization of the III-V semiconductor layer with the group V element, ie z.
  • As an As precursor to GaAs are started and then converted by adding the nitrogen source this. This procedure also allows a higher
  • the growth on silicon substrates in an MOVPE process is described below: After cleaning the substrate, it is placed in the test or coating chamber and ideally heated in a hydrogen atmosphere to about 680 ° C. Due to the hydrogen atmosphere, it is possible to stabilize a hydrogen-terminated by the preparation surface, which is beneficial for the seeding effect. Then, as a first step, the pre-flow of aluminum in the form of an aluminum precursor, such as trimethylaluminum, takes place for about 2 to 15 seconds. This step is followed by opening the nitrogen precursor, such as. B: ammonia, or z. B. very suitable at low temperatures, dimethyl hydrazine. At the same time, ideally the aluminum supply remains open.
  • an aluminum precursor such as trimethylaluminum
  • Layer thicknesses of 1 ⁇ advantageous to either introduce a biasing AlGaN layer in the lower buffer or to use LT-A1N intermediate layers.
  • LT-A1N layers are more efficient here. With increasing tilt angle decreases due to the lower coefficient of thermal expansion perpendicular to the c-axis of the group III nitride layer from the tendency to crack, ie here also crack-free layer thicknesses without stress-reducing layers can be achieved, which are more than 1 ⁇ layer thickness.
  • FIG. 1 shows by way of example in cross-section the possible interface of a group III nitride layer to a group IV substrate with (211) surface.
  • This surface consists of (11 1) terraces and (001) steps.
  • the (11) terraces are tilted by about 18 ° to the surface normals.
  • Figure 2 shows schematically the top view of a tilted (1 1 1) surface, with only the (1 1 1) sections can be seen. Between the steps (201), terraces can be formed with (1 1 1) surfaces, which are either only one monolayer wide (202) or wider (203). On the narrow terrace (202) no threefold symmetry of the surface atoms can be seen; this occurs only on the broader one
  • FIG. 3 shows a scanning electron micrograph of a GaN on Si (21 1) surface. The remaining craters can be improved by optimizing the
  • the invention relates to all group III nitrides on zinc blende or group
  • the designation of surfaces or directions with () for surfaces and [] for directions is intended to include all equivalent surfaces or directions, e.g. B. (11 1) and the (1 ⁇ ), ( ⁇ 1), (111), (1 ⁇ ), (H l), (1 11), (III) surfaces.
  • it relates to all epitaxial manufacturing processes that are suitable for the preparation of Group III nitride layers. This often requires the
  • the growth temperatures in the MBE are usually always a few hundred degrees below the MOVPE or HVPE process.
  • Orientations for Si is a monocrystalline c-axis-oriented growth described in the literature and accordingly a tilted growth is not meaningful, since the possible low tilt angle is not worth mentioning
  • FET field effect transistor
  • HVPE Hydride Vapor Phase Epitaxy, hydride
  • MBE Molecular Beam Epitaxy, Molecular Beam Epitaxy
  • MEMS Micro Electromechnical Systems, Electromechanical
  • MOVPE Metal organic vapor phase epitaxy, organometallic
  • SAW Surface Acoustic Wave

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

1. Couches de semiconducteurs à base de nitrure du groupe III de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches. 2. Les couches de nitrure du groupe III trouvent de nombreuses applications en électronique et optoélectronique. La croissance de telles couches s'effectue généralement sur des substrats tels que le saphir, le SiC et plus récemment le Si (111). Les couches ainsi obtenues sont généralement orientées dans le sens de croissance de façon polaire ou dans l'axe c. La croissance de couches de nitrure du groupe III, non polaires ou semi-polaires, est intéressante voire nécessaire pour de nombreuses applications en optoélectronique, mais également pour des applications acoustiques dans des dispositifs à ondes acoustiques de surface. Le procédé selon l'invention permet une croissance aisée et peu onéreuse de couches de nitrure de type III, à polarisation réduite, sans nécessiter une structuration préalable du substrat.
EP10776926A 2009-09-20 2010-09-16 Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches Withdrawn EP2478551A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009042349A DE102009042349B4 (de) 2009-09-20 2009-09-20 Semipolare wurtzitische Gruppe-III-Nitrid basierte Halbleiterschichten und darauf basierende Halbleiterbauelemente
PCT/DE2010/001094 WO2011032546A1 (fr) 2009-09-20 2010-09-16 Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches

Publications (1)

Publication Number Publication Date
EP2478551A1 true EP2478551A1 (fr) 2012-07-25

Family

ID=43480844

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10776926A Withdrawn EP2478551A1 (fr) 2009-09-20 2010-09-16 Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches

Country Status (8)

Country Link
US (1) US20120217617A1 (fr)
EP (1) EP2478551A1 (fr)
JP (1) JP2013505590A (fr)
KR (1) KR20120083399A (fr)
CN (1) CN102668027A (fr)
DE (1) DE102009042349B4 (fr)
TW (1) TW201126757A (fr)
WO (1) WO2011032546A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299560B2 (en) * 2012-01-13 2016-03-29 Applied Materials, Inc. Methods for depositing group III-V layers on substrates
US9368582B2 (en) * 2013-11-04 2016-06-14 Avogy, Inc. High power gallium nitride electronics using miscut substrates
DE102014102039A1 (de) * 2014-02-18 2015-08-20 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Nitrid-Verbindungshalbleiterschicht
CN111448674B (zh) * 2017-12-05 2023-08-22 阿卜杜拉国王科技大学 用于形成分级纤锌矿iii族氮化物合金层的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2743901B2 (ja) * 1996-01-12 1998-04-28 日本電気株式会社 窒化ガリウムの結晶成長方法
JP3500281B2 (ja) * 1997-11-05 2004-02-23 株式会社東芝 窒化ガリウム系半導体素子およびその製造方法
JP2001093834A (ja) * 1999-09-20 2001-04-06 Sanyo Electric Co Ltd 半導体素子および半導体ウエハならびにその製造方法
JP3888374B2 (ja) * 2004-03-17 2007-02-28 住友電気工業株式会社 ＧａＮ単結晶基板の製造方法
JP2007095858A (ja) * 2005-09-28 2007-04-12 Toshiba Ceramics Co Ltd 化合物半導体デバイス用基板およびそれを用いた化合物半導体デバイス
JP2008021889A (ja) * 2006-07-14 2008-01-31 Covalent Materials Corp 窒化物半導体単結晶
US20080296626A1 (en) * 2007-05-30 2008-12-04 Benjamin Haskell Nitride substrates, thin films, heterostructures and devices for enhanced performance, and methods of making the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2011032546A1 *

Also Published As

Publication number Publication date
US20120217617A1 (en) 2012-08-30
JP2013505590A (ja) 2013-02-14
DE102009042349A1 (de) 2011-03-31
CN102668027A (zh) 2012-09-12
WO2011032546A1 (fr) 2011-03-24
TW201126757A (en) 2011-08-01
KR20120083399A (ko) 2012-07-25
DE102009042349B4 (de) 2011-06-16

Similar Documents

Publication Publication Date Title
EP1908099B1 (fr) Substrat a semi-conducteurs, procede de production associe, et couche de masque destinee a produire un substrat a semi-conducteurs isole au moyen d'une epitaxie d'hydrure en phase gazeuse
DE10392313B4 (de) Auf Galliumnitrid basierende Vorrichtungen und Herstellungsverfahren
US7674699B2 (en) III group nitride semiconductor substrate, substrate for group III nitride semiconductor device, and fabrication methods thereof
EP2815004B1 (fr) Procédé de production de monocristaux de iii-n, et monocristaux de iii-n
DE112006001847B4 (de) Ausrichtung von Laserdioden auf fehlgeschnittenen Substraten
EP2414567A1 (fr) Cristal semi-conducteur semi-polaire et procédé de préparation associé
JP4860736B2 (ja) 半導体構造物及びそれを製造する方法
DE10196361B4 (de) Verfahren zur Herstellung eines Gruppe-III-Nitrid-Halbleiterkristalls
WO2011032546A1 (fr) Couches de semiconducteurs à base de nitrure du groupe iii de type wurtzite, semi-polaires, et composants à semiconducteurs produits sur la base de ces couches
DE10151092B4 (de) Verfahren zur Herstellung von planaren und rißfreien Gruppe-III-Nitrid-basierten Lichtemitterstrukturen auf Silizium Substrat
DE60303014T2 (de) Zwischenprodukt für die Herstellung von optischen, elektronischen oder optoelektronischen Komponenten
DE10313315A1 (de) Verfahren zum Herstellen eines III-V-Verbundhalbleiters
DE102012204553B4 (de) Verfahren zur Herstellung eines Templats, so hergestelltes Templat, dessen Verwendung, Verfahren zur Herstellung von III-N-Einkristallen, Verfahren zur Herstellung von III-N-Kristallwafern, deren Verwendung und Verwendung von Maskenmaterialien
DE102011011043B4 (de) Halbleiterschichtsystem mit einem semipolaren oder m-planaren Gruppe-III-Nitrid Schichtsystem und ein darauf basierendes Halbleiterbauelement
KR101145595B1 (ko) 질화물계 화합물 반도체의 성장방법
RU2750295C1 (ru) Способ изготовления гетероэпитаксиальных слоев III-N соединений на монокристаллическом кремнии со слоем 3C-SiC
WO2001077421A1 (fr) Procede de croissance de materiaux cristallins semi-conducteurs contenant de l'azote
DE102012204551A1 (de) Verfahren zur Herstellung von III-N-Einkristallen, und III-N-Einkristall
DE10238135B4 (de) Verfahren zur Herstellung von Gruppe-II-Oxid Schichten mit der Gasphasenepitaxie, Gruppe-II-Oxid Schicht und Gruppe-II-Oxid Halbleiterbauelement
DE10206750A1 (de) Verfahren zum Herstellen von III-V-Laserbauelementen
DE10319972B4 (de) Verfahren zur Herstellung einer epitaktischen ZnO-Schicht
DE20122426U1 (de) Gruppe-III-Nitrid-basierte Lichtemitterstruktur auf Silizium Substrat
Kwon et al. The Influence of AlN Buffer Layer Thickness on the Growth of GaN on a Si (111) Substrate with an Ultrathin Al Layer
DE10321305A1 (de) Verfahren zur Herstellung von hoch leitfähigen, rissfreien, GaN-basierten Pufferschichten

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20120420

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
19U Interruption of proceedings before grant

Effective date: 20140430

19W Proceedings resumed before grant after interruption of proceedings

Effective date: 20151001

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20160401