Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
  • H01L21/02005—Preparing bulk and homogeneous wafers
  • H01L21/02008—Multistep processes
  • H01L21/0201—Specific process step
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

• the present invention relates to a method of enhancing the strength of semiconductor wafers or semiconductor chips, the semiconductor wafers being sliced from an ingot or cut from a foil and preprocessed in one or several preprocessing steps prior to further processing steps for generating semiconductor elements like microelectronic components or solar cells.
• Semiconductor wafers are reguired for many- applications in the field of photovoltaics, microelectronics and micro systems technology.
• the semiconductor materials like for example silicon, gallium arsenide or germanium used for the fabrication of semiconductor wafers are rather brittle materials. Due to this brittleness the semiconductor wafers may crack during the processing for the fabrication of solar cells or microelectronic components.
• a monocrystalline or multicrystalline ingot is formed which is then sliced to thin wafers, for example by a mechanical sawing process.
• Known techniques for the formation of single crystalline ingots are the Czochralski-Method or the Float-Zone- Method.
• For the formation of a multicrystalline ingot for example techniques like the Bridgman-Method or the Block-Cast-Method are applied.
• foils of the semiconductor material from a melt. These foils are then separated into single wafers by laser cutting or a mechanical cutting technique.
• the surface of the wafers is preprocessed in order to prepare the wafers for the later processing of the semiconductor components.
• preprocessing steps are etching of a damaged or contaminated surface layer, uniform doping of the wafer, lapping and polishing of the wafer surface.
• the preprocessing steps for the production of photovoltaic elements like solar cells are different from the preprocessing steps for the production of microelectronic components. For the fabrication of microelectronic components a higher purity of the semiconductor material as well as a higher surface quality of the semiconductor wafer is required.
• the preprocessing steps include a step of lapping the wafer surface, a step of etching the wafer surface after the lapping step and a step of polishing the wafer surface after the etching step.
• a step of lapping the wafer surface In the fabrication of solar cells only an etching step is applied in order to remove a thin damaged surface layer.
• the wafer or dies of the wafer are damaged on the surface or in the bulk material due to the foregoing slicing or cutting process.
• damages are micro-cracks, dislocations or internal stresses.
• the defects significantly influence the mechanical properties of the wafer, in particular the fracture strength of the wafer.
• a fracture of the wafer during the later processing has obvious disadvantages like loss of material, possible shut down times in the fabrication line and damages to the processing equipment. Therefore, in order to avoid a fracture of the brittle wafers during the later processing, the wafer slicing, cutting or thinning processes can be optimized to lower the damages or defects of the wafers as is explained for example in N.
• US 2008/0157241 Al discloses a method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects.
• the method starts with a lower quality semiconductor wafer including dispersed defects.
• these defects getter from the semiconductor bulk to form impurity clusters toward the surface contaminant layer, thereby increasing the purity level in wafer regions from which the impurities are gettered.
• the surface contaminant layer including the impurity clusters is then removed by etching. This allows the use of lower quality semiconductor wafers for solar cell processing.
• the document does not deal with the problem of fracture of semiconductor wafers and is silent about any effect of the proposed preprocessing steps on the strength of the semiconductor wafers.
• At least one annealing step is performed in addition to the one or several preprocessing steps and processing steps by non-homogenous heating of the wafers or chips or by sequential local heating of several or all portions of the wafers or chips.
• This step can be applied at any time during the fabrication of the semiconductor elements, for example solar cells or microelectronic elements, at which time a damage of portions of the wafers or chips has been caused by forgoing processing or preprocessing steps and at which time the annealing step would not the desired results of the previous processing.
• the overall fracture strength is increased and the energy consumption for the annealing step is minimized. It is nevertheless also possible to only heat portions of the wafers or chips which show an increased damage or to anneal the whole wafer or chip by sequentially local heating of all portions of the wafer or chip. Also in the last case the energy consumption is lower than in the case of a furnace heating of the whole wafer or chip.
• This first alternative of the proposed method can be applied in the production of photovoltaic elements like solar cells as well as in the production of other semiconductor elements, in particular microelectronic elements .
• Non-homogeneous heating means that portions of the wafer or chip are heated to a higher temperature than other portions. This results in a temperature gradient in the wafer or chip. In contrast to a homogenous heating, at the end of which the temperature at each point of the wafer or chip is the same, during the non- homogenous heating a temperature gradient is maintained. The wafer or chip is thus locally or regionally heated to a higher temperature than in the remaining regions. This local heating can also be applied in a sequential manner in which several portions of the wafer or chip are heated sequentially to the higher temperature. Such a sequential local heating can be applied for example to the whole wafer or chip or at least to the whole upper and/or lower surface of the wafer or chip.
• the annealing step is performed prior to the first preprocessing step, i.e. before the etching step of removing the damaged and contaminated surface layer or before the lapping step in case of wafers for the fabrication of microelectronic elements. This measure already lowers the fracture risk during the first preprocessing step.
• the non-homogeneous heating or sequential local heating is preferably performed with an energy beam, in particular a laser beam, which may be scanned over the portions to be heated.
• an energy beam in particular a laser beam
• other techniques of local and contact less heating of the wafers or chips can be applied, for example by using infrared lamps or by using heating elements like heating wires or heating rods close to the surface of the wafers or chips.
• the common preprocessing steps applied to the semiconductor wafers prior to the further processing for generating semiconductor elements comprise etching steps for removing a damaged surface layer, steps for doping the semiconductor wafers and steps for improving the smoothness of the wafer surface like lapping and polishing.
• the preprocessing steps in case of the fabrication of semiconductor elements for photovoltaics are different from the preprocessing steps in case of the fabrication of semiconductor elements for microelectronic applications.
• Microelectronic applications require a significantly higher purity of the semiconductor material and a higher quality of the wafer surface than semiconductor wafers for applications in photovoltaics, like for the fabrication of solar cells. Therefore, the semiconductor wafers for microelectronic applications after being sliced or cut are typically first lapped, then etched and then polished.
• the semiconductor wafers for applications in photovoltaics are typically only etched in order to remove the damaged surface layer. Nevertheless, in both cases additional preprocessing steps like doping may be included in the preprocessing.
• the wafers are further processed to generate the desired semiconductor elements, like microelectronic elements or components or like solar cells.
• the wafers are cut during the further processing into single chips which may still be further processed.
• the second alternative of the proposed method relates to semiconductor wafers or semiconductor chips in a production line for fabricating photovoltaic elements.
• the at least one annealing step is performed in addition to the one or several preprocessing steps and processing steps after a first preprocessing step of removing a surface layer from the wafers.
• the first preprocessing step means between the first preprocessing step and the next preprocessing or processing step, or between or after any steps following the first preprocessing step.
• the third alternative of the proposed method relates to semiconductor wafers or semiconductor chips in a production line for fabricating microelectronic elements.
• the at least one annealing step is performed in addition to the one or several preprocessing steps and processing steps after a preprocessing step of lapping a surface of the wafers and prior to a further preprocessing step of polishing the wafer surface.
• the annealing step can be performed in a furnace for global heating of the wafers or chips.
• the annealing step is performed in order to heat the semiconductor wafers or chips or portions of the semiconductor wafers or chips to temperatures of ⁇ 200 0 C.
• An upper limit of the annealing temperature is the melting point of the semiconductor material. The temperatures are kept below this melting point. Depending on the temperature different annealing times may be applied, preferably longer annealing times at lower temperatures and higher annealing times at higher temperatures. The annealing times may range from a few seconds to several hours.
• the wafers or chips are cooled down, preferably to room temperature, i.e. to a temperature of between 20 and 30° C.
• the annealing step is preferably performed in a vacuum environment or under an inert gas environment, for example an argon gas environment.
• the annealing step according to the second and third alternative can be applied at different stations during the production of the semiconductor elements. Examples are given in figures 1 and 2.
• the annealing step in the second and third alternative may be applied by homogeneous heating or by non-homogeneous heating.
• the present method is applied to semiconductor wafers for the production of semiconductor elements in photovoltaics, in particular for the production of solar cells.
• the semiconductor wafers preferably have a lower quality, i.e. a higher content of impurities than in the case of the fabrication of microelectronic elements. Since the wafers for these applications are not lapped or polished they still have a higher risk of fracture than the semiconductor wafers preprocessed for applications in microelectronics.
• the additional annealing step prior to or during the preprocessing of the semiconductor wafers for semiconductor elements of photovoltaics increases the yield of the whole process without significantly enlarging the process time and thus reduces the costs of the photovoltaic elements.
• Fig. 1 an example of preprocessing and processing steps of semiconductor wafers for photovoltaic applications
• Fig. 2 an example of preprocessing steps of semiconductor wafers for microelectronic applications
• Fig. 3 an example of a temperature profile for the annealing step of the proposed method
• Fig. 4 a measurement showing the difference in fracture probability of monocrystalline semiconductor wafers with and without the proposed annealing step
• Fig. 5 a measurement showing the difference in fracture probability of multicrystalline silicon wafers with and without the proposed annealing step;
• Fig. 7 schematically an example of the local annealing of the wafer edges with a laser beam.
• Figure 1 shows an example of some of the preprocessing and processing steps of semiconductor wafers for photovoltaic applications, in the present case for the production of solar cells.
• a semiconductor ingot is first sliced into individual semiconductor wafers by a wire saw. The damages caused on the surface of the semiconductor wafers by the sawing process are subsequently removed by etching back the surface of the wafers to a depth of one or several micrometers.
• the semiconductor wafers are doped using POCL 3 at a temperature of approximately 900 0 C.
• an Al containing paste is applied by screen printing. The paste is dried at a temperature of approximately 200 0 C and subsequently baked at a higher temperature of approximately 850 0 C. After these steps the fabrication of the solar modules is performed.
• At least one annealing step is performed in addition to the above described preprocessing and processing steps.
• This annealing step can be performed between the sawing step and the etching step, between the etching step and the doping step, between the doping step and the screen printing step, between the drying step and the baking step or between the baking step and the later local processing.
• These different positions 1 of the annealing step between the preprocessing and processing steps are indicated in figure 1 by double arrows. It is obvious for the skilled person that further processing or preprocessing steps may be included between the steps shown in figures 1 and 2.
• the proposed annealing step is always an additional step, in addition to the standard process steps which are required for the fabrication of the semiconductor element .
• Figure 2 shows an example of some of the preprocessing steps of semiconductor wafers for the production of semiconductor components in microelectronics.
• the applications in microelectronics require semiconductor material with a higher purity and with a higher surface quality as in the case of applications in photovoltaics .
• the semiconductor wafers in this case are achieved by slicing the ingots with a wire saw or with an ID saw. After the sawing step the wafers are lapped. Then the wafer edges are rounded off and a surface layer is removed in an etching step. After this etching step the wafer surface is polished in order to get the required high surface smoothness.
• the wafers are then further processed in a known manner in order to produce the desired microelectronic elements .
• At least one annealing step is performed according to the present invention prior to the further processing.
• This annealing step is performed in addition to the above preprocessing steps and is preferably added between the sawing step and the lapping step. It is also possible to include the annealing step between the lapping step and the step of rounding off the wafer edges or between the step of rounding off the wafer edges and the etching step. These different positions 1 within the pre-treating process are indicated in figure 2 by double arrows.
• An annealing step for the whole wafer after the polishing step is not useful in this case since the polished wafers already have an increased strength which cannot be significantly further improved by a subsequent global annealing step.
• the proposed method allows the use of semiconductor wafers with signify- cantly larger damages after the sawing step for the further processing, since such wafers are improved in the facture strength by the proposed annealing step. This results in a higher yield of the wafer processing.
• Figure 3 shows an example of an annealing step of the present invention.
• the temperature of the wafer or at least a portion of the wafer is increased to a temperature of approximately 1000 °C for a time of approximately one hour.
• the wafer is cooled down during a period of approximately 9 to 10 hours to room temperature.
• This is only an example for the annealing step which may also be performed with different temperatures and different heating and cooling times.
• Figure 4 shows the measured probability of fracture dependent on the fracture stress for monocrystalline silicon wafers treated according to the present invention in comparison to reference wafers which have not been treated according to the present invention.
• Figure 5 shows the same comparison for multicrystalline silicon wafers. It is obvious from the above measurements that the proposed annealing step according to the present invention in addition to the common preprocessing steps significantly increases the fracture strength of the wafers and thus the yield of the whole process of semiconductor manufacturing.
• Tests with different annealing temperatures have been performed with monocrystalline silicon wafers.
• the wafers have been annealed at temperatures of 200 0 C, 300 0 C, 400°C, 600 0 C, 800°C and 1000°C under an argon gas environment for approximately one hour.
• the measured characteristic fracture stress after the annealing step shows an increase of the fracture stress with rising annealing temperatures from 200°C to 600 0 C.
• a further increase of the annealing temperature does not further increase the fracture stress but lowers this fracture stress compared to the value at 600 0 C.
• Figure 6 shows the corresponding measurement of the characteristic fracture stress dependent on the annealing temperature.
• the figure also shows the fracture stress of a wafer which has not been treated according to the present invention, i.e. the measurement at a temperature of 25°C. It can be recognized that the annealing at an annealing temperature of 200 0 C already increases the fracture strength of the wafer.
• the annealing step according to the present invention can be performed with the whole wafer. This may be wafers for applications in microelectronics which after the dicing step may be further thinned, for example by back etching.
• the annealing step is only performed locally, in particular at the edges of the semiconductor wafers. This local annealing step can also be applied later during the further wafer processing, for example after dividing the wafer into single chips.
• the chip edges, which are damaged by the cutting step can be locally annealed to enhance their strength, for example using a laser beam for heating. The same applies to the chip edges of solar cells for concentrators or other applications.
• the annealing step can be performed after each processing step which allows a further annealing without damaging the desired results of the previous processing steps and which enhances the strength of the chip or wafer at least locally.
• Figure 7 shows two schematic views of the local heating of the edge portion 3 of a circular and of a rectangular semiconductor wafer 2.
• the circular wafer is used for applications in microelectronics
• the rectangular wafer is used for the fabrication of solar cells.
• the edge portion 3 is heated by a laser beam 4 which is scanned about the circumference of the wafer 2.
• a laser beam - or another energy beam or locally impinging radiation - also the whole wafer surface can be heated. In the latter case the impinging beam is moved over the whole wafer surface so that all regions of this wafer surface are sequentially heated.
• the non-homogenous heating may be applied such that the whole surface layer of the wafer is heated to the higher temperature, whereas the underlying bulk material remains at a lower temperature.
• the sequential local heating may also be applied by moving the wafer relative to a stationary heat source locally applying heat, for example by moving the wafer surface relative to a heating element maintaining a constant distance of the surface to the heating element.

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• 2010
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