WO2010083995A3 - Method of enhancing the strength of semiconductor wafers or chips - Google Patents

Method of enhancing the strength of semiconductor wafers or chips Download PDF

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Publication number
WO2010083995A3
WO2010083995A3 PCT/EP2010/000328 EP2010000328W WO2010083995A3 WO 2010083995 A3 WO2010083995 A3 WO 2010083995A3 EP 2010000328 W EP2010000328 W EP 2010000328W WO 2010083995 A3 WO2010083995 A3 WO 2010083995A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor wafers
strength
semiconductor
enhancing
chips
Prior art date
Application number
PCT/EP2010/000328
Other languages
French (fr)
Other versions
WO2010083995A2 (en
Inventor
Jörg BAGDAHN
Alexander Bohne
Stephan SCHÖNFELDER
Carola Fischer
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V
Priority to EP10700719A priority Critical patent/EP2380190A2/en
Publication of WO2010083995A2 publication Critical patent/WO2010083995A2/en
Publication of WO2010083995A3 publication Critical patent/WO2010083995A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Photovoltaic Devices (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)

Abstract

The present invention relates to a method of enhancing the strength of a semiconductor wafer or semiconductor chip, the semiconductor wafers being sliced from an ingot or cut from a foil and preprocessed in one or several preprocessing steps prior to further processing steps for generating semiconductor elements. In the proposed method at least one annealing step is performed in addition to the one or several preprocessing steps and processing steps. With the proposed method the fracture strength of semiconductor wafers can be significantly enhanced thus allowing the use of semiconductor wafers with a higher degree of damages and increasing the yield of the whole wafer processing.
PCT/EP2010/000328 2009-01-21 2010-01-20 Method of enhancing the strength of semiconductor wafers or chips WO2010083995A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10700719A EP2380190A2 (en) 2009-01-21 2010-01-20 Method of enhancing the strength of semiconductor wafers or chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009005484 2009-01-21
DE102009005484.7 2009-01-21

Publications (2)

Publication Number Publication Date
WO2010083995A2 WO2010083995A2 (en) 2010-07-29
WO2010083995A3 true WO2010083995A3 (en) 2010-09-23

Family

ID=42307843

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2010/000328 WO2010083995A2 (en) 2009-01-21 2010-01-20 Method of enhancing the strength of semiconductor wafers or chips

Country Status (2)

Country Link
EP (1) EP2380190A2 (en)
WO (1) WO2010083995A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014107238B4 (en) * 2014-05-22 2020-01-23 Hanwha Q Cells Gmbh Semiconductor wafer treatment process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060016385A1 (en) * 2004-07-22 2006-01-26 Sumitomo Mitsubishi Silicon Corporation Silicon wafer and method for manufacturing the same
WO2007148490A1 (en) * 2006-06-20 2007-12-27 Shin-Etsu Handotai Co., Ltd. Silicon wafer manufacturing method and silicon wafer manufactured by the method
US20080157241A1 (en) * 2006-12-30 2008-07-03 Calisolar, Inc. Semiconductor wafer pre-process annealing & gettering method and system for solar cell formation
WO2010016586A1 (en) * 2008-08-08 2010-02-11 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Method for manufacturing semiconductor wafer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060016385A1 (en) * 2004-07-22 2006-01-26 Sumitomo Mitsubishi Silicon Corporation Silicon wafer and method for manufacturing the same
WO2007148490A1 (en) * 2006-06-20 2007-12-27 Shin-Etsu Handotai Co., Ltd. Silicon wafer manufacturing method and silicon wafer manufactured by the method
EP2031647A1 (en) * 2006-06-20 2009-03-04 Shin-Etsu Handotai Co., Ltd Silicon wafer manufacturing method and silicon wafer manufactured by the method
US20080157241A1 (en) * 2006-12-30 2008-07-03 Calisolar, Inc. Semiconductor wafer pre-process annealing & gettering method and system for solar cell formation
WO2010016586A1 (en) * 2008-08-08 2010-02-11 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Method for manufacturing semiconductor wafer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SUOEKA K ET AL: "Dependence of Mechanical Strength of Czochralski Silicon Wafers on the Temperature of Oxygen Precipitation Annealing", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US LNKD- DOI:10.1149/1.1837541, vol. 144, no. 3, 1 March 1997 (1997-03-01), pages 1111 - 1120, XP002470185, ISSN: 0013-4651 *

Also Published As

Publication number Publication date
EP2380190A2 (en) 2011-10-26
WO2010083995A2 (en) 2010-07-29

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