Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
  • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0469—Details of the physics of pixel operation
  • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
  • G09G2300/0482—Use of memory effects in nematic liquid crystals
  • G09G2300/0486—Cholesteric liquid crystals, including chiral-nematic liquid crystals, with transitions between focal conic, planar, and homeotropic states
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/04—Partial updating of the display screen
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

• the invention relates to a method for addressing a liquid crystal display screen and a display device applying this method.
• the field of the invention is that of liquid crystal displays. More specifically, the present invention relates to nematic liquid crystal bistable displays. It is particularly applicable to nematic liquid crystal bistable displays whose two stable textures differ by a twist of about 180 °.
• the object of the present invention is to improve the performance of bistable display devices.
• the object of the invention is to improve, by the use of new means, the switching of states of the pixels of the display so as to make the desired switching of the pixels homogeneous over the entire display.
• the most widely used liquid crystal displays use a nematic type liquid crystal. They consist of a layer of liquid crystal placed between two blades. Each blade comprises a substrate, often made of glass, on which a conductive electrode has been deposited, followed by a so-called anchoring layer, also called an alignment layer.
• the anchoring layer exerts on the neighboring liquid crystal molecules a return torque which tends to orient them parallel to a direction called easy axis.
• Anchor layers are often made by a brushed polymer deposit to create the direction of the easy axis. This is most often very close to the direction of brushing.
• the thickness of the cell thus formed is made constant by distributing, between the blades, beads whose diameter is equal to the desired thickness (typically 1 to 6 microns).
• TN twisted nematic
• STN supertordus
• EOB electrically controlled birefringence
• VAN vertically aligned nematic
• the bistable display which we will designate in the rest of the description under the trade name BINEM® ([I] to [5]) is shown schematically in FIG. 1. It uses two textures, which differ by a twist of about +/- 180 °, in absolute value between 150 ° and 180 °.
• a uniform or slightly twisted texture U illustrated on the left of FIG. 1 in which the molecules are substantially parallel to each other, and the other texture T (illustrated on the right of FIG. Figure 1) bent at about 180 °.
• the liquid crystal layer 30 is placed between two blades 20 and 10, which is called master blade and slave blade.
• the master blade 20 comprises a substrate 21, an electrode 22 and an anchoring layer 24 providing a strong azimuth and zenith anchorage of the liquid crystal.
• the slave blade 10 comprises a substrate 11, an electrode 12 and an anchoring layer 14 providing a low zenith anchorage and a medium or strong azimuthal anchoring of the liquid crystal.
• the usually transparent electrodes 12 and 22 are typically made of a material called ITO and deposited on the substrates 11 and 21. They make it possible to apply an electric field perpendicular to the plates 10 and 20.
• each texture is associated with an optical state, for example dark for the texture U and clear for the texture T or vice versa, depending on the angles of the two polarizers with respect to the directions of anchoring.
• the nematic is chiralised with a spontaneous pitch po, chosen close to four times the thickness d of the cell, to equalize the energies of the two aforementioned textures.
• the ratio between cell thickness d and po spontaneous pitch, d / po, is therefore about 0.25 +/- 0.1.
• the states T and U are the states of minimum energy: the cell is bistable.
• the term "switching" of a BiNem® screen element will be used to pass the molecules of the liquid crystal from an initial stable texture (U or T or a coexistence of these two textures) to a stable texture. final (U or T or a coexistence of these textures).
• the signal applied to the pixel is conventionally made up of several stages, the transitions from one bearing to the other being called sidewalls. Each bearing is preceded by a leading edge consisting of the transition between the preceding bearing and said bearing and followed by a trailing edge consisting of the transition between said bearing and the next bearing.
• the breaking of the electric field corresponds to one or more rear flanks of the applied signal (reduction of the electric voltage in absolute value).
• the signal applied to the pixel VP (FIG.
• gray levels in a pixel by controlling the intensity of the hydrodynamic flow via the variation of the signal at the terminals of the pixel. For a given value of the pixel signal, a fraction of its texture surface T is obtained within the same pixel and the other fraction U is a texture. At another pixel signal value and therefore this hydrodynamic flow corresponds to a ratio different between the surfaces occupied by the two textures U and T. Gray levels are thus obtained [9].
• the Binem® display is a matrix screen consisting of N x M screen elements called pixels, where N is the number of rows and M is the number of columns, and the addressing takes place online. after line.
• each pixel is constituted by the intersection of a line conductive strip 52 and a column conductor strip 50 (see FIG. 3). These perpendicular strips are deposited respectively on the master blades 20 and slave 10.
• the area between two adjacent conductive strips carried by the same substrate 11 or 21 ( Figure 1) is called interpixel space.
• the area consists of the set of pixels is called matrix area.
• the matrix area corresponds to the display area, on which area the image content that is to be displayed is displayed.
• the aforementioned conductive strips 50, 52 are transformed into tracks which make the connection to the control circuits generating the addressing signal.
• These control circuits may be located on the substrate or remote.
• the displays are addressed using components or control circuits that we will call “drivers” located for example on flexible connection elements welded to the screen.
• the drivers consisting mainly of analog gates controlled by shift registers, make it possible to make the link between the control electronics and the tracks.
• a line addressing signal VLn is applied on the line n and a column addressing signal VCm on the column m.
• the conductive electrodes are made of a transparent conductive material called ITO (mixed oxide of Indium and tin). But when the display is reflective, the electrodes located on the opposite side to the observer can be made with an opaque conductive material, for example aluminum.
• the first phase essentially consists in obtaining an anchoring break, ie the homeotropic texture on the line considered, by applying for example a voltage VlL> Vcass on the line addressing signal for a duration T1, which constitutes a first level of VL.
• VlL is between 6V and 30V over the 0 ° - 50 ° temperature range.
• a signal V2L is applied on the line for example V2L £ VlL for a duration T2, which constitutes a second and last level of VL.
• V2L is between 2 V and 12V over the 0 ° - 50 ° temperature range.
• the line addressing signal is in this two-stage example, but it can also be single-stage or multi-stage. Electrical signals called "data" called VC are applied simultaneously on all the columns. According to a conventional variant, the falling edge of the data signal VC is synchronized with the falling edge of the second stage of the line activation signal V2L [I].
• the texture U or T is obtained in the pixel corresponding to the intersection of this column and the activated line [6].
• the next line is turned on, the other lines are off and so on from the first to the last line of the display.
• the time between the end of activation of a line and the beginning of the activation of the next line is called TL interline time. This time is typically but not limited to between 10 ⁇ s and 10 ms. The value of this time is very important for good switching, and can vary with temperature. We will call this addressing "one-step addressing".
• the order of activation of the lines (first n-1, then n, then n + 1) defines the scanning direction 46
• the addressing time of the display is the time required to address all its lines, so as to display new image content.
• Document [9] describing the achievement of gray levels provides three variants for obtaining gray levels (FIG. 23 of document [9]) by modifying the parameters of VC.
• a first variant consists in varying the amplitude of the Vcol voltage level (in the case of a slot-type column addressing signal) applied to the pixel P.
• a second variant consists in varying the duration te of the VC column addressing signal applied to the pixel P. In these two variants the trailing edge of the column addressing signal is synchronized with the trailing edge of the second and last stage of the line addressing signal.
• phase modulation consists of the variation of the desynchronization ⁇ Tc of the VC column addressing signal with respect to the trailing edge of the second and last stage of the line addressing signal.
• Document [12] recommends desynchronization of the signal column addressing with respect to a trailing edge of an intermediate bearing other than the last step of the line addressing signal.
• partial addressing it is desired to display new content in only one area of the image, the rest of the image remaining unchanged. In this case, only the lines corresponding to the zone to be displayed are activated.
• the entire addressing of the screen (display of a complete image) or of an area of the screen is collectively performed.
• partial addressing in a given texture, usually T, by simultaneously activating all the lines or a group of lines corresponding to the area to be addressed, with a signal Vpre (see Figure 4).
• the lines are then addressed one by one, according to the conventional multiplexing method, to display the desired image or area. Only two types of transitions must then be made, the transition T to T on the one hand, and the transition T to U or to a mixture of U and T on the other hand.
• This "two-step addressing" makes it possible to better control the switching of the pixels, in particular for controlling the gray levels, because thus the pixels all start from a well-defined state at the beginning of the second step.
• FIG. 4 the principle of multiplexed passive addressing of the Binem® display in two steps is illustrated in FIG. 4.
• the values VC1 to VC5 are the values of VCm applied on column m in synchronization with lines 1 to 5, successively activated, so as to obtain the desired final texture on the pixel at the intersection of the activated line and the column. m.
• VC (U) + Vcol
• VC (T) -Vcol or good:
• the brushing direction of the alignment layers is orthogonal to the direction of the lines of the display, this type of display is called "orthogonal brushing" ( document [9]) -
• line parameters of the signal VL voltage levels and duration of each step, for example (V 1 L, V 2 L, T 1, T2) and time spaced TL column parameters of the VC signal: voltage levels and duration of each step, for example for a single-stage slot signal (Vcol, te) , possibly ⁇ Tc desynchronization value with respect to a trailing edge of a line signal.
• these parameters are a function of the temperature and the size of the pixels.
• Vrms mean square voltage
• a signal Vcomp is applied to the column in question m, at a time when this signal will have no influence on the choice of the final texture.
• the data signal synchronized rather at the end of the activation signal, is applied.
• the amplitude of the signal Vcomp typically a slot, is calculated as a function of the value Vc of the data column signal in order to obtain a predetermined constant mean square voltage Vrms, identical for each pixel [8].
• Figure 5 illustrates an example of a timing chart applying this method.
• the activation voltage of the line n is in this bipolar example, ??? to prevent effects of electrolysis of the liquid crystal, but only the second part of the signal VL, in this example the positive polarity, is the useful signal for the addressing of the line in question.
• Vcoll and Vcol2 of column signals are illustrated, with values (VcI, such) and (Vc2, tc2) corresponding for example each to a specific gray level. It can be seen that the value of Vcomp (duration and / or amplitude) varies as a function of the applied data signal, in order to obtain for both cases a constant and predetermined mean square value Vrms. After many experiments, several types of switching faults have come to light. These defects appear in spatially determined areas of the display.
• addressing parameters of the line addressing signal of the VL voltage level of each step, duration of these steps, and interlaced time TL.
• addressing parameters of the line addressing signal of the VL voltage level of each step, duration of these steps, and interlaced time TL.
• a line addressing signal comprising two steps: (VlL, V2L, T1, T2, TL)
• - addressing parameters of the VC column signal voltage level of each step, duration of these bearings, desynchronization value ⁇ Tc of a trailing edge of a column address signal bearing relative to a trailing edge of a step of the line addressing signal, value of Vcomp.
• a column addressing signal comprising a single step (slot type): (Vcol, te, ⁇ Tc, Vcomp)
• these parameters are a function of the temperature and the size of the pixels, but the parameters of the line addressing signal VL are identical for all the pixels of the display and the parameters of the signal of VC column addressing can take as many values as states of the desired textures, but these values are the same for all the pixels of the display.
• the switching of the Binem® in passive mode is sensitive to the electrical and geometrical characteristics of the addressing band, which is not the case in active mode (see Document [7]). From what has been described above, a specificity of the Binem® is that the switching of texture T requires the pixel to apply a sudden drop in absolute value of voltage, called active back flank. This sidewall must keep a voltage drop in absolute value sufficiently steep to the extreme points (rows and columns) of the display, that is to say located furthest from the beginning of electrodes for addressing lines and columns directly connected to the control circuits.
• the texture switching U is also sensitive to the shape of the pixel signal, and to the synchronization of the line addressing signal with the column addressing signal (Document [12]).
• the behavior of the ITO band is characterized by a time constant RC, constituted by the charging time of the pixel capacitance Cpx through the resistances of the tracks and bands.
• This characteristic time will directly affect the shape of the signal, line and column, as described in FIG. 6a for an example of a line addressing signal, and 6b for an example of a column addressing signal.
• the least deformed signals, that is to say close to the beginning of the line addressing electrode, are given in solid lines, the signals influenced by the constant RC, therefore more distant are represented in dashed lines.
• the line addressing signal is bi-terminal, of levels VlL and V2L, the rear flanks of the two levels being respectively denominated FL1 and FL2.
• FLId and FL2d designate the trailing edges of the addressing signal at the beginning of the line.
• FLIF and FL2f designate the trailing flanks towards the "end" of the line. Due to the effect of the constant RC, it is noted that the rear flanks at the end of the line are deformed relative to the rear flanks at the beginning of the line.
• the column signal is for example, single-stage, of level Vcol.
• FCd designates the trailing edge of the column addressing signal at the "beginning" of the column addressing electrode directly connected to the control circuit
• FCf designates the trailing edge of the column addressing signal located towards the "end” of the column. Due to the effect of the constant RC, it is noted that the trailing edge at the end of the column is deformed relative to the trailing edge at the beginning of the column.
• the document [7] quantitatively describes an example of disruption of the end-of-line commutation (see FIG. 10a and 10b of this document). Document [7] demonstrates that the value of RC increases quadratically with the distance to the driver connection. It can be seen in FIGS.
• the time constant RC influences both the slope of the signal propagating on the electrode strip (decrease of the slope in absolute value) and the duration of the voltage step (s). (reduction of this duration).
• This double modification is thus likely to create switching heterogeneities in the areas "too far" from the beginning of the electrode.
• the shape of the voltage signal at the terminals of the last pixel is always compatible with the desired switching.
• both the shape of the line pulse and the shape of the column pulse contribute to the shape of the pixel signal and are therefore likely to influence the switching of the pixel, in U or T.
• an important parameter is, among other things, the slope of the active trailing edge.
• FIG. 7 illustrates, by way of example, the different areas of the display that may pose a problem. These are the areas located some distance from the beginning of the line addressing electrodes or columns connected to the control circuit DRL for the lines and DRC for the columns, the phenomenon being amplified as and when the away from the beginning of the row or column addressing electrodes.
• ZRCL is the area at the end of the row addressing electrodes and ZRCC the area at the end of the column strips. Possible switching problems may appear in these areas ZRCC and / or ZRCL.
• FIG. 8 shows an illustrative Binem® type QVGA display 56.6 mm (312 lines) x 40.95 mm (234 columns) corresponding to a square pixel of 175 microns pitch.
• the column bands are the longest, and in the zone ZRCC, there are pixel switching defects, with the presence of texture T in the pixels to be completely filled in U-textures (default called “T”). in U ").
• T U-textures
• FIG. 8 it can be seen that in the lower right part of the screen (part corresponding to the zone common to the zones ZRCC and ZRCL of FIG. 7) the pixels of are not completely switched to texture U (dark color) and have textures T (light color).
• the parameters used are:
• the document [8] describes the influence of the RMS voltage of the column addressing signals on the switching and a method allowing its stabilization in order to avoid switching faults.
• the implementation of this method is problematic for the first lines of the display, corresponding to the zone ZRMS in Figure 7.
• a series of pre-pulses are applied, for example via the columns before the display of the image itself, so that the first lines of the display also see a constant RMS (see variant 4 and Figure 19 of document [8]).
• a large number of pre-pulses must be applied, resulting in the extension of the frame time necessary for the display of an image.
• a 25% increase in the frame time has been noted to obtain a correct switching of the first lines with a standard signal of the type described in the previous paragraph.
• FIG. 9 shows the display described in the previous paragraph for which an insufficient number of pre-pulses, in this case about ten, has been applied.
• the invention therefore relates to a method for addressing a nematic bistable nematic liquid crystal matrix screen having two stable states without an applied electric field.
• This screen comprises two substrates between which the liquid crystal is arranged.
• the first substrate has line addressing electrodes and the second substrate has column addressing electrodes.
• the said addressing electrodes are in the form of electrically conductive strips.
• the switching of each pixel from one stable state to another is controlled by a switching voltage pulse obtained by the application of at least one line addressing signal applied to a first end of an electrode. line addressing and the application of at least one column addressing signal applied to a first end of a column addressing electrode.
• the characteristics of the row addressing signals and / or the characteristics of the column addressing signals for the switching of a pixel of the matrix screen are a function of the position of said pixel in said matrix screen.
• the addressing of the pixels of said matrix screen is of the passive multiplex type.
• the line addressing signal has at least one voltage plateau and in that at least one of the following parameters of the line addressing signal is a function of the position of each pixel in the matrix screen:
• the line addressing signal has at least two voltage levels and that at least one of the following parameters of the line addressing signal is a function of the position of each pixel in the line addressing signal.
• the method according to the invention can provide that it comprises at least one voltage step and in that at least one of the following parameters of the column addressing signal is a function of the position of the pixel in the matrix screen: - voltage level of said column address signal voltage plateau, duration of said column addressing signal plateau, desynchronization time of the trailing edge of said voltage plateau of the column addressing signal with respect to a trailing edge of a voltage plateau of a line addressing signal.
• the voltage level of the line addressing signal is a function of the number of the line in the matrix screen.
• the method according to the invention also provides that the line addressing signal may comprise at least one upper level followed by a lower level in absolute value and that the voltage level of the lower level is a function of the number of the line. in the matrix screen.
• the characteristics of the column addressing signal of a pixel are a function of the number of the column to which this pixel belongs.
• the characteristics of the column addressing signal of a pixel are a function of the number of the line to which this pixel belongs.
• the line addressing signal has the same characteristics for all the rows of the matrix screen.
• each column addressing signal is applied to one end of the column addressing electrodes and in that the voltage level of the lower level of the line addressing signal is increased in absolute value when the position of the addressed line addressing electrode moves away from said ends of the column addressing electrodes.
• a signal is applied to all the pixels. conferring the same state, that is, the same texture.
• the method according to the invention also optionally provides that to modify only the display of an area of the image of the matrix screen, a line addressing signal is applied only to the row electrodes corresponding to said zone.
• the direction of brushing of the anchoring layers is orthogonal to the direction of the line electrodes (L1-LN) of the matrix screen.
• the respective twists of the two stable textures of the liquid crystal differ from 150 ° to 180 ° in absolute value.
• the invention also provides that to modify only the display of an area of the image of the matrix screen, a line addressing signal is applied only to the row electrodes corresponding to said zone.
• the respective twists of the two stable textures of the liquid crystal differ from 150 ° to 180 ° in absolute value.
• the invention also relates to a method of addressing a liquid crystal matrix screen which provides that a second line addressing signal is applied to a second end of said line addressing electrode, and / or that a second column addressing signal is applied to a second end of said column addressing electrode.
• the first and the second line addressing signal are of identical shapes and / or the first and second column addressing signals are of identical shapes.
• the two said line addressing signals are synchronized with each other and / or both said column addressing signals are synchronized with each other.
• the two said line addressing signals are the same signal and / or the two said column addressing signals are the same signal.
• a first and a second line addressing signal and / or a first and a second address addressing signal. column are respectively applied to each row addressing electrode and / or to each column addressing electrode.
• the first line addressing signals are identical to each other and are shifted together by a fixed interlining time (TL). It is also advantageously provided that the line addressing signals are all identical in shape and that the line addressing signals have at least one trailing edge which is synchronized with at least one trailing edge of the column addressing signals. .
• the line addressing signals have a first bearing and at least one intermediate bearing and in that at least one of the rear flanks of the column addressing signals is synchronized with the sidewall. rear of said first bearing or with the trailing edge of said intermediate bearing row addressing signals.
• the line addressing signals have a first bearing and at least one intermediate bearing and in that at least one of the rear flanks of the column addressing signals is desynchronized with respect to the rear flank of said first bearing or relative to the trailing edge of said intermediate level of the line addressing signals.
• the voltage level of the first step is greater in absolute value than the voltage level of the intermediate bearing.
• each line addressing electrode is intended to be connected either to a very high impedance or to a generator providing a voltage equal to the voltage at which one of the rear flanks of the signal of line addressing. It will advantageously be provided that each line addressing signal applied to one of the ends of the line electrode has an at least sufficient value, combined with the value of each column addressing signal to switch about half of the pixels. of said line of the matrix screen located on the side where the line addressing signal is applied, no signal being applied to the other end.
• the invention also provides a variant in which the method comprises at least three steps: a first step of addressing the lines located on the side of the first ends of the column electrodes during which first signals of addressing of columns are applied to these first ends, no signal being applied to the second ends of the column electrodes, a second step of addressing the lines located in the central part of the lines of the matrix screen during which first column addressing signals are applied to the first ends of the column addressing electrodes and second column addressing signals are applied to the second ends of the column addressing electrodes; a third step of addressing the rows; located on the side of the second ends of the column addressing electrodes during which second column addressing signals are applied to these second ends, no signal being applied to the first ends of the column electrodes.
• the invention also relates to a display device as described above and in which a control circuit makes it possible to control the characteristics of said line addressing signal and / or the characteristics of said column addressing signal as a function of the position. a pixel to control in the matrix screen.
• the addressing of the pixels of said matrix screen is of passive multiplex type.
• the line addressing signal has at least two different voltage levels and the control circuit controls at least one of the following parameters of the line addressing signal as a function of the position of each pixel in the matrix screen:
• control circuit controls at least one of the following parameters of the column addressing signal as a function of the position of the pixel in the matrix screen: voltage levels of the column addressing signal, duration of the column address signal, - desynchronization duration of the trailing edge of said column address signal voltage plateau with respect to a trailing edge of a voltage plateau of a line addressing signal.
• the voltage level of at least one step of the line addressing signal is a function of the position of the line in the matrix screen.
• the line addressing signal comprises at least one upper bearing followed by a lower bearing and in that the central control circuit controls the voltage level of the lower bearing as a function of the position of the line. in the matrix screen.
• the characteristics of the column addressing signal of a pixel are a function of the number of the column of said pixel, whereas the line addressing signal has the same characteristics for all the rows of the matrix screen. .
• the invention also relates to a bistable liquid crystal display device having two stable states without an applied electric field comprising at least two line control circuits each connectable to one end of a line addressing electrode and making it possible to apply two line addressing signals at both ends of the row addressing electrodes and / or two column control circuits each connectable to one end of each column addressing electrode and making it possible to apply at least two signals of column addressing at both ends of the column addressing electrodes.
• the two line control circuits making it possible to address the same line addressing electrode are the same circuit having, for each line electrode, two outputs, and / or in that the two control circuits of columns enabling to address the same column addressing electrode are the same circuit having two outputs for each column.
• FIG. 1 schematically shows the bistable display of the BiNem type
• FIG. 2 describes an example of a voltage level bi-level pixel addressing signal (VlP, V2P) and the active trailing edge of this signal as a function of the level of voltage of the V2P stage,
• FIG. 3 describes the structure of a multiplexed passive addressing matrix liquid crystal screen
• FIG. 4 describes an example of two-step addressing of a passive screen of the BiNem type
• FIG. 5 describes a timing diagram of the method for obtaining a predetermined constant mean square voltage.
• FIGS. 6a and 6b describe an exemplary measurement of a bi-level line addressing signal at a location very close to the connection to the control circuit and at a place remote from this connection,
• FIG. 7 schematically describes a matrix screen type display as well as the different zones of this screen which may be disturbed in terms of switching by the effect of the time constant RC 5 .
• FIG. 8 represents a screen having display faults in a zone remote from the ends of the row and column electrodes to which addressing signals are applied;
• FIG. 9 represents photos of a screen also presenting faults; display,
• FIGS. 10a and 10b illustrate exemplary embodiments of the method according to the invention
• FIGS. 10c and 10d schematize variations, according to the invention, of voltage levels of a line addressing signal
• FIG. 11 represents photos of a screen which does not have, according to the invention, display defects
• FIG. 12 represents control circuits of a matrix screen according to the invention
• FIG. 13 describes different variants of the invention.
• Figure 13a describes a variant where the invention is applied to a line of the display.
• Figure 13b describes a variant where the invention is applied to all lines of the display.
• Figure 13c describes a variant where the invention is applied to all the columns of the display.
• FIG. 13d describes a variant in which the invention is applied to all the rows and columns of the display;
• FIG. 14 describes a variant of the invention that uses control circuits.
• FIG. 14a describes a variant of the invention in which the row addressing electrodes are connected at each of their ends to a control circuit.
• FIG. 14b describes a variant of the invention in which the column addressing electrodes are connected at each of their ends to a control circuit,
• FIG. 15 describes a variant of the invention in which the two ends of the row addressing electrodes are connected to the same control circuit.
• DETAILED DESCRIPTION In order to solve the problems and switching faults described above, and also other faults that may appear on displays BiNem® type, the invention consists in applying a pixel signal VP, defined by all the parameters.
• pixel addressing which, for a given temperature range and pixel shape, depends on the spatial position of the pixel considered in the display.
• a pixel P is identified with respect to the number of its line n (n from 1 to N, for example in the scanning direction), and its column m (m from 1 to M).
• the pixel signal VP applied to the pixel P (n, m) becomes according to the invention a function of its position in the display VP (n, m).
• the pixel voltage VP becomes a function of n and / or m, that is to say that the line signal becomes a function of n, VL (n), and / or the column signal becomes a function of m,
• the line addressing signal VL becomes a function of n, VL (n), where n is the number of the line and the column addressing signal VC is independent of m. It depends only on the texture one wishes to obtain.
• at least one parameter of the line addressing signal is variable as a function of the line n.
• VC becomes a function of m, column number, and possibly n, with the line addressing signal VL remaining independent of n.
• at least one parameter of the column signal is variable as a function of the column m and possibly of the line n.
• the first and second variants are combined, and at least one parameter of the line addressing signal is a function of n while at least one parameter of the column addressing signal is a function of m and possibly of n for addressing a pixel P (n, m).
• the variation of at least one parameter of the line addressing signal and / or the column addressing signal can be defined for example, according to a first nonlimiting option, by a function (linear, polynomial or other) of n and / or m.
• the variation of at least one parameter of the line addressing signal and / or the column addressing signal can be defined for example by ranges. A group of adjacent rows or columns then have a constant value of this / these parameters, this constant being able, for example, but not limited to being defined by a function.
• the parameters on which the invention may be applied are in a nonlimiting manner: parameters of the line addressing signal VL:
• Vcol or te, ⁇ Tc, Vcomp according to m.
• the advantage of using a ⁇ Tc synchronization variation has the advantage of not introducing a spatial variation of the RMS voltage.
• the invention is applied by compensating for this problem of homogeneity by a variation of the line signal VL (n), so as to favor the U-switching for the lines corresponding to the ends of the columns, that is to say, for example, for the lines of the zone ZRCC of FIG.
• the invention is applied by offsetting this problem of homogeneity by a variation of signal line VL (n), so as to favor the switching in T for the first lines.
• the invention makes it possible to simultaneously correct the defects previously described and present in ZRMS and ZRCC.
• the invention it can be seen that, at a given temperature, when addressing with a two-level line addressing signal VlL and V2L, a reduction in absolute value of V2L favors the texture T and an increase in value. absolute of V2L favors the texture U which will allow to obtain this double correction.
• the implementation of the invention in this case consists in varying the amplitude of V2L as a function of n, with a rather lower value of V2L for the first lines (favoring switching in T) and a rather higher value. V2L for the last lines (favor U-switching).
• First step pre-T signal of bipolar form of amplitude of 25 V applied for twice 2 ms.
• Second step bipolar line signal, first polarity + 25 V for 250 ⁇ s and second polarity:
• FIG. 11 shows an image inscribed with this method.
• the zooms on the zones ZRMS and ZRCC show the disappearance of the preceding faults described in FIG. 9.
• FIG. 12 represents a matrix screen such as that of FIG. 7 with its DRL line electrode addressing circuit and its addressing circuit. DRC column.
• a central control circuit CC makes it possible to control the addressing circuits to control the addressing of the rows and columns and to control the characteristics of the row and column addressing signals as a function of the positions of the rows and columns. as just described.
• the present invention is of course applicable for obtaining homogeneous gray levels on the whole of the display.
• the invention also relates to a method for addressing a liquid crystal display addressed in a passive type multiplex mode in which a line addressing signal and a column signal are applied to one of the ends of the line addressing electrodes and of columns.
• addressing signals are also applied to the other end of said row and / or column addressing electrodes.
• the addressing is done using control circuits of the "driver" type.
• at least one line addressing electrode is addressed according to the invention.
• FIG. 13a describes a matrix screen including a line addressing electrode Ln, the line and the line electrode being grouped under the same name L, comprising a first end ELn through which a first line addressing signal is applied. VLn and a second end ELn 'by which is applied a second line addressing signal VLn'.
• FIG. 13b describes a matrix screen, each of whose row electrodes L1-LN is addressed by a first line addressing signal VL1 to VLN via a first end EL1 to ELN and by a second line addressing signal VL1 'to VLN 'via a second end EL1' to ELN '.
• the column addressing electrodes are addressed according to the state of the art, via a single end.
• FIG. 13c describes a matrix screen in which each of the column electrodes C1 to CM is addressed by a first column addressing signal VCl to VCM via a first end EC1 to ECM and by a second column addressing signal VCl 'to VCM 'via a second end EC1' to ECM '.
• the lines L1-LN are addressed with a line electrode signal VL1 to VLN via a single end EL1 to ELN.
• FIG. 13d describes such a combination that combines addressing according to the invention of all the rows and all the columns.
• the row and / or column addressing signal is obtained by at least one control circuit connected to the ends of the row and / or column addressing electrodes via connection tracks.
• FIG. 14a describes the connection of all the lines L1 to LN to a control circuit DRL1, from outputs drll.l to drll.N, at the first ends EL1 to ELN via the tracks PL1 to PLN and to a control circuit DRL2, from outputs drl2.1 to drl2.N, at the second ends ELl 'to ELN' via tracks PL1 'to PLN'.
• FIG. 14b describes the connection of all columns C1 to CM to a control circuit DRCl from outputs drcl.l to drcl.M at the first ends EC1 to ECM and to a control circuit DRC2 from outputs drc2.1. at drc2.M at the second ends EC1 'to ECM', while the lines L1-LN are conventionally connected to a control circuit DRL1 via the outputs drll.l to drll.N at the first ends EL1 to ELN only.
• the two ends of the same row addressing electrode and / or the same column addressing electrode are connected via the tracks to the same control circuit.
• the addressing signals according to the invention applied to the two ends are synchronized.
• the addressing signals applied to the two ends are of identical shapes. According to another variant, the addressing signals applied to the two ends are the same signal supplied by a common control circuit such as the control circuit DRL3 of FIG. 15.
• a variant suitable for improving the discharge only is to apply at one end of the band a standard addressing signal via a control circuit and at the other end a binary signal via a switch-type component, collectively for all bands: either a very high impedance, to maintain the applied voltage, or a low impedance connection to the voltage level that is desired at the end of the discharge.
• the discharge is thus accelerated by using a simpler component than a driver component used for the addressing of the passive displays.
• the invention is compatible with the addressing of a zone of the screen only, in which it is desired to display a new content, the rest of the image remaining identical (partial addressing).
• the invention is compatible with addressing in two steps, a first collective step intended to make all the pixels pass in the same state, that is to say the same texture, then a second step where the addressing is done. according to the classic multiplex mode.
• the signal applied according to the invention at the second end of the electrodes is also applied during the first step.
• the invention is compatible with obtaining gray levels as described in the state of the art.
• the activation signal of the lines VlL to VNL is identical for all the lines, equal to VL.
• the same addressing signal is applied to both ends of the row and / or column addressing electrodes as a function of the position of the pixel in the matrix screen.
• the invention is also applicable to an active type bistable display comprising a transistor per pixel as described for example in document [7].
• the line signal serves only to "open" the transistor, so in this case the invention consists in spatially modulating the column signal only.
• the present invention also has other advantages.
• a first advantage is the possibility, because of the possible correction of the effect of the RC, to achieve with bistable Binem® type technology large displays
• Another advantage is that the correction of the aforementioned defects increases the control capabilities of the display, that is to say the range of optimization of the driving parameters.
• Another advantage is the increase of the refresh rate since according to the state of the art, without the implementation of the invention, an increase in the frame time was necessary to reduce or eliminate certain switching faults.

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• 2007
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  • 2008-04-15 WO PCT/FR2008/000543 patent/WO2008142301A1/fr active Application Filing
  • 2008-04-15 US US12/600,814 patent/US20100149168A1/en not_active Abandoned
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