Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
  • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
  • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
  • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
  • G06F11/2023—Failover techniques
  • G06F11/2033—Failover techniques switching over of hardware resources
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
  • G06F11/25—Testing of logic operation, e.g. by logic analysers
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
  • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
  • G06F11/2046—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share persistent storage

Definitions

• This invention relates to adapter cards and more particularly relates to adapter card failover.
• a data processing system often includes a plurality of processor complexes.
• Each processor complex may include one or more microprocessors, cache memory, main memory, bridges to peripheral devices and buses, and the like.
• a processor complex may communicate with a Peripheral Component Interconnect (PCI) bus through a north bridge and a south bridge.
• PCI Peripheral Component Interconnect
• Adapter card peripheral devices such as network connections, storage devices, specialized compute engines, and the like may communicate with the processor complexes through the PCI bus.
• Adapter cards typically comprise a plurality of semiconductor circuits mounted on a circuit board.
• An adapter card may connect to a bus through one or more connectors.
• Each adapter card may perform one or more specialized functions.
• adapter cards may function as Ethernet controllers, Redundant Array of Independent Disks (RAID) controllers, and the like.
• More than one processor complex of a data processing system may require access to an adapter card.
• a cluster of two or more processor complexes may access a RAID controller adapter card in order to write data to and read data from hard disk drives in a fault-tolerant RAID subsystem.
• the adapter card communicating with two processor complexes may be referred to as a twin-tailed adapter card.
• the processor complex controlling the adapter card is referred to herein as an owner processor complex.
• the owner processor complex may configure and manage the adapter card. Providing a single owner processor complex may prevent two or more processor complexes from attempting to configure and manage the adapter card.
• an apparatus, system, and method for adapter card failover.
• an apparatus, system, and method would preferably transfer control of an adapter card from an original owner processor complex to allow the continued use of the adapter card.
• the apparatus for adapter card failover is preferably provided with a plurality of modules configured to functionally execute the steps of connecting a first processor complex, connecting a second processor complex, detecting a failure, and modifying a switch module.
• modules in the described embodiments include a switch module, a detection module, and a setup module.
• the switch module includes semiconductor logic and logically connects a first processor complex to an adapter card through a first port as an owner processor complex.
• the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card.
• the switch module further logically connects a second processor complex to the adapter card through the second port as a non-owner processor complex.
• the non-owner processor complex manages the second port.
• the detection module includes semiconductor logic and software instructions executing on a processor. In addition, the detection module detects a failure of the first processor complex.
• the setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• the setup module includes software instructions executing on a processor. The apparatus performs a failover from the first processor complex to the second processor complex if the first processor complex fails.
• a system of the present invention is also presented for adapter card failover.
• the system may be embodied in a data processing system.
• the system in one embodiment, includes a first processor complex, a second processor complex, and an adapter card.
• the first and second processor complexes are in communication with the adapter card.
• the second processor complex preferably includes a setup module.
• the adapter card includes a controller, a first memory module, and a switch module.
• the controller manages the adapter card.
• the first memory module stores a control store comprising software instructions and setup data for the controller.
• the switch module includes semiconductor logic and logically connects the first processor complex to the adapter card through a first port as an owner processor complex.
• the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card.
• the switch module further logically connects a second processor complex to the adapter card through the second port as a non-owner processor complex.
• the non-owner processor complex manages the second port.
• the setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• the system preferably fails over from the first processor complex owning the adapter card to the second processor complex owning the adapter card in response to the failure.
• a method of the present invention is also presented for adapter card failover.
• the method in the disclosed embodiments substantially includes the steps to carry out the functions presented above with respect to the operation of the described apparatus and system.
• the method includes connecting a first processor complex, connecting a second processor complex, detecting a failure, and modifying a switch module.
• a switch module connects a first processor complex to an adapter card through a first port as an owner processor complex.
• the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card.
• the switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex.
• the non-owner processor complex manages the second port.
• a detection module detects a failure of the first processor complex.
• a setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• the method preferably performs a failover from the first processor complex to the second processor complex so that the adapter card continues to be useable.
• an apparatus for adapter card failover comprising: a switch module comprising semiconductor logic and configured to logically connect a first processor complex to an adapter card through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card, and the switch module further logically connects a second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port; a detection module comprising semiconductor logic and software instructions executing on a processor and configured to detect a failure of the first processor complex; and a setup module comprising software instructions executing on a processor and configured to modify the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• a system for adapter card failover comprising: a first processor complex in communication with an adapter card; a second processor complex in communication with the adapter card and comprising a detection module configured to detect a failure of the first processor complex; the adapter card comprising a controller configured to manage the adapter card; a first memory module configured to store a control store comprising software instructions and setup data for the controller; a switch module comprising semiconductor logic and configured to logically connect the first processor complex to the adapter card through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card, and the switch module further logically connects the second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port; the second processor complex further comprising a setup module configured to modify the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to
• a processor program product comprising a processor useable medium having a processor readable program, wherein the processor readable program when executed on a processor causes the processor to: connect a switch module of an adapter card to a first processor complex through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card; connect a second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port; detect a failure of the first processor complex; and modify the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• a method for adapter card failover comprising: logically connecting, using a switch module, a first processor complex to an adapter card through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card; logically connecting, using the switch module, a second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port; detecting a failure of the first processor complex; and modifying the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
• the embodiment of the present invention performs a failover from a first processor complex that owns an adapter card to a second processor complex.
• the present invention supports preferably the continued use of the adapter card when the first processor complex fails.
• Figure 1 is a schematic block diagram illustrating one embodiment of a data processing system in accordance with the present invention
• Figure 2 is a schematic block diagram illustrating one embodiment of an adapter card of the present invention
• Figure 3 is a schematic block diagram illustrating one alternate embodiment of an adapter card of the present invention.
• Figure 4 is a schematic block diagram illustrating one embodiment of a failo ver apparatus of the present invention.
• Figure 5 is a schematic flow chart diagram illustrating one embodiment of a failo ver method of the present invention
• Figure 6 is a schematic block diagram illustrating one embodiment of adapter card communications of the present invention
• Figure 7 is a schematic block diagram illustrating one alternate embodiment of adapter card communications of the present invention.
• Figure 8 is a schematic block diagram illustrating one embodiment of failo ver communications of the present invention.
• modules may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
• a module may also be implemented in programmable hardware devices such as field programmable gate arrays (FPGA), programmable array logic, programmable logic devices or the like.
• FPGA field programmable gate arrays
• Modules may also be implemented in software for execution by various types of processors.
• An identified module of executable code may, for instance, comprise one or more physical or logical blocks of processor instructions, which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
• a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices.
• operational data may be identified and illustrated herein within the modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including different storage devices.
• FIG. 1 is a schematic block diagram illustrating one embodiment of a data processing system 100 in accordance with the present invention.
• the data processing system 100 includes one or more processor complexes 105, and an adapter card 110. Although for simplicity, two processor complexes 105 are shown, any number of processor complexes 105 may be employed.
• the first and second processor complexes 105a-b communicate with the adapter card 110 over one or more communications channels 120.
• the communication channels 120 are configured as a Peripheral Component Interconnect Express (PCIe) bus.
• PCIe Peripheral Component Interconnect Express
• the communication channels 120 may be configured as a Peripheral
• PCI-X Component Interconnect Extended
• PCI Peripheral Component Interconnect
• the adapter card 110 performs one or more functions for the first and second processor complexes 105a-b.
• the adapter card 110 may function as an Ethernet controller.
• the adapter card 110 may function as a RAID controller.
• the adapter card 110 functions as storage area network controller.
• One of skill in the art will recognize that the present invention may be practiced with a plurality of adapter card types and functions.
• the first processor complex 105a is initially configured as the owner processor complex.
• the owner processor complex initializes, controls, and manages the adapter card 110.
• the first processor complex 105a as owner processor complex may discover and initialize the adapter card 110 as will be described hereafter.
• the second processor complex 105b is initially configured as a non-owner processor complex.
• the data processing system may include a plurality of non-owner processor complexes.
• a non- owner processor complex may also use the adapter card 110.
• a non-owner processor complex may employ a RAID controller adapter card 110 to access a RAID subsystem.
• non-owner processor complexes do not initialize, manage, and/or control the adapter card 110.
• the adapter card 110 may communicate with a device 115.
• the device may be a network interface, a RAID subsystem, a storage device, and the like.
• the owner processor complex may also discover and initialize the device 115. Non-owner processor complexes may be unable to discover the device 115 during initialization as will be described hereafter.
• the adapter card 110 may be unusable by the second processor complex 105b. As a result, the data processing system 100 may lose critical functionality.
• the present invention in accordance with a preferred embodiment, performs a fail over of ownership of the adapter card 110 from the first processor complex 105 a to the second processor complex 105b to support the continued use of the adapter card 110 as will be described hereafter.
• FIG 2 is a schematic block diagram illustrating one embodiment of an adapter card 250 of the present invention.
• the adapter card 250 is one embodiment of the adapter card 110 of Figure 1.
• the description of the adapter card 250 refers to elements of Figure 1, like numbers referring to like elements.
• the adapter card 250 includes one or more ports 205, a switch module 210, a controller 230, setup registers 235, a memory module 240, and adapter card functions 245.
• the ports 205 may be configured as PCI interfaces, PCIe interfaces, PCI-X interfaces, and the like.
• the first processor complex 105a may communicate with a first port 205a while the second processor complex 105b may communicate with a second port 205b.
• the switch module 210 logically and physically connects the first processor complex 105 a to the adapter card 110 through the first port 205a as the owner processor complex.
• the owner processor complex manages the adapter card 110, except for the second port 205b.
• the owner processor complex receives error messages from the adapter card 110.
• the switch module 210 further logically and physically connects the second processor complex 105b to the adapter card 110 through the second port 205b as a non-owner processor complex.
• the non-owner processor complex manages the second port 205b.
• the adapter card functions 245 may include communication functions such as an Ethernet controller function, a token ring controller function, and the like.
• the adapter card functions may include communication functions such as an Ethernet controller function, a token ring controller function, and the like.
• the 245 may also include storage management functions such as a RAID controller function, a storage controller function, and the like.
• the controller 230 manages the adapter card 110.
• the controller 230 may initialize and manage the adapter card functions 245.
• the memory module 240 stores a control store comprising software instructions and setup data for the controller 230.
• the controller 230 may include a processor, instruction sequencer, and the like that executes the software instructions.
• the software instructions may be configured as one or more processor program products.
• the setup registers 235 store binary data values.
• the function of the switch module 210, adapter card functions 245, controller 230, and memory module 240 may be modified by the data values stored in the setup registers 235.
• a value stored in the setup registers 235 may cause the switch module 210 to configure a processor complex 105 connected to the first port 205 a as the owner processor complex and to configure a processor complex connected to the second port 205b as a non-owner processor complex.
• Figure 3 is a schematic block diagram illustrating one alternate embodiment of an adapter card 350 of the present invention.
• the adapter card 350 is an alternate embodiment of the adapter card 110 of Figure 1.
• the description of the adapter card 250 refers to elements of Figures 1-2, like numbers referring to like elements.
• the ports 205, switch module 210, controller 230, and setup registers 235 are the ports 205, switch module 210, controller 230, and setup registers 235 of Figure 2.
• the adapter card 350 further includes a first and second memory module 240a-b.
• the first memory module 240a stores a first control store comprising software instructions and setup data for the controller 230.
• the first control store configures the switch module 210 and the controller 230 to treat the processor complex 105 in communication with the first port 205 a as the owner processor complex and to treat the processor complex 105 in communication with the second port 205b as a non-owner processor complex.
• the second memory module 240b stores a second control store that also comprises software instructions and setup data for the controller 230.
• the second control store configures the switch module 210 and the controller 230 to treat the processor complex 105 in communication with the second port 205b as the owner processor complex and to treat the processor complex 105 in communication with the first port 205 a as a non-owner processor complex.
• the first and second memory modules 240a-b each share a binary address bus and a binary data bus.
• a first binary value stored in the setup registers 235 may enable the first memory module 240a and disable the second memory module 240b so that only the first memory module 240a outputs data on the binary data bus.
• An opposite second binary value stored in the setup registers 235 may disable the first memory module 240a and enable the second memory module 240b to output data on the binary data bus.
• a control store used by the controller 230 may be selected using a value written to the setup registers 235.
• the adapter card 350 further includes a RAID controller 305 and a first and second downstream port 310a-b.
• the first and second downstream ports 310a-b communicate with first and second RAID subsystems 315a-b respectively.
• the RAID controller 305, downstream ports 310, and RAID subsystems 315 are exemplary of functionality that may be supported by the adapter card 350 and are not shown by way of limitation.
• the first and second processor complexes 105a-b may each access the first and second processor complexes 105a-b
• the RAID controller 305 and switch module 210 may arbitrate priority between the first and second processor complexes 105, so that each processor complex 105 may access the RAID subsystems 315.
• the RAID controller 305 may further autonomously perform one or more RAID controller functions, such as calculating parity stripe data, recovering lost data from redundant data, and the like.
• FIG 4 is a schematic block diagram illustrating one embodiment of a failover apparatus 400 of the present invention.
• the apparatus 400 may be embodied in one or more processor complexes 105 of Figure 1 and the adapter cards 110, 250, 350 of Figures 1-3.
• the description of the apparatus 400 refers to elements of Figures 1-3, like numbers referring to like elements.
• the apparatus 400 includes the switch module 210, a detection module 405, and a setup module 410.
• the switch module 210 includes semiconductor logic as is well known to those of skilled in the art.
• the switch module 210 may include a crossbar switch, a non-blocking point-to-point switch, and the like.
• the switch module 210 may connect the first port 205a and the second port 205b to one or more semiconductor devices of the adapter card 110.
• the detection module 405 includes semiconductor logic and software instructions executing on a processor such as the second processor complex 105b and/or the controller processor. In addition, the detection module 405 detects a failure of the first processor complex 105 a as will be described hereafter.
• the setup module 410 modifies the switch module 210 to connect the second processor complex 105b to the adapter card 110 as the owner processor complex and to logically disconnect the first processor complex 105 a from the adapter card in response to detecting the failure.
• the setup module 410 includes software instructions executing on a processor such as the second processor complex 105b and/or the controller processor. The apparatus performs a failover from the first processor complex to the second processor complex.
• the schematic flow chart diagram that follows is generally set forth as a logical flow chart diagram. As such, the depicted order and labeled steps are indicative of one embodiment of the presented method. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow chart diagrams, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown.
• FIG. 5 is a schematic flow chart diagram illustrating one embodiment of a failover method 500 of the present invention.
• the method 500 substantially includes the steps to carry out the functions presented above with respect to the operation of the described apparatus and system of Figures 1-4.
• the method is implemented with a processor program product comprising a processor readable medium having a processor readable program.
• the processor readable program may be integrated into a semiconductor device, such as the controller 230 and/or processor complex 105, wherein the program in combination with the controller 230 and/or processor complex 105 are capable of performing the method 500.
• the method 500 begins and the switch module 210 connects 505 the first processor complex 105a to the adapter card 110 through the first port 205a as an owner processor complex.
• the owner processor complex manages the adapter card 110 except for the second port 205b and receives error messages from the adapter card 110.
• the owner processor complex may initialize the adapter card 110 during a power-on boot as will be described hereafter.
• the owner processor complex may also communicate directly with the controller 230.
• the adapter card 110 is configured as a RAID controller adapter card 350 and the RAID controller adapter card 350 detected a hard disk drive failure in a RAID subsystem 315, the RAID controller adapter card 350 may communicate an error message describing the failure to the owner processor complex.
• the switch module 210 further connects 510 the second processor complex 105b to the adapter card 110 through the second port 205b as a non-owner processor complex.
• the non- owner processor complex does not initialize the adapter card 110.
• the non- owner processor complex may not receive error messages, status messages, and the like from the adapter card 110.
• the RAID controller adapter card 350 if the RAID controller adapter card 350 experiences a hard disk drive failure, the RAID controller adapter card 350 does not communicate an error message to the non-owner processor complex.
• the non-owner processor complex manages the second port 205b. In one embodiment, only the non-owner processor complex communicates with the second port 205b. Alternatively, the non-owner processor complex may set a data transfer rate for the second port 205b, direct the second port 205b to communicate data, and the like.
• the detection module 405 detects 515 a failure of the first processor complex. 105a.
• the detection module 405 is configured as a processor program product comprising software instructions executing on the second processor complex 105b.
• the detection module 405 may periodically communicate with the first processor complex 105a. If the detection module 405 is unable to communicate with the first processor complex 105 a during a specified interval, the detection module 405 may detect 515 the failure of the first processor complex. 105a.
• a multi-node operating system executing on and managing the first and second processor complexes 105a-b may detect the failure of the first processor complex 105 a.
• the multi-node operating system may communicate an error message to the detection module 405 in response to a failure of the first processor complex 105 a and the detection module 405 may detect 515 the failure of the first processor complex 105 a from the error message.
• the detection module 405 is configured as semiconductor logic coupled with a processor program product executing on a processor of the controller 230.
• the detection module 405 may detect 515 the failure of the first processor complex 105 a if the first processor complex 105 a does not communicate with adapter card 110 during a specified time interval. For example, if the first processor complex 105a does not communicate with the adapter card 110 during a two (2) minute time interval, the detection module 405 may query the first processor complex 105a. If the first processor complex 105a does not respond, the detection module 104 may detect 515 the failure of the first processor complex 105 a.
• the setup module 410 modifies 520 the switch module 210 to logically connect the second processor complex 105b to the adapter card 110 as the owner processor complex in response to detecting the failure.
• the setup module 410 comprises a processor program product executing on the second processor complex 105b.
• the setup module 410 may communicate a specified binary values to the second port 205b of the adapter card 110.
• the specified binary values may direct the controller 230 to accept commands from a non-owner processor complex.
• the second processor complex 105b may then write binary values to the setup registers 235 that designate the processor complex 105 in communication with the second port 205b as the owner processor complex.
• the setup module 410 executing on the second processor complex 105b writes binary values to the setup registers 235 that cause the controller 230 to employ the second control store of the second memory module 240b.
• the setup module 410 may further re-initialize the adapter card 110 so that the controller 230 loads and executes the second control store.
• the setup module 410 comprises semiconductor logic and/or one or more processor program product executing on the processor of the controller 230.
• the setup module 410 may modify write binary values to the setup registers 235 that cause the switch module 210 to treat the processor complex 105 in communication with the second port 205b as the owner processor complex.
• the setup module 410 may communicate a message to the second processor complex 105b requesting that the second processor complex 105b assume the tasks of the owner processor complex.
• the setup module 410 may further logically disconnect the first processor complex 105 a from the adapter card 110 in response to detecting the failure.
• the setup module 410 writes a binary value to the setup registers 235 that causes the switch module 210 to stop receiving communications through the first port 205 a.
• the setup module 410 communicates a message to a system administrator requesting that the first processor complex 105 a be physically disconnected from the data processing system 100.
• the present invention supports rapid failover from the first to second processor complex 105b when the first processor complex 105a fails. As a result, one or more processor complexes 105 may continue to use the adapter card 110.
• FIG 6 is a schematic block diagram illustrating one embodiment of adapter card communications 600 of the present invention.
• the description of the communications 600 refers to elements of Figures 1-5, like numbers referring to like elements.
• the communications 600 include logical representations of the first processor complex 105 a, the second processor complex 105b, the adapter card 110, and the RAID subsystems 315.
• the communications 600 show the first processor complex 105a as the owner processor complex.
• the first processor complex 105 a communicates a discovery communication with one or more devices that are connected to the communication channel 120.
• the communication channel 120 is a PCIe bus
• the first processor complex 105 a communicates a discovery request to each device such as the adapter card 110 connected to the PCIe bus.
• the adapter card 110 may respond to the discovery request with an identification response that identifies the adapter card 110.
• the discovery request and identification response are shown as an owner communication 605.
• the switch module 210 only supports owner communication 605 between the owner processor complex first processor complex 605 and the adapter card 10.
• the first processor complex 105a may initialize the adapter card 110 and direct the adapter card 110 to communicate error messages, status messages, and the like to the first processor complex 105a.
• the first processor complex 105a may also communicate directly with the controller 230.
• the second processor complex 105b is unable to initialize the adapter card 110.
• the first processor complex 105b may also communicate discovery communications 610 through the adapter card 110 to devices such as the depicted RAID subsystems 315. Thus the first processor complex 105a may also initialize the RAID subsystems 315. In contrast, the second processor complex 105b sees the adapter card 110 as an end point. Thus the second processor complex 105b does not see or attempt to initialize devices such as the RAID subsystems 315.
• FIG. 7 is a schematic block diagram illustrating one alternate embodiment of adapter card communications 700 of the present invention.
• the communications 700 show the logical representations of the first processor complex 105a, the second processor complex 105b, the adapter card 110, and the RAID subsystems 115 of Figure 6.
• FIG. 8 is a schematic block diagram illustrating one embodiment of failover communications 800 of the present invention.
• the communications 800 show the logical representations of the first processor complex 105a, the second processor complex 105b, the adapter card 110, and the RAID subsystems 115 of Figure 7.
• the second processor complex 105b may communicate discovery communications 610 to the RAID subsystems 315.
• the setup module 410 modifies 540 the switch module 210 to logically disconnect the first processor module 110 from the adapter card 110.
• the first processor module 110 may communicate binary data such as random data to the adapter card 110, the adapter card 110 may not receive the communicated binary data.
• the embodiment of the present invention performs a failover from the first processor complex 105a that owns the adapter card 110 to the second processor complex 105b.
• the present invention preferably supports the continued use of the adapter card 110 when the first processor complex 105a fails.

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