WO2008128990A3 - Apparatus, system, and method for adapter card failover - Google Patents

Apparatus, system, and method for adapter card failover Download PDF

Info

Publication number
WO2008128990A3
WO2008128990A3 PCT/EP2008/054722 EP2008054722W WO2008128990A3 WO 2008128990 A3 WO2008128990 A3 WO 2008128990A3 EP 2008054722 W EP2008054722 W EP 2008054722W WO 2008128990 A3 WO2008128990 A3 WO 2008128990A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor complex
adapter card
port
owner
switch module
Prior art date
Application number
PCT/EP2008/054722
Other languages
French (fr)
Other versions
WO2008128990A2 (en
Inventor
Carol Spanel
Andrew Dale Walls
Cheng-Chung Song
Stephen Blinick
Original Assignee
Ibm
Ibm Uk
Carol Spanel
Andrew Dale Walls
Cheng-Chung Song
Stephen Blinick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/738,142 external-priority patent/US7870417B2/en
Priority claimed from US11/738,150 external-priority patent/US20080263391A1/en
Application filed by Ibm, Ibm Uk, Carol Spanel, Andrew Dale Walls, Cheng-Chung Song, Stephen Blinick filed Critical Ibm
Priority to CN200880012500.XA priority Critical patent/CN101663650B/en
Priority to KR1020097016914A priority patent/KR101143684B1/en
Priority to JP2010503518A priority patent/JP5322064B2/en
Priority to EP08736370A priority patent/EP2149089A2/en
Publication of WO2008128990A2 publication Critical patent/WO2008128990A2/en
Publication of WO2008128990A3 publication Critical patent/WO2008128990A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2033—Failover techniques switching over of hardware resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/25—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2046—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share persistent storage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)

Abstract

An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.
PCT/EP2008/054722 2007-04-20 2008-04-18 Apparatus, system, and method for adapter card failover WO2008128990A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200880012500.XA CN101663650B (en) 2007-04-20 2008-04-18 Apparatus, system, and method for adapter card failover
KR1020097016914A KR101143684B1 (en) 2007-04-20 2008-04-18 Apparatus, system, and method for adapter card failover
JP2010503518A JP5322064B2 (en) 2007-04-20 2008-04-18 Apparatus, system, method, and computer program for adapter card failover
EP08736370A EP2149089A2 (en) 2007-04-20 2008-04-18 Apparatus, system, and method for adapter card failover

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/738,142 US7870417B2 (en) 2007-04-20 2007-04-20 Apparatus, system, and method for adapter card failover
US11/738,150 2007-04-20
US11/738,150 US20080263391A1 (en) 2007-04-20 2007-04-20 Apparatus, System, and Method For Adapter Card Failover
US11/738,142 2007-04-20

Publications (2)

Publication Number Publication Date
WO2008128990A2 WO2008128990A2 (en) 2008-10-30
WO2008128990A3 true WO2008128990A3 (en) 2009-01-15

Family

ID=39769314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/054722 WO2008128990A2 (en) 2007-04-20 2008-04-18 Apparatus, system, and method for adapter card failover

Country Status (4)

Country Link
EP (1) EP2149089A2 (en)
JP (1) JP5322064B2 (en)
KR (1) KR101143684B1 (en)
WO (1) WO2008128990A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MX2012014575A (en) 2010-06-15 2013-02-07 Bayer Ip Gmbh Novel ortho-substituted aryl amide derivatives.
JP6455759B2 (en) * 2015-02-27 2019-01-23 サイレックス・テクノロジー株式会社 Device server, device usage method, and program,
US10296484B2 (en) 2015-12-01 2019-05-21 International Business Machines Corporation Dynamic re-allocation of computer bus lanes
US10102074B2 (en) 2015-12-01 2018-10-16 International Business Machines Corporation Switching allocation of computer bus lanes
KR101767181B1 (en) 2017-02-21 2017-08-22 한국과학기술정보연구원 Multipurpose PCIe Card and Method for Expanding Multipurpose PCIe Card

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040193737A1 (en) * 2003-03-31 2004-09-30 Huffman Amber D. Apparatus, method and system to couple one or more hosts to a storage device using unique signal from host
US6845467B1 (en) * 2001-02-13 2005-01-18 Cisco Systems Canada Co. System and method of operation of dual redundant controllers
EP1675006A2 (en) * 2004-12-21 2006-06-28 Nec Corporation Fault tolerant computer system and interrupt control method for the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3026350B2 (en) * 1990-07-11 2000-03-27 株式会社日立製作所 System switching method for a redundant system
JPH04205033A (en) * 1990-11-29 1992-07-27 Tamagawa Seiki Co Ltd Device control method by cpu
JP4459408B2 (en) * 2000-08-01 2010-04-28 ネクスコム インターナショナル カンパニー リミテッド Hot swap bus
JP2002202897A (en) * 2000-12-28 2002-07-19 Yokogawa Electric Corp Switching device
US6931568B2 (en) * 2002-03-29 2005-08-16 International Business Machines Corporation Fail-over control in a computer system having redundant service processors
US7058738B2 (en) * 2004-04-28 2006-06-06 Microsoft Corporation Configurable PCI express switch which allows multiple CPUs to be connected to multiple I/O devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6845467B1 (en) * 2001-02-13 2005-01-18 Cisco Systems Canada Co. System and method of operation of dual redundant controllers
US20040193737A1 (en) * 2003-03-31 2004-09-30 Huffman Amber D. Apparatus, method and system to couple one or more hosts to a storage device using unique signal from host
EP1675006A2 (en) * 2004-12-21 2006-06-28 Nec Corporation Fault tolerant computer system and interrupt control method for the same

Also Published As

Publication number Publication date
KR20090130850A (en) 2009-12-24
KR101143684B1 (en) 2012-05-09
WO2008128990A2 (en) 2008-10-30
EP2149089A2 (en) 2010-02-03
JP2010533900A (en) 2010-10-28
JP5322064B2 (en) 2013-10-23

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