EP2033219A1 - Boîtier de puissance pour puces à semi-conducteur et configuration dudit boîtier pour la dissipation de chaleur - Google Patents

Boîtier de puissance pour puces à semi-conducteur et configuration dudit boîtier pour la dissipation de chaleur

Info

Publication number
EP2033219A1
EP2033219A1 EP06804809A EP06804809A EP2033219A1 EP 2033219 A1 EP2033219 A1 EP 2033219A1 EP 06804809 A EP06804809 A EP 06804809A EP 06804809 A EP06804809 A EP 06804809A EP 2033219 A1 EP2033219 A1 EP 2033219A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor chips
housing
chip carrier
heat dissipation
carrier substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06804809A
Other languages
German (de)
English (en)
Inventor
Egbert Freiberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Creative Led GmbH
Original Assignee
Creative Led GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Creative Led GmbH filed Critical Creative Led GmbH
Publication of EP2033219A1 publication Critical patent/EP2033219A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink

Definitions

  • the invention relates to an auto-mountable surface-mount power housing for semiconductor chips and their arrangement for heat dissipation in conjunction with a wiring substrate and a cooling medium with optimized high heat dissipation when using one or more semiconductor chips, for example radiation-emitting devices with the same and mixed, arbitrary wavelength in a housing and any internal interconnection, which make a high current load and the removal of the associated heat generation necessary.
  • Another known disadvantage is that all previously known housing, which can derive a higher power dissipation, can not be used for use in conjunction with flexible circuit boards.
  • Another known disadvantage is that no multi-layer wiring levels can be applied, which leads to a reduction in the compactness of the devices and the associated disadvantages of an application.
  • the object of the present invention is to make the design for power housing for semiconductor chips so that on the one hand the number of thermal resistances is reduced and on the other hand, the electrical connection capability of the component independent of any cooling media use of the existing soldering technology for the electrical connection and, if necessary, also for the mechanical and thermal connection with the cooling medium and an unrestricted use in conjunction with flexible Wiring carriers, for example, in flexible printed circuit boards, with full potential freedom is possible.
  • the solution of the problem is achieved according to the invention that is omitted for mounting the formative of the prior art placement of the component housing on the wiring medium, for example, a circuit board, which is connected by heat resistance to the cooling medium constructive.
  • the wiring medium from the chain of thermal transitions is completely removed and the thermal coupling can be done directly with the cooling medium, the electrical connection via the wiring medium, which just not applied in the prior art solid connection with the cooling medium has, for example, metal core board, but continues to be so that the assembly can be done with the power housing for semiconductor chips according to the known rules of soldering and the arrangement for heat dissipation by applying the built in the wiring medium power housing for semiconductor chips is formed on the cooling medium.
  • the power housing for semiconductor chips must be constructed so that on the one hand take place the direct contact with the cooling medium and at the same time the electrical connection can be constructively self-sufficient and executed independently.
  • the invention is explained symbolically and by way of example closer.
  • FIG. 4 shows an example embodiment of the isolated chip metallization of the power housing for semiconductor chips with self-aligning position positioning or different polarity
  • the direct thermal coupling is effected according to the invention in that the wiring carrier (14) contains an opening (21) adapted to the chip carrier substrate (12), whereby only the chip carrier substrate (12) is inserted, which is electrically conductively connected to the housing carrier substrate (13) Connected sides and at the same time realized the mechanical connection.
  • Housing support substrate (13) and chip carrier substrate (12) form the structural unit of the housing, which is part of the overall arrangement according to the invention for heat dissipation with the other components cooling medium (15) and wiring substrate (14).
  • the chip carrier substrate (12) thus allows the direct connection assembly with the cooling medium (15) via a townleititatismaterial (16) without thermally intermediate wiring carrier (14) for electrical connection of the device.
  • the chip carrier substrate (12) consists of conductor tracks structured ceramic material or silicon or a constructive combination of the two. Typically, but not compulsorily, a metallized surface which is electrically insulated from the outside is provided in the center, the chip carrier metallization (23) for mounting the semiconductor chips (10). This Chipisme (23) is designed in such a way that the chips can be mounted by means of conventional conductive adhesive or fins.
  • the back surface of the chip carrier substrate (12) metallized executable and thus allows a soldering by means of lead-free solders on the cooling medium (15).
  • the top of the chip carrier substrate (12) with silicon dioxide applied as insulation and metallization applied thereto.
  • the housing support substrate (13) consists of ceramic or laminate materials with adapted thermal expansion coefficients to the chip carrier substrate (12).
  • the sauceleittellsmaterial (16) consists of any suitable for heat dissipation materials, for example, metallic solders when mounted by soldering or thermally conductive adhesives and pastes.
  • Design tolerances and assembly-related unevenness can be compensated for by means of self-adhesive or single-sided or double-sided self-adhesive halogen-free and lead-free politiciansleitucunsmaterialien (16) by means of conventional tools.
  • the electrical connection between the semiconductor chip (10) and the bonding wires (11) to the wiring level (25) on the wiring substrate (14) is achieved in that the chip carrier substrate (12) metallic over the wiring level of the housing support (20) with the opposite Genzouselect (13) via the wiring level for electrical connection the chip carrier substrate (22) is geometrically larger than the chip carrier substrate (12), in order to achieve that an electrical connection to the wiring carrier (14) for connecting the semiconductor chip (10) takes place to an external circuit.
  • the thickness of the chip carrier substrate is adapted to the thickness of the wiring substrate so that it terminates at least at the same level. Furthermore, the disadvantage in the soldering process is eliminated since the component housing can be connected to the wiring support (14) for connection of the component under existing technologically proven soldering processes including the standardized soldering times (soldering profiles).
  • the method of assembly is carried out by simply applying the fully assembled wiring substrate (14) after the soldering of inventively realized mecanicalden electronic components on the heat sink, optionally using a fixing material (24), which may also be thermally conductive.
  • a fixing material 24
  • the thermal connection can be improved by means of a heat-conducting connection material (16) underneath the chip carrier substrate (12).
  • a thermal connection on the surface of the wiring substrate (14) can be achieved by thermally bonding between the wiring plane of the wiring substrate (25) and the metallic connection plane (27) electrically insulated at the wiring plane of the housing support substrate (20) is, during the soldering process is connected with metallic.
  • the isolation of the individual wirings on the chip carrier substrate (12) and the housing support substrate (13) takes place horizontally via an insulating passivation (26), for example made of glass, according to FIG. 2, which simultaneously realizes a sealing of the overall arrangement.
  • an insulating passivation for example made of glass, according to FIG. 2, which simultaneously realizes a sealing of the overall arrangement.
  • the mechanical connection strength of the housing assembly of the two parts chip carrier substrate (12) and housing support substrate (13) by a combined or simultaneous sintering of the glass passivation (26) and the metallic wiring of conductive pastes on the chip carrier substrate (12) and the housing support substrate (13). be achieved.
  • the chip carrier substrate (12) and the housing support substrate (13) regardless of the materials used by a bonding process or soldering process by means of electrically conductive material, the wiring level of the chip carrier and the wiring level of the housing support are connected.
  • the protection of the semiconductor chips (10) and the bonding wires (11) is carried out by any potting materials based on epoxy or silicones with adapted thermal expansion coefficient. Also, a closure by gluing or soldering a lid is possible.
  • an optical encapsulation (17) is executed with level or curved shape according to the required optical properties in the emission opening (18).
  • the shape of the emission opening (18), which simultaneously allows the passage of the radiation, can be carried out in any manner and is subject exclusively to the technical requirements of the optical characteristics of the application.
  • the function of the wiring level of the housing carrier substrate (20) is reduced to the mechanical connection between chip carrier substrate (12) and housing carrier substrate (13), wherein the electrical connection now directly between the wiring level of the chip carrier substrate (22) and the wiring level (25) of the wiring substrate ( 14) can take place.
  • the chip carrier substrate (12) On the chip carrier substrate (12) is a metallized surface for mounting the half-chips (10) by means of conventional bonding method by using adhesive Leitmaterialien. If a eutectic chip bonding is to be carried out, the metallization of the chip carrier metallization (23) is structured as a function of the chip size in partial areas of the chip carrier metallization (28) in order to reduce or avoid floating effects. This structuring is carried out in such a way that the semiconductor chips (10) are self-aligned using the surface tension of the liquid solder.
  • FIG. 4 shows the detailed structure of an isolated chip carrier metallization (23) of the chip carrier substrate (12) for receiving the semiconductor chips (10) in partial areas of the chip carrier metallization (28).
  • the dimensions of the individual semiconductor chips (10) plus a border gives the size of a partial area of the chip carrier metallization (28), which can be arbitrarily configured in arrangement and number.
  • Connected are the partial surfaces of the Chipangometallmaschine (28) with electrically conductive connecting webs and small bonding surfaces (29), which are necessary for bilaterally to be contacted semiconductor chips (10), in one-sided components to be contacted, this part and the web omitted if the contact of the Upper side takes place.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Boîtier de puissance (1) pouvant être monté en surface pour puces à semi-conducteur (10) et configuration dudit boîtier pour la dissipation de chaleur par transfert à des milieux de refroidissement (15), dans des composants à haute puissance, par réduction des résistances thermiques conditionnées par la structure et situées en rangée. Ledit boîtier de puissance est ainsi conçu que la face inférieure peut être directement connectée au corps de refroidissement (15) par une ouverture (21) ménagée dans le plan de câblage (25), et que le plan de câblage nécessaire n'est pas intégré. Ledit boîtier est composé d'un substrat de support (12) de puce et d'un substrat de support (13) de boîtier qui sont pourvus de connexions électriques en vue de l'établissement du contact entre les puces à semi-conducteur (10) et le plan de câblage (25). Ce boîtier de puissance est constitué de préférence de matières céramiques ou de silicium.
EP06804809A 2005-10-20 2006-10-17 Boîtier de puissance pour puces à semi-conducteur et configuration dudit boîtier pour la dissipation de chaleur Withdrawn EP2033219A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH16852005 2005-10-20
PCT/CH2006/000574 WO2007045112A1 (fr) 2005-10-20 2006-10-17 Boîtier de puissance pour puces à semi-conducteur et configuration dudit boîtier pour la dissipation de chaleur

Publications (1)

Publication Number Publication Date
EP2033219A1 true EP2033219A1 (fr) 2009-03-11

Family

ID=37563760

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06804809A Withdrawn EP2033219A1 (fr) 2005-10-20 2006-10-17 Boîtier de puissance pour puces à semi-conducteur et configuration dudit boîtier pour la dissipation de chaleur

Country Status (3)

Country Link
EP (1) EP2033219A1 (fr)
TW (1) TW200729437A (fr)
WO (1) WO2007045112A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8652860B2 (en) 2011-01-09 2014-02-18 Bridgelux, Inc. Packaging photon building blocks having only top side connections in a molded interconnect structure
US8354684B2 (en) 2011-01-09 2013-01-15 Bridgelux, Inc. Packaging photon building blocks having only top side connections in an interconnect structure
EP3340293A1 (fr) * 2016-12-20 2018-06-27 Siemens Aktiengesellschaft Module à semi-conducteurs comprenant une structure de support sur la face inférieure
DE102018208256A1 (de) * 2018-05-25 2019-11-28 Volkswagen Aktiengesellschaft Leistungsbauteil und Verfahren zum Herstellen desselben
CN109671812A (zh) * 2018-12-25 2019-04-23 江苏罗化新材料有限公司 一种散热型芯片级led封装方法及其封装结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378247A (ja) * 1989-08-22 1991-04-03 Oki Electric Ind Co Ltd 半導体チップ放熱実装構造
JP2541494B2 (ja) * 1993-12-15 1996-10-09 日本電気株式会社 半導体装置
WO2001073843A1 (fr) * 2000-03-29 2001-10-04 Rohm Co., Ltd. Dispositif semi-conducteur
DE10117889A1 (de) 2001-04-10 2002-10-24 Osram Opto Semiconductors Gmbh Leiterrahmen und Gehäuse für ein strahlungsemittierendes Bauelement, strahlungsemittierendes Bauelement sowie Verfahren zu dessen Herstellung
US20040226688A1 (en) * 2003-04-30 2004-11-18 Arthur Fong Application specific apparatus for dissipating heat from multiple electronic components

Also Published As

Publication number Publication date
WO2007045112A1 (fr) 2007-04-26
TW200729437A (en) 2007-08-01

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