EP1988466A1 - Dispositif de memoire cache et procede de controle de memoire cache - Google Patents

Dispositif de memoire cache et procede de controle de memoire cache Download PDF

Info

Publication number
EP1988466A1
EP1988466A1 EP06714614A EP06714614A EP1988466A1 EP 1988466 A1 EP1988466 A1 EP 1988466A1 EP 06714614 A EP06714614 A EP 06714614A EP 06714614 A EP06714614 A EP 06714614A EP 1988466 A1 EP1988466 A1 EP 1988466A1
Authority
EP
European Patent Office
Prior art keywords
data
unit
address
tag information
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06714614A
Other languages
German (de)
English (en)
Other versions
EP1988466A4 (fr
Inventor
Takashi Miura
Naohiro Kiyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP1988466A1 publication Critical patent/EP1988466A1/fr
Publication of EP1988466A4 publication Critical patent/EP1988466A4/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Definitions

  • the present invention relates to a cache memory device which includes a cache that stores data and tag information indicating an address specifying stored data and to a cache memory control method thereof, and in particular, to a cache memory device that is capable of preventing an error of tag information at a time of a replace process, and protecting a system from damage, and to a cache memory control method thereof.
  • a cache memory installed inside a processor such as a CPU provides a high-speed access but has smaller storage capacity than a main memory.
  • the cache memory cannot store all data stored in the main memory, and stores only a part of data stored in the main memory. Therefore, in order to allow for search on data of which address in the main memory is stored (cached) in the cache memory, the cache memory stores data and tag information indicating an address in the main memory.
  • tag information is read out from the cache memory and a search is conducted to find whether desired data is cached in the cache memory or not.
  • error detection is sometimes performed with the use of a parity bit added to the tag information.
  • the error detection may utilize an ECC (Error Correcting Code) and the like instead of the parity bit as described in Patent Document 1. Further, it is described in Patent Document 1 that, based on a ratio of main memory capacity to cache memory capacity, error detection in tag information is performed with the use of a parity bit or an ECC for improved reliability.
  • ECC Error Correcting Code
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2000-20397
  • the tag information is searched and it is checked whether desired data is stored in the cache memory or not. As a result, if the desired data is not stored in the cache memory (cache miss), a replace process is performed in which data currently stored in the cache memory is replaced by the desired data stored in a main memory or an upper cache memory (i.e., secondary cache or the like).
  • tag information is read out again from the cache memory and data to be replaced by the desired data is decided.
  • data to be replaced is decided, the data and tag information corresponding to the data are temporarily stored in a save-buffer, and the main memory or the upper cache memory is requested to replace data of an address indicated by the tag information with the desired data.
  • the replace process is performed under the assumption that the tag information read out from the cache memory is correct.
  • the tag information does not have an error at the time of the readout and writing processes, if an error occurs during the readout process of tag information at a time of the replace process, significant damage can be caused on a system.
  • the present invention is made in view of the above and it is an object of the present invention to provide a cache memory device and a cache memory control method which can prevent a tag information error at a time of a replace process and protect a system from damage.
  • the present invention is a cache memory device that includes a cache which stores data and tag information specifying an address of stored data, and includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit.
  • the memory unit includes a selection unit that selects an address of data least recently accessed from a plurality of addresses contained in the tag information, and the memory unit stores the address selected by the selection unit.
  • control unit reads out and invalidates data corresponding to an address stored by the memory unit.
  • control unit reads out data corresponding to an address stored by the memory unit, and transfers the data to an external unit.
  • control unit compares an address of data to be processed with the address stored by the memory unit and cancels the process if the addresses are identical.
  • the present invention in an aspect of the present invention above, further includes an acquiring unit that acquires tag information where an error is detected and data corresponding to the tag information from an external unit when an error is detected in the tag information as a result of error detection by the detection unit, and a writing unit that writes tag information and data acquired by the acquiring unit, in the cache.
  • the present invention in an aspect of the present invention above, further includes a writing/readout unit that performs writing/readout of desired data stored in the cache when an address of desired data is contained in the tag information as a result of search by the search unit.
  • the present invention is a cache memory control method that controls a cache which stores data and tag information specifying an address of stored data, and includes a detection step of detecting an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search step of searching the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection in the detection step, a storing process of storing an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search in the search step, and a requesting step of requesting an external unit to replace data with a use of the address stored in the storing step.
  • tag information is read out and an error therein is detected.
  • the tag information is searched for an address of the desired data.
  • an address of data to be replaced by the desired data is stored, and data replacement is requested to an external unit with the use of the stored addresses.
  • the addresses used in the data replacement that is, in the replace process are based on the tag information where no error is detected, whereby correctness of the tag information is guaranteed, a tag information error in the replace process is prevented, and as a result, a system is protected from damage.
  • data corresponding to a stored address is read out from the cache and invalidated, whereby data to be replaced is invalidated and cache capacity is secured, and the desired data can be newly stored in the cache.
  • data to be replaced can be transferred, for example, to the secondary cache or the main memory and cache capacity is secured, whereby the desired data can be newly stored in the cache.
  • an address of data for the process is compared with a stored address, and the process is cancelled if both of the addresses are identical. Therefore, even if a storage process, for example, is requested on data that is to be invalidated or transferred as data to be replaced, the process is not executed in vain.
  • the tag information where the error is detected and data corresponding to the tag information are acquired from an external unit, and the acquired tag information and data are written into the cache. Therefore, the tag information is updated and an error reoccurrence is prevented.
  • a writing/readout of data is immediately performed if the desired data is stored in the cache, that is, if a cache hit occurs.
  • FIG. 1 is a block diagram of an overall configuration of a CPU including a cache memory device according to the embodiment of the present invention.
  • the CPU shown in FIG. 1 includes a primary cache control unit 100, a primary cache 200, a secondary cache control unit 300, a secondary cache 400, a command processing unit 500, and an operation processing unit 600. Further, the CPU is connected to a main memory 700.
  • the primary cache control unit 100 performs readout and writing of data from/to the primary cache 200 according to a command from the command processing unit 500. Further, when desired data is not stored at a time of readout of data from the primary cache 200, the primary cache control unit 100 sends a replace request to the secondary cache control unit 300. At this time, the primary cache control unit 100 keeps tag information where an error has been detected at the time of readout of data from the primary cache 200, and performs a replace process based on the tag information. Specific operations of the primary cache control unit 100 are described in detail later.
  • the primary cache 200 stores therein frequently used data in the secondary cache 400 and the main memory 700, and also stores tag information indicating an address in the main memory 700 of stored data.
  • the primary cache 200 adopts a set-associative scheme where a plurality of cache lines correspond to each predetermined memory block in the main memory 700. Cache lines corresponding to an identical memory block are referred to below as a way.
  • the secondary cache control unit 300 performs readout and writing of data from/to the secondary cache 400 based on a replace request from the primary cache control unit 100. Further, when error information indicating that an error is detected in tag information is output from the primary cache control unit 100, the secondary cache control unit 300 refers to a copy of tag information in the primary cache 200, reads out tag information where an error has occurred and data corresponding to the tag information from the secondary cache 400, and outputs the data and the tag information to the primary cache control unit 100.
  • the secondary cache 400 stores frequently used data of the main memory 700 and stores tag information of stored data and a copy of tag information of the primary cache 200.
  • the command processing unit 500 interprets a command such as a program, instructs the operation processing unit 600 to perform a necessary operation process, and instructs the primary cache control unit 100 to perform readout and writing of necessary data.
  • the operation processing unit 600 performs an operation process with data read out from the primary cache 200 and the like, according to an instruction from the command processing unit 500.
  • the main memory 700 is a main memory device which stores data and programs needed for CPU processes.
  • the main memory 700 provides a greater capacity and a lower-speed access than the primary cache 200 and the secondary cache 400.
  • FIG. 2 is a block diagram of a configuration of main parts of the primary cache control unit 100 and the primary cache 200 according to the present embodiment.
  • the primary cache control unit 100 includes a connection unit 101, a readout instruction unit 102, a writing/readout unit 103, an error detection unit 104, an error notification unit 105, a tag/data acquiring unit 106, a search unit 107, a way selection unit 108, a replace control unit 109, an address memory unit 110, and a data memory unit 111.
  • the primary cache 200 includes a tag RAM 201 and a data RAM 202.
  • connection unit 101 which is connected with the command processing unit 500, notifies the readout instruction unit 102 of a data readout command from the command processing unit 500, and outputs data read out from the primary cache 200 to the command processing unit 500.
  • the readout instruction unit 102 gives an instruction notifying the writing/readout unit 103 of an address of data to read out when a data readout command is issued from the command processing unit 500.
  • the writing/readout unit 103 When an instruction notifying of an address is given by the readout instruction unit 102, the writing/readout unit 103 reads out tag information corresponding to the address from the tag RAM 201, and outputs the tag information to the error detection unit 104. Further, when the writing/readout unit 103 is notified of a cache hit by the search unit 107, the writing/readout unit 103 reads out data corresponding to the address of the instruction of the readout instruction unit 102 from the data RAM 202, and outputs the data to the command processing unit 500 via the connection unit 101. Further, the writing/readout unit 103 writes tag information and data which are output from the tag/data acquiring unit 106 respectively in the tag RAM 201 and the data RAM 202. Further, the writing/readout unit 103 reads out data from the data RAM 202 based on control of the replace control unit 109.
  • the error detection unit 104 performs error detection in tag information that is output from the writing/readout unit 103. To be specific, the error detection unit 104 performs error detection with the use of a parity bit added to tag information. If an error is detected in the tag information, the error detection unit 104 notifies the error notification unit 105 of the error. If an error is not detected in the tag information, the error detection unit 104 notifies the search unit 107 of it and the tag information.
  • the error notification unit 105 When an error is detected in the tag information, the error notification unit 105 outputs to the secondary cache control unit 300 error information that can specify the tag information where the error is detected, in order to update the tag information and data corresponding to the tag information.
  • the tag/data acquiring unit 106 acquires tag information and data which are output from the secondary cache control unit 300, and instructs the writing/readout unit 103 to write the acquired tag information and data into the primary cache 200.
  • the search unit 107 searches the tag information for an address, for which the readout instruction unit 102 instructs the writing/readout unit 103 to perform readout.
  • the tag information read out by the writing/readout unit 103 includes information of a plurality of ways corresponding to a same memory block, and thus includes data addresses which differ from way to way. Therefore, search of the tag information is needed to determine whether desired data is stored in the primary cache 200. As a result of the search, if an address of data to be read out is contained in the tag information, the case is a cache hit. If an address of data to be read out is not contained in the tag information, the case is a cache miss.
  • the search unit 107 notifies the writing/readout unit 103 of the cache hit to let the data read out from the data RAM 202 in the primary cache 200.
  • the search unit 107 outputs the tag information to the way selection unit 108 and notifies the replace control unit 109 of the cache miss.
  • the way selection unit 108 selects a recently least frequently used way from the tag information based on LRU (Least Recently Used) control, and outputs an address of data stored in the selected way to the address memory unit 110.
  • LRU Location Recently Used
  • the replace control unit 109 On a cache miss, the replace control unit 109 starts a replace process that replaces data stored in the data RAM 202 in the primary cache 200 with desired data stored in the secondary cache 400 or in the main memory 700. To be specific, when the replace control unit 109 is notified of a cache miss by the search unit 107, the replace control unit 109 reads out an address from the address memory unit 110, and outputs a replace request that requests for replacement of data of the readout address with desired data, to the secondary cache control unit 300.
  • the replace control unit 109 instructs the writing/readout unit 103 to read out data of an address stored in the address memory unit 110 from the data RAM 202. Then, the replace control unit 109 outputs the data read out by the writing/readout unit 103 to the data memory unit 111.
  • the address memory unit 110 stores an address of data to be replaced by the desired data, the address being output from the way selection unit 108. It can be guaranteed that the stored address does not contain an error because the address memory unit 110 stores an address stored in a way which is selected from tag information where no error is detected as a result of error detection by the error detection unit 104.
  • the data memory unit 111 stores data that is output from the replace control unit 109 and is to be replaced by desired data. Further, although not shown in FIG. 2 , the address memory unit 110 and the data memory unit 111 invalidate the stored address and data when an invalidation request on data to be replaced is sent from the secondary cache control unit 300.
  • the tag RAM 201 stores tag information indicating an address in the main memory 700 of data stored in the primary cache 200.
  • the data RAM 202 stores data corresponding to an address stored in the tag RAM 201.
  • the primary cache 200 adopts a set-associative scheme. Therefore, the tag RAM 201 and the data RAM 202 have, for example, a set of a plurality of ways 0 to n as shown in FIG. 3 corresponding to each memory block in the main memory 700. Each way in the tag RAM 201 stores an address of data stored in the data RAM 202 in the corresponding memory block. Each way in the data RAM 202 stores data itself in the corresponding memory block.
  • a valid bit V that indicates whether the set is valid or not
  • a system absolute address Adrs that corresponds to data or an address stored in each way
  • a parity bit P for an error detection in the valid bit V and the system absolute address Adrs are added.
  • the command processing unit 500 issues a readout command to read out desired data from the primary cache 200, and the same reaches the connection unit 101 in the primary cache control unit 100 (Step S101). Then, the connection unit 101 outputs the readout command to the readout instruction unit 102, the readout instruction unit 102 notifies the writing/readout unit 103 of an address of desired data included in the readout instruction, and the writing/readout unit 103 reads out tag information corresponding to the address of the notification from the tag RAM 201 in the primary cache 200 (Step S102).
  • the readout tag information is output to the error detection unit 104.
  • the error detection unit 104 utilizes a parity bit of the tag information and performs error detection of the tag information (Step S103). If an error is detected in the tag information as a result of the error detection (Step S103 Yes), the error notification unit 105 outputs error information to the secondary cache control unit 300 (Step S104). Then, the secondary cache control unit 300 refers to a copy of tag information in the primary cache 200, reads out data and tag information corresponding to the tag information where an error is detected based on the error information, and outputs the data and the tag information to the primary cache control unit 100. These data and tag information are acquired by the tag/data acquiring unit 106 in the primary cache control unit 100.
  • the writing/readout unit 103 is instructed to write the data and the tag information respectively into the data RAM 202 and the tag RAM 201. Then, the writing/readout unit 103 writes the data and the tag information which contain no error respectively into the data RAM 202 and the tag RAM 201, and the tag RAM 201 is updated (Step S105).
  • Step S103 No if an error is not detected in the tag information as a result of the error detection in the tag information (Step S103 No), the tag information is output to the search unit 107, and the search unit 107 searches the tag information to determine whether the desired data is registered in the tag information or not (Step S106). As a result, if the desired data is registered in the tag information and a cache hit occurs (Step S106 Yes), a data readout process is performed since the data corresponding to the readout command from the command processing unit 500 is stored in the data RAM 202 (Step S107). That is, the search unit 107 instructs the writing/readout unit 103 to read out the desired data, the writing/readout unit 103 reads out the desired data from the data RAM 202 and outputs the data to the command processing unit 500 via the connection unit 101.
  • Step S106 No If the desired data is not registered in the tag information and a cache miss occurs as a result of the search of the tag information by the search unit 107 (Step S106 No), the tag information is output to the way selection unit 108 and the replace control unit 109 is notified of the cache miss. Then the way selection unit 108 selects a least recently used way from a plurality of ways in the tag information (i.e., LRU control is performed). The way is least frequently accessed recently, and thus becomes a way to be replaced by the desired data to be accessed this time. Therefore, an address stored in the way selected by the way selection unit 108 is stored in the address memory unit 110 (Step S108). Here, the address stored in the address memory unit 110 is acquired from tag information where no error is detected as a result of error detection by the error detection unit 104. Hence, the address is guaranteed to be correct.
  • the replace control unit 109 that is notified of the cache miss reads out an address stored in the address memory unit 110, and sends to the secondary cache control unit 300 a replace request that requests replacing, in the primary cache 200, data of the readout address with the desired data (Step S109).
  • the replace control unit 109 instructs the writing/readout unit 103 to read out data of the address read out from the address memory unit 110, and the data is read out from the data RAM 202 by the writing/reading unit 103 as data to be replaced (Step S110), then the data is output to the data memory unit 111 from the replace control unit 109, and is stored therein (Step S111).
  • the correctness of the address stored in the address memory unit 110 is guaranteed as described above.
  • LRU control can be used to determine which way to store the data to be replaced.
  • ways in the tag RAM 201 correspond to ways in the data RAM 202, the same way as the way in way selection for tag information is selected. As a result, a way that stores data of an address stored in the address memory unit 110 is selected.
  • the replace control unit 109 invalidates an address stored in the address memory unit 110 and data stored in the data memory unit 111 (Step S112), and stores the desired data and tag information which are output from the secondary cache control unit 300 respectively in the data RAM 202 and the tag RAM 201, and then the replace process is finished.
  • the secondary cache control unit 300 acquires the desired data from the main memory 700, and outputs the data to the primary cache control unit 100.
  • the replace control unit 109 may move out an address stored in the address memory unit 110 and data stored in the data memory unit 111 to the secondary cache control unit 300.
  • the present invention can be applied to prevent a tag information error at a time of a replace process, and to protect a system from damage.
EP06714614A 2006-02-24 2006-02-24 Dispositif de memoire cache et procede de controle de memoire cache Withdrawn EP1988466A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/303475 WO2007096998A1 (fr) 2006-02-24 2006-02-24 Dispositif de memoire cache et procede de controle de memoire cache

Publications (2)

Publication Number Publication Date
EP1988466A1 true EP1988466A1 (fr) 2008-11-05
EP1988466A4 EP1988466A4 (fr) 2009-12-23

Family

ID=38437060

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06714614A Withdrawn EP1988466A4 (fr) 2006-02-24 2006-02-24 Dispositif de memoire cache et procede de controle de memoire cache

Country Status (4)

Country Link
US (1) US20080320227A1 (fr)
EP (1) EP1988466A4 (fr)
JP (1) JPWO2007096998A1 (fr)
WO (1) WO2007096998A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160350229A1 (en) * 2014-12-14 2016-12-01 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
US9798668B2 (en) 2014-12-14 2017-10-24 Via Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
US10719434B2 (en) 2014-12-14 2020-07-21 Via Alliance Semiconductors Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013084314A1 (fr) * 2011-12-07 2013-06-13 富士通株式会社 Unité de traitement et procédé de commande d'unité de traitement
EP2790107A1 (fr) * 2011-12-07 2014-10-15 Fujitsu Limited Unité de traitement et procédé de commande d'unité de traitement
CN108847263B (zh) * 2013-10-23 2021-03-23 钰创科技股份有限公司 具有嵌入式内存的系统级封装内存模块
US9946469B2 (en) * 2016-03-21 2018-04-17 Smart Modular Technologies, Inc. Solid state storage system with latency management mechanism and method of operation thereof
US11237972B2 (en) * 2017-12-29 2022-02-01 Advanced Micro Devices, Inc. Method and apparatus for controlling cache line storage in cache memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693163A (en) * 1979-12-25 1981-07-28 Fujitsu Ltd Buffer access control system
JPS60189553A (ja) * 1984-03-09 1985-09-27 Hitachi Ltd バッファメモリ制御方法
JPH05165719A (ja) * 1991-12-18 1993-07-02 Nec Eng Ltd メモリアクセス処理装置
JP3483296B2 (ja) * 1994-04-28 2004-01-06 富士通株式会社 情報処理装置
JP2000020397A (ja) 1998-07-03 2000-01-21 Pfu Ltd キャッシュメモリ制御装置
US6792568B2 (en) * 2001-07-31 2004-09-14 Hewlett Packard Development Co. Lp Data transfer and storage device and method
JP4673584B2 (ja) * 2004-07-29 2011-04-20 富士通株式会社 キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
No further relevant documents disclosed *
See also references of WO2007096998A1 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160350229A1 (en) * 2014-12-14 2016-12-01 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
US9798668B2 (en) 2014-12-14 2017-10-24 Via Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
US10698827B2 (en) * 2014-12-14 2020-06-30 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
US10719434B2 (en) 2014-12-14 2020-07-21 Via Alliance Semiconductors Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode

Also Published As

Publication number Publication date
WO2007096998A1 (fr) 2007-08-30
JPWO2007096998A1 (ja) 2009-07-09
EP1988466A4 (fr) 2009-12-23
US20080320227A1 (en) 2008-12-25

Similar Documents

Publication Publication Date Title
EP1988466A1 (fr) Dispositif de memoire cache et procede de controle de memoire cache
EP0118828B1 (fr) Dispositif de lecture d'instructions et méthode d'opération
US7958318B2 (en) Coherency maintaining device and coherency maintaining method
EP1622007B1 (fr) Dispositif de traitement des informations et procédé de commandement de pré-lecture logiciel
KR101483931B1 (ko) 캐시 로킹 디바이스 및 그 방법들
US7159076B2 (en) Cache operation with non-cache memory
RU2397534C2 (ru) Эффективное управление иерархией памяти
JP5526626B2 (ja) 演算処理装置およびアドレス変換方法
EP1622028B1 (fr) Antémémoire et procédé de commande d'une antémémoire
US10545879B2 (en) Apparatus and method for handling access requests
JPH07295886A (ja) 階層メモリ、階層メモリを有するコンピュータ・システムおよび階層メモリ管理方法
US7461212B2 (en) Non-inclusive cache system with simple control operation
US20090292857A1 (en) Cache memory unit
EP0498520B1 (fr) Antémémoire de données et procédé de traitement d'erreurs de mémoire pendant réécriture
JPH05324468A (ja) 階層化キャッシュメモリ
US20110072216A1 (en) Memory control device and memory control method
US20080313409A1 (en) Separating device and separating method
US20110283041A1 (en) Cache memory and control method thereof
US9075732B2 (en) Data caching method
CN117331853B (zh) 缓存处理方法、装置、电子设备及介质
US20020010837A1 (en) Cache memory system and method of controlling cache memory
EP0128353A2 (fr) Recouvrement d'erreur dans une antémémoire non inscriptible au travers
JPH04363738A (ja) キャッシュメモリ装置
JPS6310461B2 (fr)
JPH04127341A (ja) バッファメモリのエラー処理方式

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080901

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

A4 Supplementary search report drawn up and despatched

Effective date: 20091123

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 11/14 20060101ALI20091117BHEP

Ipc: G06F 12/12 20060101ALI20091117BHEP

Ipc: G06F 12/08 20060101AFI20070925BHEP

18W Application withdrawn

Effective date: 20091124