JP5526626B2 - 演算処理装置およびアドレス変換方法 - Google Patents
演算処理装置およびアドレス変換方法 Download PDFInfo
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- JP5526626B2 JP5526626B2 JP2009156305A JP2009156305A JP5526626B2 JP 5526626 B2 JP5526626 B2 JP 5526626B2 JP 2009156305 A JP2009156305 A JP 2009156305A JP 2009156305 A JP2009156305 A JP 2009156305A JP 5526626 B2 JP5526626 B2 JP 5526626B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1012—Design facilitation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1056—Simplification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/68—Details of translation look-aside buffer [TLB]
- G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Description
2 メインメモリ
11 命令制御部
12 演算部
13 L1命令タグ
14 L1データタグ
15 L1命令キャッシュ
16 L1データキャッシュ
17 L2キャッシュ
20 アドレス変換バッファ
21 仮想アドレスレジスタ
22 コンテキストレジスタ
23,23a TLB本体部
24,24a,24b TLB検索部
25a,25b チェック部
26 グッドタグ部
27 グッドデータ部
28 ラッチ検索部
29 ラッチ
31,33,34 タグ部
32,35 データ部
41,42 比較回路
43 アンド回路
Claims (6)
- 仮想アドレスを物理アドレスに変換するアドレス変換対の一部をアドレス変換バッファに保持する演算処理装置であって、
前記アドレス変換バッファは、
セットアソシアティブ方式で参照する第1の領域と、エントリを順に比較するフルアソシアティブ方式で参照する第2の領域とを備えるランダムアクセスメモリである記憶部と、
前記仮想アドレスから前記物理アドレスへのアドレス変換を行う場合に、アドレス変換対象の仮想アドレスに対応するアドレス変換対を、前記第1の領域から検索し、前記第1の領域に前記アドレス変換対象の仮想アドレスに対応するアドレス変換対が存在しない場合に、前記第2の領域から前記アドレス変換対象の仮想アドレスに対応するアドレス変換対を検索する検索部と、
を備えたことを特徴とする演算処理装置。 - 前記演算処理装置において、
前記アドレス変換バッファは、複数の記憶部に前記第1の領域と第2の領域とを設け、前記第2の領域に対して検索を行なう場合に前記複数の記憶部に同時に検索を行なう事を特徴とする請求項1に記載の演算処理装置。 - 前記演算処理装置において、
前記複数の記憶部の第2の領域に前記アドレス変換対を二重化して登録し、前記複数の記憶部の第2の領域に対して検索の結果を検証する検証部と、前記検証の結果に基づいて前記複数の記憶部の第2の領域から各々得られた検索結果を選択する選択部と、をさらに備えたことを特徴とする請求項2に記載の演算処理装置。 - 前記演算処理装置において、
前記第2の領域に登録したアドレス変換対のうち一部を保持するラッチと、前記仮想アドレスから前記物理アドレスへのアドレス変換を行う場合に、前記アドレス変換対象の仮想アドレスに対応するアドレス変換対を前記ラッチから検索するラッチ検索部とをさらに備えたことを特徴とする請求項1〜3のいずれか一つに記載の演算処理装置。 - 前記演算処理装置において、
前記検索部は、前記第1の領域に前記アドレス変換対象の仮想アドレスに対応するアドレス変換対が存在せず、かつ前記アドレス変換が所定の条件を満たす場合に、前記第2の領域に対する検索を行なうことを特徴とする請求項1〜4のいずれか一つに記載の演算処理装置。 - 仮想アドレスを物理アドレスに変換するアドレス変換対の一部を記憶部にアドレス変換バッファとして保持する演算処理装置のアドレス変換方法であって、
前記仮想アドレスから前記物理アドレスへのアドレス変換を行う場合に、アドレス変換対象の仮想アドレスに対応するアドレス変換対を、ランダムアクセスメモリである前記記憶部に設けられた第1の領域から、セットアソシアティブ方式で検索する第1の検索ステップと、
前記アドレス変換対象の仮想アドレスに対応するアドレス変換対が前記第1の領域に存在しない場合に、前記アドレス変換対象の仮想アドレスに対応するアドレス変換対を、ランダムアクセスメモリである前記記憶部に設けられた第2の領域から、エントリを順に比較するフルアソシアティブ方式で検索する第2の検索ステップと、
を備えたことを特徴とするアドレス変換方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009156305A JP5526626B2 (ja) | 2009-06-30 | 2009-06-30 | 演算処理装置およびアドレス変換方法 |
US12/825,959 US8745356B2 (en) | 2009-06-30 | 2010-06-29 | Processor and address translating method |
EP10167869A EP2275939B1 (en) | 2009-06-30 | 2010-06-30 | Processor and address translating method |
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JP2009156305A JP5526626B2 (ja) | 2009-06-30 | 2009-06-30 | 演算処理装置およびアドレス変換方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011013858A JP2011013858A (ja) | 2011-01-20 |
JP5526626B2 true JP5526626B2 (ja) | 2014-06-18 |
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JP2009156305A Expired - Fee Related JP5526626B2 (ja) | 2009-06-30 | 2009-06-30 | 演算処理装置およびアドレス変換方法 |
Country Status (3)
Country | Link |
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US (1) | US8745356B2 (ja) |
EP (1) | EP2275939B1 (ja) |
JP (1) | JP5526626B2 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9343177B2 (en) * | 2013-02-01 | 2016-05-17 | Apple Inc. | Accessing control registers over a data bus |
US9823929B2 (en) * | 2013-03-15 | 2017-11-21 | Qualcomm Incorporated | Optimizing performance for context-dependent instructions |
US9645934B2 (en) * | 2013-09-13 | 2017-05-09 | Samsung Electronics Co., Ltd. | System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer |
US9836410B2 (en) | 2015-04-15 | 2017-12-05 | Qualcomm Incorporated | Burst translation look-aside buffer |
JP6592310B2 (ja) * | 2015-09-01 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10180909B2 (en) | 2016-07-18 | 2019-01-15 | International Business Machines Corporation | Host-based resetting of active use of guest page table indicators |
US10176110B2 (en) | 2016-07-18 | 2019-01-08 | International Business Machines Corporation | Marking storage keys to indicate memory used to back address translation structures |
US10223281B2 (en) | 2016-07-18 | 2019-03-05 | International Business Machines Corporation | Increasing the scope of local purges of structures associated with address translation |
US10802986B2 (en) | 2016-07-18 | 2020-10-13 | International Business Machines Corporation | Marking to indicate memory used to back address translation structures |
US10162764B2 (en) | 2016-07-18 | 2018-12-25 | International Business Machines Corporation | Marking page table/page status table entries to indicate memory used to back address translation structures |
US10241924B2 (en) | 2016-07-18 | 2019-03-26 | International Business Machines Corporation | Reducing over-purging of structures associated with address translation using an array of tags |
US10168902B2 (en) | 2016-07-18 | 2019-01-01 | International Business Machines Corporation | Reducing purging of structures associated with address translation |
US10248573B2 (en) | 2016-07-18 | 2019-04-02 | International Business Machines Corporation | Managing memory used to back address translation structures |
US10176006B2 (en) | 2016-07-18 | 2019-01-08 | International Business Machines Corporation | Delaying purging of structures associated with address translation |
US10176111B2 (en) | 2016-07-18 | 2019-01-08 | International Business Machines Corporation | Host page management using active guest page table indicators |
US10282305B2 (en) | 2016-07-18 | 2019-05-07 | International Business Machines Corporation | Selective purging of entries of structures associated with address translation in a virtualized environment |
US10169243B2 (en) | 2016-07-18 | 2019-01-01 | International Business Machines Corporation | Reducing over-purging of structures associated with address translation |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS576956A (en) | 1980-06-16 | 1982-01-13 | Hitachi Ltd | Information processor |
JPH0335336A (ja) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | アドレス変換バッファ機構 |
JPH03164845A (ja) * | 1989-11-22 | 1991-07-16 | Hitachi Ltd | アドレス変換バッファ方式 |
JP3229045B2 (ja) | 1992-12-22 | 2001-11-12 | 株式会社東芝 | アドレス変換バッファ機構 |
JPH08115262A (ja) | 1994-10-14 | 1996-05-07 | Hitachi Ltd | アドレス変換回路および該アドレス変換回路を具備する電子計算機 |
JP3922844B2 (ja) * | 1999-09-02 | 2007-05-30 | 富士通株式会社 | キャッシュtag制御方法及びこの制御方法を用いた情報処理装置 |
US6625715B1 (en) * | 1999-12-30 | 2003-09-23 | Intel Corporation | System and method for translation buffer accommodating multiple page sizes |
US6941442B2 (en) * | 2002-08-02 | 2005-09-06 | Arm Limited | Entry lockdown within a translation lookaside buffer mechanism |
US7017005B2 (en) * | 2002-08-28 | 2006-03-21 | Hywire Ltd. | Implementation of a content addressable memory using a RAM-cell structure |
US7117290B2 (en) | 2003-09-03 | 2006-10-03 | Advanced Micro Devices, Inc. | MicroTLB and micro tag for reducing power in a processor |
US7797509B2 (en) * | 2007-01-11 | 2010-09-14 | Netlogic Microsystems, Inc. | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure |
EP2159707A4 (en) * | 2007-06-20 | 2010-11-24 | Fujitsu Ltd | ARITHMETIC PROCESSING UNIT, INPUT TAX PROGRAM AND INPUT TAX PROCEDURE |
-
2009
- 2009-06-30 JP JP2009156305A patent/JP5526626B2/ja not_active Expired - Fee Related
-
2010
- 2010-06-29 US US12/825,959 patent/US8745356B2/en not_active Expired - Fee Related
- 2010-06-30 EP EP10167869A patent/EP2275939B1/en not_active Not-in-force
Also Published As
Publication number | Publication date |
---|---|
US8745356B2 (en) | 2014-06-03 |
US20100332790A1 (en) | 2010-12-30 |
EP2275939A1 (en) | 2011-01-19 |
EP2275939B1 (en) | 2012-08-22 |
JP2011013858A (ja) | 2011-01-20 |
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