Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
  • H05H1/00—Generating plasma; Handling plasma
  • H05H1/24—Generating plasma
  • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
  • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
  • H03H7/38—Impedance-matching networks
  • H03H7/40—Automatic matching of load impedance to source impedance

Definitions

• RF generators provide power to dynamic loads typically at frequencies between about 400 kHz and about 200 MHz. Frequencies used in some scientific, industrial and medical applications are approximately 2 MHz, 13.56 MHz and 27 MHz.
• one system 100 for providing RF power to dynamic loads involves a fixed frequency RF generator 110 and a two-axis tunable matching network 120 connected by a 50 ⁇ transmission line 130.
• the tunable matching network 120 includes a series motorized vacuum variable capacitor 122 and inductor 124 and a shunt motorized vacuum variable capacitor 126.
• the algorithm used to determine the series and shunt capacitance is based on impedance measurements typically made using a magnitude and phase detector 150.
• Independent power control is based on power measurements at the RF generator 110.
• the power control loop 160 and impedance control loop 162 are independent. As shown in FIG.
• another system 100' for providing RF power to dynamic loads involves a fixed element matching network 120' fed by an RF generator 110 and connected by a 50 ⁇ transmission line 130.
• the fixed element matching network 120' includes a series capacitor 122 and inductor 124 and a shunt capacitor 126.
• the frequency of the RF generator 110 can be tuned to a certain range (e.g., 13.56 MHz ⁇ 5%).
• the RF generator 110 frequency command is based on the value of voltage standing wave ratio (VSWR).
• the independent power loop and VSWR (impedance) control loop 160' are based on measurements at the output of the RF generator 110.
• another system 100" for providing RF power to dynamic loads involves an integrated RF generator-impedance matching network 120".
• the RF generator- impedance matching network 120" includes a series capacitor 122 and inductor 124 and a plurality of shunt capacitor 126a...126n.
• the shunt capacitor 126a...126n are coupled to a switching circuit 127a...127n that couples and decouples the capacitors 126 to ground.
• the power control and frequency control 160" of the system 100" are not conducted simultaneously.
• Plasma impedance is a function of the power delivered to the plasma. Furthermore, the power delivered by the RF generator is a function of the impedance "seen" by the generator. As
• the dynamic response of any controlled system is only as fast as the slowest functional module (sensor, actuator, or control system parameters).
• the slowest functional module is typically the DC power supply.
• the DC power supplied to the input of the RF power amplifier usually includes a large electrolytic capacitor that is used to filter higher frequencies.
• the downside of using such a filter network is that the dynamic
• the response time is on the order of hundreds of milliseconds. Owing to the fact that plasma transients (sudden and rapid change of impedance) of interest occur within hundreds of microseconds, the vacuum capacitor
• Impedance measurement-based matching control suffers from an inherent disadvantage. For example, a change in shunt capacitance to correct or modify the real component of the impedance results in an undesirable
• Calibration methods for prior art systems calibrate the RF impedance analyzer or VI probe at the input of the electronic matching network. These calibration methods assume the power loss in the electronic matching network is fixed for all states of the electronic matching network and operating frequencies. However, the losses of the electronic matching network contribute significantly to the overall system operation.
• the system includes a power supply providing DC power having a substantially constant power open loop response, a power amplifier for converting the DC power to RP power, a sensor for measuring voltage, current and phase angle between voltage and current vectors associated with the RP power, an 0 electrically controllable impedance matching system to modify the impedance of the power amplifier to at lease substantially match an impedance of a dynamic load, and a controller for controlling the electrically controllable impedance matching system.
• the system further includes a sensor calibration measuring module for determining power delivered by the power amplifier, an electronic matching system calibration module for determining power delivered to 5 a dynamic load, and a power dissipation module for calculating power dissipated in the electrically controllable impedance matching system.
• the electrically controllable impedance matching system can include an inductor, a capacitor in series with the inductor, and a plurality of switched capacitors in parallel with the dynamic load.
• the inductor can be a multiple tap-type inductor or a variable- '.0 type inductor.
• Each of the plurality of switched capacitors can be in series with a switch and an additional capacitor.
• the electrically controllable impedance matching system can include a capacitor, and a plurality of switched capacitors in parallel with the dynamic load, wherein each of the plurality of capacitors is in series with a switch and an additional capacitor.
• the electrically controllable impedance '.5 matching system can control the frequency of the impedance matching between the power amplifier and the dynamic load.
• the controller can control the electrically controllable impedance matching system for simultaneous control of conductance and susceptance associated with the impedance between the power amplifier and the dynamic load.
• the SO controller can simultaneously control RP power frequency, RF power magnitude and the impedance between the power amplifier and the dynamic load.
• the controller can control the electrically controllable impedance matching system for regulating conductance and susceptance to setpoints that stabilize an unstable dynamic load.
• the power dissipated in the electrically controllable impedance matching system is the difference between the power delivered by the power amplifier and the power delivered to the dynamic load.
• the power delivered to the dynamic load is a sum of the power delivered to a resistive load and the power dissipated inside the load simulator.
• the sensor calibration measuring module calibrates the sensor into a resistive load, wherein the resistive load is 50 ⁇ .
• the electronic matching module calibrates an output of the electrically controllable impedance matching system into a load simulator.
• the load simulator can be an inverse electrically controllable impedance matching system.
• the electronic matching system calibration module can include a power meter calibration module for determining power delivered to a resistive load; and a load simulator calibration module for determining power dissipated inside the load simulator.
• the resistive load can be 50 ⁇ .
• the radio frequency power delivery system provides at least the following advantages over prior art systems.
• the system can enhance power setpoint regulation, impedance matching, and load disturbance mitigation using high-speed (e.g., in excess of 50 kHz in one embodiment) digital multi-input-multi-output (MIMO) control.
• the system can operate in the presence of transient changes in plasma load properties and under conditions involving fast plasma stabilization.
• the system can provide a RF power delivery system that is robust to transients during startup of the system.
• the system can provide a high power step-up ratio, wherein the high power step-up ratio is 100 (e.g., 15W to 1500 W).
• the system can measure power delivered to the load connected to the output of the integrated generator system.
• the system can allow for regulation of power that is independent of the power loss variation associated with the state/value of various controlled variables.
• the system can eliminate the need for recipe-based calibration for plasma loads.
• FIG. IA is a diagram of an RF power delivery system having a two-axis tunable matching network according to the prior art
• FIG. IB is a diagram of an RF power delivery system having a fixed matching network according to the prior art
• FIG. 1C is a diagram of an RF power delivery system having an integrated RF generator- impedance matching network according to the prior art
• FIG. 2 is a module-based diagram of the On-Chamber RF power delivery system
• FIG. 3 is a plasma stability graph
• FIG. 4 is one embodiment of a fast DC bus of FIG. 2;
• FIG. 5 is one embodiment of an RF impedance analyzer or VI Probe of FIG. 2
• FIG. 6 is one embodiment of an electronic matching network of FIG. 2;
• FIG. 7 is one embodiment of a module-based diagram of a DSP compensator board of FIG. 2;
• FIG. 8 is a block diagram for calibrating the On-Chamber RF power delivery system;
• FIG. 9 A is one embodiment for calibrating a power meter to a 50 ⁇ calorimeter power reference
• FIG. 9B is one embodiment for calibrating a load simulator to a DC power reference
• FIG. 9C is one embodiment for calibrating an RF impedance analyzer into a 50 ⁇ load.
• FIG. 9D is one embodiment for calibrating power delivered into the load simulator.
• an integrated radio frequency (RF) power delivery system is provided for dynamic load applications (e.g., inductive and/or capacitive plasma load).
• Figure 2 is an illustration of the integrated radio frequency (RF) power delivery system 200.
• Representative functional modules of the integrated system 200 include a fast DC bus 210, an RF power amplifier ("PA”) 220, a digital signal processor ("DSP") compensator board 230, an RF impedance analyzer or VI probe 240, and an electronic matching network 250.
• the system 200 is coupled to a plasma load 260. It should be understood by one skilled in the art that the integrated system 200 can be implemented for a wide range of resistive and reactive loads.
• the fast DC bus 210 delivers DC power to the power amplifier 220.
• the power amplifier 220 converts the DC power from the fast DC bus 210 to an RF power at a frequency.
• the electronic matching system 250 switches shunt capacitors (not shown) to match the impedance between the power amplifier 220 and the plasma load 260 to facilitate stable and maximum power transfer from the power amplifier 220 to the plasma load 260.
• the DSP compensator board 230 controls the operation of the system 200 based on measurements received from the fast bus controller 212 and RF impedance analyzer 240.
• the RF impedance analyzer 240 measures the RMS voltage, RMS current, and phase angle between the RF voltage and current vectors. Based on these measurements, relevant RF parameters are computed by the DSP compensator board 230.
• Typical operations of the DSP compensator board include power setpoints through the fast bus controller 212, RF power frequency setpoints through the power amplifier driver 222, and switching frequency through the electronic match controller 252.
• the system 200 achieves simultaneous power and impedance regulation.
• Independent susceptance regulation allows for the implementation of a frequency control algorithm based only on the deviation of the conductance from the conductance setpoint.
• both control loops can be operated simultaneously and at high-speed resulting in improved robustness.
• well-known instabilities for electronegative plasmas at low- pressure e.g., SF6 at 5mT at 300W as illustrated in Figure 3
• FIG. 4 is a diagram of a partial resonant inverter power supply type fast DC bus 210.
• the fast DC bus 210 provides process stability due to its associated constant power open loop response.
• the fast DC bus 210 improves FET utilization over the entire load space which results in more power being delivered to the load with the same PA 220 (FIG. 2).
• the fast DC bus 210 has a fast response rate allowing it to deliver increased power to the plasma so it does not extinguish while also allowing the flexibility to reduce the bus voltage to ensure the FETs on the PA 220 operate in a safe mode.
• Other types of topologies can for the fast DC bus 210 can be used. See for example, co-pending continuation-in-part application it's parent U.S. Application Serial No. 10/947,397 filed September 22, 2004, the entire teaching of each application are herein incorporated by reference.
• the fast DC bus can be a partial resonant inverter 210 that includes a pair of switches (MOSFETs) 302a, 302b, an inductor (L) 306, a capacitor (C) 308, and four diodes 310a, 310b, 310c, and 310d.
• the partial resonant inverter 300 converts the input voltage into a square wave or other known type DC wave form. The square wave is passed through the inductor 306 and capacitor 308, the combination of which form an LC filter, clamped by the diodes 310c, 310d, coupled and rectified by a transformer rectifier 304 and filtered to obtain a desired DC voltage (power setpoint).
• the DC power setpoint is provided from the DSP compensator board 230 (FIG. 2).
• the desired impedance setpoint can be specified in terms of its vector inverse (referred to as admittance) and which constitutes simultaneous regulation of conductance to an arbitrary conductance setpoint and regulation of susceptance to an arbitrary susceptance setpoint.
• the output of the partial resonant inverter 300 (DC-DC converter) is connected to DC input of the RF power generator/amplifier 220.
• the capacitor 308 is periodically charged to an input rail voltage (+Vin) and discharged while the capacitor current is passed via the plasma load 260 (FIG.2). Every charge or discharge cycle, the energy deposited in the resistive load is equal to CV 1 12, independent of load resistance.
• the power is equal to F sw x CV 2 12, where F sw is the switching frequency and V is the input voltage.
• the inductor 306 ensures that the capacitor 308 is fully charged and discharged in finite time.
• One advantage of the partial resonant inverter 300 design is the ability to control the output voltage by varying either V or/and F sw .
• FIG. 5 is a diagram of one embodiment of an RF impedance analyzer or VI Probe 240.
• the VI Probe 240 includes a DC power supply 242, an analysis board assembly 244, and a probe head assembly 246.
• the analysis board assembly 244 receives low-level RF signals from the probe head assembly 246.
• the probe head assembly 246 provides two voltage outputs: 1) a voltage representation of the time varying electric field present in the probe head assembly 246 (voltage signal); and 2) a voltage representation of the time varying magnetic field present in the probe head assembly 246 (current signal).
• the analysis board assembly 244 receives and processes the two voltage outputs of the probe head assembly 246 and outputs the RF parameters to the DSP compensator board 230 (FIG.2).
• VI-Probe-4100 and VI- Probe-350 are exemplary analyzers that can be used for this purpose.
• FIG. 6 is a diagram of one embodiment of an electronic matching network 250.
• the electronic matching 250 includes an inductance 254 in series with the load 260 (e.g., a compact inductor with multiple tap points), a fixed or variable series-padding capacitor 252, and field effect transistors ("FET's") 256a...256n that switch one or more upper capacitors
• FET's field effect transistors
• the electronic matching 250 network does not include the inductance 254 in series with the load 260.
• Other types of electronic matching networks can be used. See for example, U.S. Patent No. 6,887,339, the entire teaching of which is herein incorporated by reference.
• FIG. 7 shows a module-based diagram of a DSP compensator board 230.
• the DSP compensator board 230 incorporates both a digital signal processor ("DSP") and a field programmable gate array (“FPGA”), and together controls the entire integrated system 200.
• the DSP compensator board includes an admittance compensation module 232, a frequency control module 234, an electronic match control module 236, an RF power computation module 237, and an RF power control module 238.
• the DSP compensator board receives the output from the VP probe 240.
• the admittance computation module 232 uses the VI probe
• the frequency control module 234 uses the admittance to vary the frequency of the power amplifier 220.
• the electronic match control module 236 uses the admittance to switch the FETs 256 of the electronic matching network 250 on or off.
• the RF power computation module 237 uses the VI probe outputs to calculate the RF power of the system 200.
• the RF power control module 234 uses the RF power computation to
• P P objective is to regulate the delivered power del to a user-defined setpoint sp .
• trajectory generators are used.
• a first-order trajectory is 5 generated as follows: f at "7 ⁇ ⁇ W ) -O EQN. 1 where ⁇ ' is the trajectory time constant and P ' is the desired power trajectory.
• the delivered-power control algorithm in terms of the change in power commanded to the Fast Bus, is given by the following relationship:
• Admittance regulation objective A normalized admittance vector is defined as follows: y ⁇ S + J b where g is the normalized conductance and b is the normalized susceptance.
• the impedance matching control objective is formulated as follows: s ⁇ sp and sp where s b 15 6sp and sp are arbitrary setpoints selected to improve plasma stability.
• the above objective is reinterpreted in terms of impedance by noting that impedance is defined as the reciprocal of admittance, according to the following relationship:
• the shunt capacitance control loop is designed by using conductance measurements, for example, as a PI control algorithm as follows:
• the VI probe 240 provides analog signals proportional to the RF voltage and RF current, which are synchronously sampled by the analog-to-digital converters, sent to a mixer and CIC filter (not shown) and ultimately sent through a calibration matrix to yield RF voltage and RF current measurements given by the following relationships:
• * > ⁇ * denote vector representations of the instantaneous RF voltage and current, respectively, and subscripts r and * are used to denote the scalar values of the real and imaginary components.
• the average delivered power is computed as follows:
• the admittance vector Y is then computed as follows:
• the normalized conductance g and normalized susceptance b are computed as follows: z g -- z Z 0 c(J - - zZ 0 &K 2 + W 2 ) b b -- Z Z oB ⁇ -- Z Z o ( I tK 2 -W 2 )
• the electronic match controller 252 switches the FETs 256 (Fig. 6) thereby switching the shunt capacitors 258 to match the impedance between the power amplifier 20 and the dynamic load 260.
• the absence of moving mechanical parts leads to higher reliability.
• the step response of the system 200 is faster than about 1 ms because the speed of the response is governed by the electronics and not by the mechanical response.
• a change in frequency results in a change in both the conductance and the susceptance.
• a change in shunt capacitance results only in a change in the susceptance and does not affect the conductance value.
• the matrix that relates the controlled variable vector (formulated by the real and imaginary components of the admittance) and the controlling variable vector (formulated by the shunt and series capacitance or the shunt and frequency) is triangular. As a result, independent susceptance regulation is achieved by varying the shunt capacitance.
• Independent susceptance regulation allows for the implementation of a frequency control algorithm based only on the deviation of the conductance from the conductance setpoint.
• both the conductance-based frequency control loop and the susceptance-based shunt capacitance control loop can be operated simultaneously and at high-speed, resulting in improved robustness.
• Fig. 8 is a block diagram 300 of a method for determining the power dissipated (loss) in the electronic matching network 250 (Fig. 2) to improve the efficiency of the system 200.
• Step one a power meter 314 (Fig. 9A) is calibrated into a 50 ⁇ calorimeter power reference to determine the power delivered to the 50 ⁇ load.
• Step two a load simulator calorimeter 332 (Fig. 9B) is calibrated to a DC power reference to determine the power dissipated inside a load simulator 342 (Fig. 9D).
• Step three (330) the VI probe 240 (Fig. 2) is calibrated into a 50 ⁇ load to determine the power delivered by the power amplifier 220 (Fig. 2).
• Step 5 the power dissipated in the electronic matching system is calculated by difference between the he power delivered by the power amplifier 220 and the power delivered to.
• Z 1 R L + jX L
• Fig. 9 A is detailed implementation diagram of step 310 for calibrating the power meter 314.
• a calorimeter 322 is coupled to the output of the VI Probe 240, RP power is applied from the power amplifier 220, and the power meter 314 is calibrated.
• Calorimetry is the measurement of thermal losses. It is implemented by thermally insulating the 50 ⁇ load in the calorimeter (322) to prevent ambient thermal losses and measuring the flow rate and the temperature rise of the cooling water.
• a computer 324 acquires flow rate and temperature measurements to compute the power dissipation in the load and the difference (error) with respect to readout of the power meter. The computer 324 then applies this error as a correction to the power meter to complete the calibration.
• Fig. 9B is detailed implementation diagram of step 320 for calibrating the load simulator calorimeter 332.
• a load simulator calorimeter 332 is coupled to a DC power supply 334, DC power is applied, and the load simulator calorimeter 332 is calibrated.
• the DC power supply provides the DC power measurements.
• a computer 324 uses flow rate and temperature measurements at the inlet and outlet of the cooling system to compute the power dissipated in the load simulator. The computer 324 then applies the error between the power reported by the DC power supply and the power computed using calorimetry as a correction to the load simulator to complete the calibration.
• Fig. 9C is detailed implementation diagram step 330 for calibrating an RF impedance analyzer or VI probe 240.
• the VI Probe 240 calibration in each integrated RF generator system 200 includes the following steps that yield a matrix transfer function that relates the VI probe voltage and current measured by the DSP compensator board 230 to an actual RF line voltage and current.
• a short circuit connector 312 is coupled to the RF line output terminal of the VI probe 240, RF power is applied from the power amplifier 220, and Z* p is computed, wherein Zff is defined as the ratio of V ⁇ p 11 ⁇ as measured by the DSP compensator board 230 for short circuit.
• an open circuit connector 314 is coupled to the RF line output terminal of the VI probe 240, RF power is applied from the power amplifier 220, and Zf/ is computed, wherein Zf/ is defined as the ratio of V ⁇ I I ⁇ p as measured by the DSP compensator board 230 for open circuit.
• P 1 is the delivered power measured by a power meter 318 at the 50 ⁇ load 316.
• Equation 10 translates VI probe measurement signals into RF line voltage and RF line current at the output of the VI probe 240.
• Fig. 9D is detailed implementation diagram step 340 for calibrating the system 200 (Fig. 2).
• the system level calibration is used to quantify the power loss in the electronic matching network 250 for a range of values matching network variables.
• a load simulator 342 is coupled to the output of the electronic matching network 250.
• the load simulator is an electronic matching network inverse to the electronic matching network 250.
• a 50 ⁇ load is coupled to the output of the load simulator 342.
• the system-level calibration of the RF generator system 200 is performed as follows. First, a series inductance is adjusted in // steps for 4 e [A m i n A max ] • Second, a power setpoint value is changed inpp steps P sp e [P spmin P spm ⁇ ] W.
• a shunt capacitance setpoint value is changed in cc steps C lcmd e [C tcmdmin C lcmda l .
• the load simulator 342 is set to present an impedance mismatch at the output of the electronic matching network 250.
• RF power is applied from the power amplifier 220 and the power meter 314 measures the terminating load 312 resistance.
• the terminating load resistance is denoted by P 50n and transformed to the input of the load simulator 342.
• the simulated load is denoted by P ⁇ as P Sys ⁇ > where C 1 and C 2 represent the series and shunt capacitance of the load simulator and f 50 _ lo _ sim represents a tabular arrangement.
• the losses associated in electronic matching network 250 is computed by the difference between the P L and P 50n .
• Non-volatile memory e.g., flash memory
• the volatile memory e.g., Dynamic RAM
• the high-speed volatile memory is effectively utilized, wherein the arrangement of the calibration table (dimensions// xpp xccx ff ) can be based on how frequently L s , P sp , C tcmd , and / are changed.
• the calibration table can be segmented into // memory blocks; each block including pp memory pages; each memory page including a ccx ff dimensional table.
• a new memory block can be loaded into non- volatile memory when L s is changed, a new memory page can be loaded when power setpoint is changed, and calibration points for the appropriate memory page associated with C lcmd and / can be executed in real-time.

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• 2006
  • 2006-10-31 WO PCT/US2006/042360 patent/WO2007053569A1/en active Application Filing
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