EP1940209B1 - Leiterplatte und Herstellungsverfahren dafür - Google Patents

Leiterplatte und Herstellungsverfahren dafür Download PDF

Info

Publication number
EP1940209B1
EP1940209B1 EP08075294A EP08075294A EP1940209B1 EP 1940209 B1 EP1940209 B1 EP 1940209B1 EP 08075294 A EP08075294 A EP 08075294A EP 08075294 A EP08075294 A EP 08075294A EP 1940209 B1 EP1940209 B1 EP 1940209B1
Authority
EP
European Patent Office
Prior art keywords
solder
layer
roughened surface
solder resist
conductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP08075294A
Other languages
English (en)
French (fr)
Other versions
EP1940209A2 (de
EP1940209A3 (de
Inventor
Hontin En
Hui Zhong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11123926A external-priority patent/JP2000315854A/ja
Priority claimed from JP11139539A external-priority patent/JP2000082871A/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of EP1940209A2 publication Critical patent/EP1940209A2/de
Publication of EP1940209A3 publication Critical patent/EP1940209A3/de
Application granted granted Critical
Publication of EP1940209B1 publication Critical patent/EP1940209B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1157—Using means for chemical reduction
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/121—Metallo-organic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/122—Organic non-polymeric compounds, e.g. oil, wax, thiol
    • H05K2203/124—Heterocyclic organic compounds, e.g. azole, furan
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/385—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by conversion of the surface of the metal, e.g. by oxidation, whether or not followed by reaction or removal of the converted layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

  • This invention relates to a method of producing a printed wiring board, and more particularly to a printed wiring board capable of improving an adhesion property and a strength among conductor circuit for solder pad, solder resist layer and solder bump.
  • Such a build-up multilayer wiring board is considerably noticed from a viewpoint of a demand for high densification of multilayer wiring boards.
  • Such a build-up multilayer wiring board is produced by a method disclosed, for example, in JP-B-4-55555 .
  • an insulating material made from a photosensitive adhesive for electroless plating is applied onto a core substrate, dried, exposed to a light and developed to form an interlaminar insulating resin layer having an opening for a via-hole. Then, the surface of the interlaminar insulating resin layer is roughened by treating with an oxidizing agent or the like and a plating resist is disposed on the roughened surface, and thereafter non-resist forming portions are subjected to an electroless plating to form two-layer conductor circuit pattern including a via-hole. These steps are repeated several times to obtain a multilayered build-up wiring board.
  • solder bumps are arranged on respective conductor circuits for solder pads as a surface layer, and the board is connected to an IC chip through the solder bumps.
  • a solder resist layer is disposed in the printed wiring board.
  • the surfaces of the conductor circuits for the solder pads are subjected to a roughening treatment.
  • a roughening treatment of the conductor circuit there are used graphitization-reduction treatment, etching with sulfuric acid-hydrogen peroxide, copper-nickel-phosphorus needle-shaped alloy plating and the like.
  • the strength of the solder bump is difficult to be maintained in the finely wired conductor circuits for the solder pads, and hence there may be caused the dropping-off of the solder bump.
  • the inventors have confirmed that if the roughened surface of the finely wired conductor circuit is deteriorated by oxidation, corrosion or the like, the adhesion property to the solder resist layer is considerably lowered. Particularly, when the conductor circuits are arranged at a coarse state in the surface layer of the printed wiring board, the adhesion property between the conductor circuit and the solder resist layer more lowers.
  • an object of the invention to provide a printed wiring board in which the adhesion property between the finely wired conductor circuit and the solder resist layer is enhanced and these conductor circuits are strongly adhered to the solder resist layer without peeling even in solder bump-forming portions to cause no bad continuity in the solder bump-forming portions.
  • the invention lies in a method of producing a printed wiring board as defined in claim 1.
  • the inventors have made various studies with respect to the method of roughening the surface of the conductor circuit for solder pad in order to improve the adhesion property and strength between the surface layer of the multilayer printed wiring board and the solder resist layer and the adhesion property and strength between the surface layer of the multilayer printed wiring board and the solder pad.
  • the inventors have studied a graphitization-reduction treatment, an etching treatment with sulfuric acid-hydrogen peroxide or the like, a copper-nickel-phosphorus needle-shaped alloy plating and the like for demands to enhance the adhesion property and strength between the conductor circuit formed at fine wiring of not more than 50 ⁇ m and the solder resist layer and the adhesion property and strength between the conductor circuit and the solder bump, especially a demand for enhancing adhesion strength to prevent peelings and dropping-off of the solder pad and solder bump after the reliability test.
  • the graphitization-reduction treatment, the etching treatment with sulfuric acid-hydrogen peroxide and the like are unsuitable as the roughening treatment of the conductor circuit for solder pad with finer wiring.
  • the etching treatment with sulfuric acid-hydrogen peroxide and the like if the wiring density is made coarse with the fine wiring of not more than 50 ⁇ m, it has been confirmed that the contact area between the conductor circuit and the solder resist layer is made small by the convex portion formed on the roughened surface and the adhesion force of the solder resist layer can not be improved.
  • the solder resist layer is peeled off in the coarse portion of the wiring density under heat cycle condition.
  • the noble metal layer is peeled off in the solder pad, or cracking is caused to induce the dropping-off of the solder bump by the graphitization-reduction treatment or the like.
  • the formation of the roughened layer through the copper-nickel-phosphorus needle-shaped alloy plating is excellent in the adhesion property between the conductor circuit and the solder resist layer and indicates sufficient adhesion force even in the fine wiring of not more than 50 ⁇ m, particularly a coarse portion of such a wiring.
  • the roughened layer is formed by the plating, so that as the density of the fine wiring becomes high, the precipitated needle-shaped alloy stretches on the interlaminar resin insulating layer to connect the conductor circuits to each other to thereby cause a short-circuit.
  • the solder resist layer made of a resin is removed by light exposure and development in the portions forming the solder bumps.
  • the distance between the projections is narrow, so that it has been confirmed that when the solder resist layer is removed by the light exposure and development to form portions forming the solder bumps, an oxidizing agent solution or an alkali solution for removing the developing solution or residual resin does not flow in an opening portion and hence the resin retains between the projections to leave an organic residue of the solder resist forming resin in the bottom of the opening portion.
  • Such an organic residue may cause bad continuity or wiring breakage between the conductor circuit for solder pad in the opening portion and the metal beneath the solder bump. Further, the organic residue does not conduct the formation of the noble metal layer in the solder pad or causes the poor formation thereof to thereby lower the strength between the solder pad and the conductor circuit for the solder pad.
  • the inventors have made further studies with respect to the other roughening treatment. Consequently, it has been found out that the roughened surface formed by treating the surface of the conductor circuit with an etching solution containing a copper(II) complex and an organic acid is excellent in the adhesion property to the solder resist forming resin and the adhesion property to the metal beneath the solder bump and is very suitable for the formation of the solder bump and as a result, the invention has been accomplished.
  • the roughened surface having a given roughened shape as formed by the above etching solution is formed on the conductor circuit and the solder resist layer is arranged through such a roughened surface.
  • the roughened surface is formed on the conductor circuits having a high wiring density with finer wiring of not more than 50 ⁇ m without causing the bad continuity as in the copper-nickel-phosphorus needle-shaped alloy plating.
  • the roughened surface is excellent in the adhesion property to the solder resist layer and can ensure the sufficient adhesion property between the conductor circuit and the solder resist layer when the solder resist layer is removed in the portion forming the solder bump to make small the contact area between the conductor circuit and the solder resist layer, or even in the printed wiring board having a coarse state of the wiring density with fine wiring.
  • the resin residue is less on the roughened surface, so that the roughened surface is excellent in the adhesion property to the metal beneath the solder bump and does not cause the bad continuity in the portion forming the solder bump.
  • the inventors have detailedly studied the roughened surface of the conductor circuit for the solder pad in order to enhance the strength of the solder bump.
  • the inventors have found that the above roughened surface is considerably degraded by oxidation, corrosion or the like. According to the inventors' studies, it has been confirmed that as the degradation of the roughened surface occurs, the strength of the uneven portion on the surface considerably lowers and the uneven portion is dissolved by a solvent such as an acid, an alkali or the like. Such a degradation of the roughened surface considerably weakens the adhesion strength between the solder resist layer and the roughened surface or between the roughened surface and the metal beneath the solder bump and causes the peeling therebetween.
  • the inventors have found out that the strength of the solder bump is considerably increased in the printed wiring board produced by covering the roughened surface with a metal layer of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and a noble metal and arranging the solder resist layer on the metal layer and as a result, the invention has been accomplished.
  • the metal layer prevents the oxidation, corrosion or the like of the roughened surface and also prevents the surface degradation of the roughened surface. And also, according to the invention, the metal layer protects the uneven portions of the roughened surface against the solvent such as acid, alkali or the like and prevents the dissolution of the uneven portions in the roughened surface even when the roughened surface is immersed in such a solvent.
  • the metal layer prevents the lowering of the strength of the roughened surface and also the roughened surface covered with the metal layer holds its shape and strength, so that there can be eliminated the peeling between the roughened surface and the solder resist layer, no formation or poor formation of the metal layer in the solder pad.
  • the surface degradation of the roughened surface is not caused as compared with the roughened surface not covered with the metal layer in the arrangement of the solder resist layer and the solder bump, so that the shape of the roughened layer becomes uniform and the oxidation or dissolution of the roughened surface through chemicals can be prevented.
  • the adhesion strength between the conductor circuit for solder pad and the solder bump is considerably improved.
  • a shear strength of the solder bump is improved by at least 10%.
  • the shape and strength having excellent adhesion property to the solder resist layer and adhesion property to the metal beneath the solder bump are maintained by covering the roughened surface of the conductor circuit for solder pad with the metal layer, so that the strength of the solder bump is considerably increased and the dropping-off of the solder bump can be prevented.
  • the inventors have made various studies and found that the roughened surface formed on the finely wired conductor circuit for solder pad is deteriorated by oxidation, corrosion or the like, whereby the adhesion property between the solder resist layer and the conductor circuit for solder pad formed by the graphitization-reduction treatment, etching treatment with sulfuric acid-hydrogen peroxide or the like is considerably lowered.
  • the solder resist forming resin is applied to the conductor circuit for the solder pad, if the conductor circuit is deteriorated, since the wettability of the solder resist forming resin differs, the adhesion property of the solder resist layer lowers at the contact surface between the conductor circuit and the solder resist layer.
  • the surface layer of the roughened surface and the metal state of the conductor circuit for solder pad as a whole can be prevented from deteriorating due to oxidation, corrosion or the like by forming the rust proof layer on the roughened surface.
  • the difference in the wettability to the conductor circuit for solder pad is removed and there is not caused the peeling between the conductor circuit for solder pad and the solder resist layer resulted from the difference of the wettability.
  • the rust proof layer on the conductor circuit for solder pad prevents the deterioration of the conductor circuit, according to the invention, even if the opening for the solder pad is formed on the solder resist layer, the elution of the conductor circuit is eliminated and the roughened surface having a very good adhesion property to the solder pad can be held.
  • a metal layer for rust proof layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and a noble metal is formed on the roughened surface of the conductor circuit for solder pad and a rust proof layer is formed on the metal layer and the solder resist layer is arranged on the rust proof layer and an opening portion for solder body is formed, the shape of the roughened surface having an excellent adhesion property between the solder resist layer and the solder pad is maintained and also the strength of the solder pad is more improved on the roughened surface exposed to the opening portion and as a result, the invention has been accomplished.
  • the roughened surface covered with the metal layer for the rust proof layer can prevent the deterioration of the roughened surface due to the oxidation, corrosion or the like and the dissolution of uneven surface in the immersion into acid or alkali solution. Therefore, the roughened surface is a uniform shape and holds the strength, so that there is not caused the peeling of the solder resist layer and the non-formation of the metal layer in the solder pad and the dropping-off of the solder bump can be prevented.
  • the above roughened surface does not cause the bad continuity due to the resin residue in the formation of the opening portion in the solder resist layer. Because, the deterioration is not caused by covering with the metal layer for the rust proof layer and the wettability on the roughened surface becomes uniform and the organic residue of the resin itself is not left.
  • the roughened surface does not cause the resin residue thereon and is excellent in the adhesion property to the metal beneath the solder bump and does not cause the bad continuity in the portions forming the solder bumps.
  • the roughened surface covered with the metal layer for the rust proof layer uniformly holds the shape of the roughened surface as compared with the case of forming the solder resist layer and solder bumps on the roughened surface not covered with the metal layer for the rust proof layer, maintains the shape of the roughened surface and improves the strength of the resulting solder bump, which can prevent the oxidation or dissolution of the roughened surface through chemicals and the shear strength of the solder bump is improved by at least 10%. And also, even in the reliability test, there are not caused the peeling of the solder resist layer, peeling of the metal layer, cracking and occurrence of dropping-off.
  • the roughened surface of the conductor circuit for solder pad in the printed wiring board according to the invention is protected with the rust proof layer, so that the deterioration of the conductor circuit for solder pad is prevented and the shape of the roughened surface having excellent adhesion properties to the solder resist layer and the solder pad is maintained and hence the adhesion property between the solder resist layer and the conductor circuit for solder pad having a coarse wiring state with fine wiring is increased and the conductor circuit and the solder resist layer are strongly adhered to each other without peeling even in the portions forming the solder bumps and the bad continuity is not caused in the portion forming the solder bump.
  • the roughened surface of the conductor circuit for solder pad is covered with a given metal and protected with the rust proof layer, so that even when the solder pad is applied after a part of the solder resist layer is opened, the surface of the conductor circuit for solder pad maintains the shape having an excellent adhesion property to the solder pad and also the resin resulted from the solder resist layer is not left, so that the adhesion properties and strengths between the conductor circuit for solder pad and the solder resist layer and between the conductor circuit for solder pad and the solder pad are improved and the solder bump having an excellent adhesion property to the metal beneath the solder bump is formed.
  • Fig. 1 is a microphotograph illustrating a first embodiment of the roughened surface according to the invention. This is pictured obliquely from the roughened surface by means of an electron microscope.
  • Fig. 2 is a microphotograph illustrating a second embodiment of the roughened surface according to the invention. This is also pictured likewise the case of Fig. 1 in a higher magnification.
  • Fig. 3 is a microphotograph illustrating a third embodiment of the roughened surface according to the invention. This is pictured just above the roughened surface by means of an electron microscope in the same magnification as in Fig. 2 .
  • a solder resist layer is arranged on the conductor circuit for solder pad through the roughened surface formed on the conductor circuit as shown by the above electron microphotograph.
  • Figs. 4-8 are diagrammatic views of such a roughened surface.
  • Fig. 4 is a plane view
  • Fig. 5 is a longitudinal section view along a line A-A of Fig. 4
  • Fig. 6 is a longitudinal section view cut between anchor portion and recess portion
  • Fig. 7 is a longitudinal section view illustrating ridgelines between anchor portions
  • Fig. 8 is a longitudinal section view cut between ridgeline and recess portion.
  • the roughened surface according to the invention has plural anchor portions 1, plural recess portions 2 and plural ridgelines 3 in which the anchor portions 1, recess portions 2 and ridgelines 3 are dispersed.
  • the recess portion 2 is formed between the anchor portion 1 and anchor portion 1 adjacent thereto.
  • the anchor portion 1 and another anchor portion 1 adjacent thereto are connected to each other through the ridgeline 3.
  • the recess portion 2 is surrounded by the anchor portions 1 and the ridgelines 3 as shown in Figs. 6 and 8 .
  • a microphotograph of a roughened layer made of the conventional needle-shaped alloy by plating is shown in Fig. 32 .
  • needle-shaped alloys are overlapped with each other and a space is formed between the needle-shaped alloys.
  • needle projections crowd to each other, so that the distance between the projections is narrow and hence an oxidizing agent solution for removing the developing solution or residual resin is not flowed and the resin retains between the projections to cause resin residue.
  • the roughened surface according to the invention indicates a complicated uneven shape wherein the anchor portion is a highest portion and the recess portion is formed in lowest portion surrounding the anchor portion and the anchor portion and another anchor portion adjacent thereto are connected each other through the ridgeline lower than the anchor portion but higher than the recess portion.
  • the anchor portions enter into the solder resist layer to strongly bond the conductor circuit to the solder resist layer, so that the peeling between the conductor circuit and the solder resist layer is not caused in the portion forming the solder bump, particularly even at a state that the wiring density with fine wiring is coarse.
  • the roughened surface is excellent in the affinity to the plating solution, the plated film is penetrated into the recess portions of the roughened surface to adhere to the anchor portions of the roughened surface, so that the anchor portions dig into the metal beneath solder bump and hence the adhesion property between the conductor circuit and the solder bump is not lowered.
  • the anchor portions do not crowd to each other and also the ridgelines connecting the anchor portions have a shape not obstructing the flow of the resin.
  • the oxidizing agent solution for removing the developing solution or the resin residue is easily flowed between the recess portions or between the anchor portions and the solder resist forming resin hardly retains.
  • the roughened surface according to the invention has no resin residue after the developing treatment and is excellent in the adhesion property to the metal beneath the solder bump.
  • the roughened surface according to the invention has an optimum shape of preventing the resin residue after the developing treatment while maintaining the adhesion property between the conductor circuit and the solder resist layer and the adhesion property between the conductor circuit and the metal beneath solder bump.
  • the roughened surface according to the invention can be formed by dropping off metal crystal particles from the surface of the conductor circuit with an etching solution containing a copper(II) complex and an organic acid.
  • portions dropping off the metal crystal particles form the recess portions (concave parts).
  • the recess portions can be formed in the shape corresponding to approximately polyhedral shape inherent to the metal crystal particle.
  • approximately polyhedral shape used herein means a polyhedron such as trihedron, tetrahedron, pentahedron, hexahedron or the like and a combination of two or more of these polyhedrons. Such a recess portion can prevent the resin residue after the developing treatment.
  • the anchor portions of the roughened surface can be formed as portions left by dropping off the metal crystal particles.
  • the thus formed anchor portions are squarish convex portions and surrounded by the recess portions, so that they do not overlap with each other.
  • the roughened surface having such a complicated uneven shape can prevent the resin residue after the developing treatment while maintaining the adhesion properties to the solder resist forming resin and the metal beneath solder bump.
  • the ridgelines of the roughened surface are formed by dropping off adjoining metal crystal particles. These ridgelines connect the anchor portion and another adjacent anchor portion to each other at a position lower than the height of the anchor portion. These ridgelines can be formed at a branched state by dropping off three or more adjoining metal crystal particles. And also, the ridgelines can be formed at a sharp-edged state because the metal crystal particles are dropped off in approximately polyhedral shape. These ridgelines disperse the anchor portions so as to surround the anchor portion by the recess portions and the ridgelines. In the roughened surface having such amore complicated uneven shape, the contact area to the resin or the metal beneath solder bump is widened to more improve the adhesion property and the resin residue can be more prevented.
  • the roughened surface is preferable to have a maximum roughness (Rmax) of 0.5 ⁇ 10 ⁇ m.
  • Rmax maximum roughness
  • the roughened surface is favorable to have 2 ⁇ 100 anchor portions and 2 ⁇ 100 recess portions per 25 ⁇ m 2 on average.
  • the resin residue after the developing treatment can be prevented while maintaining the adhesion property between the roughened surface and the solder resist layer and the adhesion property between the roughened surface and the metal beneath solder bump, while when the number of recess portions per 25 ⁇ m 2 is 2 ⁇ 100 on average, the crowd of the anchor portions is prevented to control the occurrence of resin residue after the developing treatment and also the adhesion property between the roughened surface and the solder resist layer and the adhesion property between the roughened surface and the metal beneath solder bump can be maintained.
  • the number of ridgelines per 25 ⁇ m 2 is desirable to be 3 ⁇ 3000 on average.
  • the shape of the roughened surface becomes complicated and the contact area to the solder resist layer and the metal beneath solder bump is widened, whereby the adhesion property to the solder resist layer and the like can be improved and at the same time the resin residue can easily be removed.
  • each of anchor portions, recess portions and ridgelines is represented by an average of measured values when the roughened surface is pictured just above and obliquely from above by 45° by means of an electron microscope at 5000 magnification as shown in Figs. 2 and 3 and each number is measured at an optional region of 25 ⁇ m 2 .
  • Figs. 9 ⁇ 12 are section views of another embodiment of the roughened surface according to the invention.
  • the roughened surface as shown in Figs. 4 ⁇ 8 is covered with a metal layer 51.
  • the metal layer 51 as shown in Figs. 9 ⁇ 12 is made of a hardly oxidized or corroded metal or a metal not damaging the adhesion property to the solder resist forming resin or adhesion property to the metal beneath solder bump even if this metal itself is oxidized or corroded.
  • the metal layer prevents the formation of oxide film or corrosion film on the roughened surface, and covers the roughened surface at a state of maintaining the shape of the roughened surface, and does not damage the adhesion property between the roughened surface and the solder resist forming resin or the metal beneath solder bump.
  • Such a metal layer can prevent the lowering of adhesion strength between the roughened surface and the solder resist layer or the adhesion strength between the roughened surface and the metal beneath solder bump.
  • the metal layer can increase the hardness of the metal constituting the roughened surface, metal breakage is not caused at the roughened surface, so that the peeling between the roughened surface and the solder resist layer or between the roughened surface and the metal beneath solder bump is more prevented.
  • the roughened surface has the metal layer, so that the oxidized or corroded layer is hardly formed on the roughened surface. If the oxidized or corroded layer is formed, the adhesion property to the solder resist forming resin or the metal beneath solder bump is maintained and hence the peeling between the roughened surface and the solder resist forming resin or between the roughened surface and the metal beneath solder bump is not caused even by heating.
  • the metal layer is made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and a noble metal.
  • they are a metal or a noble metal having an ionization tendency larger than copper but not smaller than titanium.
  • a metal or noble metal having an ionization tendency larger than copper but not smaller than titanium.
  • non-oxidizing metals such as nickel, tin, cobalt and noble metal.
  • noble metal at least one of gold, silver, platinum and palladium is desirable.
  • metal not lowering the adhesion property between the metal layer and the solder resist forming resin even if such a metal is oxidized or corroded mention may be made of titanium, zinc, iron, indium, thallium, lead and bismuth.
  • the roughened surface according to the invention when the roughened surface according to the invention is covered with the metal layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal, the roughened shape suitable for preventing the resin residue after the developing treatment is maintained and the adhesion property between the conductor circuit for solder pad and the solder resist layer, adhesion property between the conductor circuit for solder pad and the metal beneath solder bump and the strength of the solder bump can be improved.
  • the metal layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal
  • plating electrolytic plating, electroless plating, substitution plating
  • vapor deposition electrophoretic deposition
  • sputtering a method of covering the roughened surface with the metal layer.
  • the thickness of the metal layer is within a range of 0.01 ⁇ 1 ⁇ m, preferably 0.03 ⁇ 0.5 ⁇ m.
  • the metal layer having the thickness within the above range can prevent oxidation or corrosion of copper conductor while maintaining the uneven shape of the roughened surface.
  • the thickness is less than 0.01 ⁇ m, the roughened surface can not completely be covered, while when it exceeds 1 ⁇ m, the metal penetrates into gaps of the roughened surface to offset the irregularity of the roughened surface and the adhesion property between the roughened surface and the solder resist layer or between the roughened surface and the metal beneath solder bump may be lowered.
  • the roughened surface according to the invention can be formed by treating the conductor circuits for solder pads with an etching solution containing copper(II) complex and an organic acid.
  • an etching solution can dissolve the copper conductor circuits under an oxygen existing condition such as spraying, bubbling or the like.
  • the etching is guessed to proceed according to the following reaction formula: Cu + Cu(II)A n ⁇ 2Cu(I)A n/2 ⁇ aeration ⁇ 2Cu(I)A n/2 + n/4O 2 + nAH ⁇ 2Cu(II)A n + n/2H 2 O wherein A is a complexing agent (acting as a chelate agent) and n is coordination number).
  • the resulting copper(I) complex is dissolved by an acid and bonds with oxygen to form copper(II) complex, which again contributes to the oxidation of copper.
  • the copper(II) complex used in the invention is favorably a cupric complex of an azole.
  • This type of the copper(II) complex acts as an oxidizing agent oxidizing metallic copper or the like.
  • the azole there are mentioned diazoles, triazoles and tetrazoles. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole and the like are preferable.
  • the addition amount of the copper(II) complex of the azole is preferably 1 ⁇ 15% by weight. Because, the complex is excellent in the solubility and stability within the above range.
  • the organic acid is compounded with the copper(II) complex for dissolving copper oxide.
  • the organic acid is favorably at least one selected from the group consisting of formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succeinic acid, gultaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid and sulfamic acid.
  • the addition amount of the organic acid is preferably within a range of 0.1 ⁇ 30% by weight for maintaining the solubility of the oxidized copper and ensuring the solution stability.
  • a halogen ion such as fluorine ion, chlorine ion, bromine ion or the like for assisting the dissolution of copper and the oxidation action of the azole.
  • a halogen ion may be supplied as hydrochloric acid, sodium chloride or the like.
  • the addition amount of the halogen ion is favorably within a range of 0.01 ⁇ 20% by weight because the adhesion property between the resulting roughened surface and the solder resist layer is excellent.
  • the etching solution according to the invention can be prepared by dissolving the copper(II) complex of the azole and the organic acid (if necessary, halogen ion) in water.
  • a commercially available etching solution for example "Mech Etchbond", trade name, made by Mech Corporation.
  • An average etching quantity with the etching solution is favorably within a range of 0.1 ⁇ 10 ⁇ m.
  • it is less than 0.1 ⁇ m, the adhesion property between the roughened surface and the solder resist layer lowers, while when it exceeds 10 ⁇ m, the resin residue is apt to be caused and also the wiring breakage and the like are easily caused in the fine wiring of not more than 50 ⁇ m.
  • the metal layer may be applied to the thus formed roughened surface.
  • the metal layer is made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal as mentioned above.
  • the formation of the metal layer may be carried out by plating, vapor deposition, electrophoretic deposition or sputtering. The plating is preferable in view of the uniformity of the resulting metal layer.
  • the roughened layer after the roughening treatment may be subjected to a heat treatment prior to the formation of the metal layer. Since the etching solution and remaining components are evaporated by the heat treatment, the surface state of the roughened layer becomes uniform, which facilitates the formation of the metal layer.
  • the temperature of the heat treatment may be set to various ranges in accordance with the shape and thickness of the roughened surface, metallic components and thickness of the conductor circuit for solder pad and the like. Particularly, the temperature is favorably within a range of 50 ⁇ 250°C. When the temperature is lower than 50°C, the effect of the heat treatment is not observed, while when it exceeds 250°C, the roughened surface is oxidized and the resulting metal layer becomes ununiform.
  • Fig. 13 shows a longitudinal section of an embodiment of the conductor circuit for solder pad to be provided with the rust proof layer according to the invention.
  • Fig. 14 shows a longitudinal section of another embodiment of the conductor circuit for solder pad to be provided with the rust proof layer according to the invention.
  • the conductor circuit for solder pad provided with the rust proof layer according to the invention is disposed on an outermost layer of the printed wiring board and connected to an IC chip or the like through the solder bumps.
  • Such a conductor circuit for solder pad is protected with the solder resist layer so as not to directly receive high temperature and high pressure from exterior and provided at its surface with the roughened surface for obtaining a high adhesion property to the solder resist layer and a high adhesion property to the solder pad.
  • the roughened surface for the formation of the rust proof layer according to the invention includes a roughened surface 103 formed by roughening a surface of a main body 102 of a conductor circuit 101 for solder pad through graphitization-reduction treatment, etching or the like as shown in Fig. 13 , and a roughened surface 107 formed by precipitating a roughened layer 106 made of an electroless plated film or the like on a surface of a main body 105 of a conductor circuit 104 for solder pad as shown in Fig. 14 .
  • the roughened surface is formed on the conductor circuit for solder pad as a surface layer of the printed wiring board provided with conductor circuits through various steps.
  • the formation of the roughened surface for the formation of the rust proof layer is carried out by anyone of oxidation-reduction treatment, electroless plating and etching treatment.
  • the formation of the roughened layer made of copper-nickel-phosphorus alloy and the roughened surface formed with an etching solution containing a copper(II) complex and an organic acid are preferable in view of the adhesion property to the solder resist layer and uniformity of the roughened surface.
  • the roughened surface When the roughened surface is formed by oxidation-reduction treatment, it may be formed by washing the printed wiring board having the conductor circuits with an alkali or the like, treating with an acid, immersing in a solution containing NaOH, NaClO 2 , Na 2 PO 4 and the like as an oxidation bath (graphitization bath) and then immersing in a solution containing NaOH and NaBH 4 as a reduction bath.
  • a maximum height of the roughened surface is within a range of 0.01 ⁇ 2 ⁇ m.
  • the oxidation bath (graphitization bath) is desirably used to have a concentration range of NaOH: 1 ⁇ 30 g/L, NaClO 2 : 5 ⁇ 6 g/L and Na 3 PO 4 : 0.1 ⁇ 20 g/L and may contain nitrogen-based or urea-based surfactant and the like. It is preferable that the conductor circuit is immersed in this plating solution at a temperature of 30 ⁇ 70°C for 1 ⁇ 15 minutes.
  • the subsequent reduction bath is desirably used to have a composition range of NaOH: 1 ⁇ 30 g/L and NaBH 4 : 0.5 ⁇ 20 g/L and may contain various additives. It is preferable that the conductor circuit is immersed in this plating solution at a temperature of 30 ⁇ 70°C for 1 ⁇ 15 minutes. Thus, the roughened surface may be formed on the surface layer of the conductor circuit.
  • the roughened surface When the roughened surface is formed by electroless plating, it may be formed by immersing the printed wiring board having the conductor circuits in an electroless plating solution after the washing with an alkali or the like, the etching, the treatment with an acid and the application and activation of a catalyst.
  • a maximum height of the roughened surface is within a range of 0.1 ⁇ 10 ⁇ m.
  • the plating solution is desirably used to have a concentration range of copper (metal salt such as copper sulfate, copper chloride or the like): 1 ⁇ 40 g/L, nickel (metal salt such as nickel sulfate or the like): 0.1 ⁇ 6 g/L, citric acid: 10 ⁇ 20 g/L, hypophosphite: 10 ⁇ 100 g/L, boric acid: 10 ⁇ 40 g/L and surfactant: 0.01 ⁇ 10 g/L and may contain various additives, stabilizer and the like. It is favorable that the conductor circuit is immersed in this plating solution at a temperature of 50 ⁇ 80°C for 5 ⁇ 20 minutes. Thus, the roughened surface consisting of the plated layer and the roughened layer may be formed on the surface layer of the conductor circuit.
  • the shape of the roughened surface there are needle shape, porous shape and a combination thereof.
  • the needle shape is favorable from a viewpoint of forming easiness and adhesion property.
  • a maximum height of the roughened surface is within a range of 0.5 ⁇ 10 ⁇ m, preferably 1 ⁇ 5 ⁇ m. When it is less than 0.5 ⁇ m, the adhesion property to the solder resist layer lowers, while when it exceeds 10 ⁇ m, the peeling of the solder resist layer and the cracking are caused because the uniformity of the roughened surface is not held in the oxidation-reduction treatment and the electroless plating.
  • the etching solution can dissolve copper conductor circuit under an oxygen existing condition such as spraying, bubbling or the like.
  • the rust proof layer may be formed on the above conductor circuit for solder pad.
  • the rust proof layer according to the invention is desirable to contain at least one anti-rust agent selected from the group consisting of 1,2,3-benzotriazole, tollyltriazole and derivatives thereof as a main component.
  • 1,2,3-benzotriazole and triazole derivatives mean compounds wherein an alkyl group such as methyl group, ethyl group or the like, or carboxyl group, amino group, hydroxyl group or the like is bonded to a benzene ring as shown by the following chemical formulae (1), (2):
  • These compounds are excellent in the rust proofing effect of copper because they control the oxidation reaction of copper. And also, they do not remain on a pad of a conductor circuit exposed in an opening for a solder pad because they easily dissolve in a solvent used for the light exposure and development of the solder resist layer. As a result, even if the opening portion is formed in the pad of the conductor circuit for solder pad, the continuity between the conductor circuit and the solder bump is ensured without being insulated.
  • the rust proof layer remains on the boundary face between the conductor circuit for solder pad and the solder resist layer.
  • the film of the remaining rust proof layer can prevent the deformation and deterioration of the conductor circuit for solder pad by oxidation and corrosion caused through water, air and the like penetrated from the solder resist layer and solder pad portion under conditions of high temperature, high pressure and high humidity.
  • the formation of the rust proof layer can be carried out by coating, spraying or immersion.
  • the immersion method is favorable because the rust proof layer can evenly be formed on the conductor circuit without damaging the roughened surface.
  • the rust proof layer can be formed on the roughened surface of the conductor circuit in the printed wiring board by immersing the printed wiring board in a tank having a depth corresponding to approximately a whole of the conductor circuit at a temperature of 20 ⁇ 60°C for an immersion time of 10 ⁇ 600 seconds.
  • the rust proof layer exposed in the opening portion is can be removed by a gas plasma.
  • a treating method there may be mentioned a method wherein the printed wiring board provided with the opening portion for solder pad formed through light exposure and development is placed in a device held at a vacuum state and a plasma of oxygen, nitrogen, carbon dioxide gas or carbon tetrafluoride is discharged therein to remove the anti-rust agent remaining in the opening portion, residue of the solder resist layer and an oxide film layer on the surface of the solder resist layer.
  • plasma discharging quantity is 500 ⁇ 1000 W
  • a gas feeding amount is 100 ⁇ 500 sec/M
  • a treating time is 1 ⁇ 15 minutes.
  • the anti-rust agent existing in the opening portion and the residue of the solder resist layer are surely removed by the plasma treatment, whereby poor conduction to the solder bump is eliminated.
  • the oxide film layer on the surface of the solder resist layer is removed, so that there can be prevented the occurrence of inconvenience at subsequent plating step and mounting step without lowering the wettability of the solder resist layer.
  • a metal layer for rust proof layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal may be formed on the roughened surface prior to the application of the anti-rust agent.
  • Such a metal layer for the rust proof layer can be carried out by plating (anyone of electrolytic plating, electroless plating and substitution plating), vapor deposition, electrophoretic deposition or sputtering.
  • plating anyone of electrolytic plating, electroless plating and substitution plating
  • vapor deposition electrophoretic deposition or sputtering.
  • this metal layer is formed on a surface layer portion of the roughened surface of the conductor circuit for solder pad.
  • the thickness of the metal layer formed as an undercoat for the rust proof layer according to the invention is preferably within a range of 0.01 ⁇ 1 ⁇ m, more particularly 0.03 ⁇ 0.5 ⁇ m.
  • the thickness is less than 0.01 ⁇ m, the roughened surface can not completely be covered, while when it exceeds 1 ⁇ m, the covering metal penetrates into the roughened surface to offset the roughened shape to thereby lower the adhesion property.
  • the above rust proof layer is formed on the roughened surface covered with the metal layer for the rust proof layer.
  • the deformation and deterioration of the roughened surface through oxidation and the like are prevented by the synergistic action of the metal layer and the rust proof layer, so that the adhesion property and strength to the solder resist layer become uniform and the peel strength of the solder bump is improved. Therefore, the shape of the roughened surface hardly deteriorates even under conditions of high temperature, high pressure and high humidity in the reliability test and the strengths of the solder resist layer and the solder bump are improved.
  • the conductor circuit for solder pad after the formation of the roughened surface may be subjected to a heat treatment within a range of 50 ⁇ 250°C prior to the formation of the metal layer and the rust proof layer.
  • the heat treating conditions can be set to adequate ranges in accordance with the shape, thickness and material of the resulting roughened surface, component and thickness of the metal layer for rust proof layer covering the roughened surface and the like.
  • the heating temperature is lower than 50°C, the effect of the heat treatment is not observed, while when it exceeds 250°C, the roughened surface is oxidized and the resulting metal layer and the rust proof layer become ununiform.
  • the solder resist layer is formed on the thus formed roughened surface having a given shape.
  • the thickness of the solder resist layer is preferably 2 ⁇ 40 ⁇ m. When the thickness is too thin, the solder resist layer does not act as a solder dam, while when the thickness is too thick, it is difficult to form the opening portion for solder bump and also the contacting with the solder body may be caused to bring about the occurrence of cracking in the solder body.
  • the solder resist layer can be made from various resins. For example, it can be formed by curing bisphenol A-type epoxy resin or an acrylate thereof, or novolac type epoxy resin or an acrylate thereof with an amine curing agent, an imidazole curing agent or the like.
  • solder resist layer when the solder resist layer is opened to dispose the solder bump thereon, it is favorable to cure the novolac type epoxy resin or an acrylate thereof with an imidazole curing agent.
  • the solder resist layer made of such a resin has a merit that migration of lead (phenomenon of diffusing lead ion into the solder resist layer) is less.
  • the acrylate of the novolac type epoxy resin when the acrylate of the novolac type epoxy resin is cured with the imidazole curing agent, the resulting solder resist layer is excellent in the heat resistance and resistance to alkali and is not deteriorated even at a temperature of fusing the solder (about 200°C) and is not decomposed with a strong base plating solution such as nickel plating solution or gold plating solution.
  • a strong base plating solution such as nickel plating solution or gold plating solution.
  • the acrylate of the novolac type epoxy resin mention may be made of epoxy resin formed by reacting glycidyl ether of phenol novolac or cresol novolac with acrylic acid or methacrylic acid, and the like.
  • the solder resist layer made from the acrylate of novolac type epoxy resin is constituted with a resin having a rigid skeleton, so that it is apt to cause the peeling from the conductor circuit.
  • the roughened surface according to the invention can advantageously prevent the above peeling.
  • the imidazole curing agent is desirable to be liquid at 25°C because the uniform mixing is easily attained.
  • a curing agent mention may be made of 1-benzyl-2-methyl imidazole (trade name: 1B2ZM), 1-cyanoethyl-2-ethyl-4-methyl imidazole (trade name: 2E4MZ-CN) and 4-methyl-2-ethyl imidazole (trade name: 2E4MZ).
  • solder resist composition it is desirable to form a solder resist composition by dissolving the above resin and curing agent in a solvent such as glycol ether or the like.
  • a solvent such as glycol ether or the like.
  • DMDG diethylene glycol dimethyl ether
  • DMTG triethylene glycol dimethyl ether
  • a solvent can completely dissolve a reaction initiator such as benzophenone, Michler ketone or the like by warming to about 30 ⁇ 50°C.
  • the amount of the solvent is preferably within a range of 10 ⁇ 40% by weight to the solder resist composition.
  • the addition amount of the imidazole curing agent is desirable to be 1 ⁇ 10% by weight based on a total solid content of the solder resist composition. When the addition amount is within the above range, the uniform mixing is easily attained.
  • the solder resist composition may be added with an anti-foaming agent, a leveling agent, an initiator, a photosensitizer, a thermosetting resin for improving heat resistance and resistance to base and giving a flexibility, a photosensitive monomer for improving a resolution, and the like.
  • leveling agent a polymer of acrylic ester is favorable.
  • initiator Irgaquar 1907 (trade name, made by Ciba Geigy) is favorable.
  • photosensitizer DETX-S (trade name, made by Nippon Kayaku Co., Ltd.) is favorable.
  • thermosetting resin bisphenol type epoxy resin
  • bisphenol type epoxy resin there are bisphenol A-type epoxy resin and bisphenol F-type epoxy resin.
  • the former is used in case of improving the resistance to base, and the latter is used in case of decreasing the viscosity (i.e. improvement of applicability).
  • a polyvalent acrylic monomer can be used because it can improve the resolution.
  • polyvalent acrylic monomers such as DPE-6A (trade name, made by Nippon Kayaku Co., Ltd.), R-604 (trade name, made by Kyoeisha Kagaku Co., Ltd) and the like.
  • the solder resist composition may contain a coloring matter, a pigment and the like for shielding the wiring pattern.
  • a coloring matter it is desirable to use phthalocyanine blue.
  • the solder resist composition is favorable to have a viscosity of 0.5 ⁇ 10 Pa ⁇ s, preferably 1 ⁇ 10 Pa ⁇ s at 25°C for facilitating the application through a roll coater.
  • an opening portion can be formed by light exposure and developing treatment.
  • the production method of the printed wiring board according to the invention will be described below. This method is mainly carried out by a semi-additive process, but a full-additive process can be adopted.
  • a wiring board is first prepared by forming conductor circuit as a solder pad on a surface of a substrate.
  • a resin insulating substrate such as a glass epoxy resin substrate, a polyimide substrate, a bismaleimide triazine substrate or the like, a ceramic substrate, a metal substrate and so on.
  • Such a wiring board may be a multilayer printed wiring board provided in its interior with plural layers of conductor circuit.
  • a method of forming such plural conductor circuit layers for example, there is a method of forming an adhesive layer made of an adhesive for electroless plating as an interlaminar insulating resin layer on an underlayer conductor circuit formed on the substrate, roughening the surface thereof, subjecting the whole of the roughened surface to an electroless thin plating, forming a plating resist thereon, subjecting portions not forming the plating resist to an electrolytic thick plating, removing the plating resist and etching to form a conductor circuit of two layers consisting of the electroless plated film and the electrolytic plated film.
  • the conductor circuit is preferable to be a copper pattern.
  • the adhesive for electroless plating is optimum to be formed by dispersing cured heat-resistant resin particles soluble in an acid or an oxidizing agent into an uncured heat-resistant resin hardly soluble in the acid or oxidizing agent. These heat-resistant resin particles are removed by treating with the acid or oxidizing agent, whereby a roughened surface having octopus pot-shaped anchors is formed.
  • the adhesive for electroless plating may be constituted with two layers having different compositions.
  • the cured heat-resistant resin particles soluble in the acid or oxidizing agent it is desirable to use at least one selected from the group consisting of (1) heat-resistant resin particles having an average particle size of not more than 10 ⁇ m, (2) aggregate particles of heat-resistant resin powder having an average particle size of not more than 2 ⁇ m, (3) a mixture of heat-resistant resin powder having an average particle size of 2 ⁇ 10 ⁇ m and heat-resistant resin powder having an average particle size of less than 2 ⁇ m, (4) false particles obtained by adhering at least one of heat-resistant resin powder and inorganic powder having an average particle size of not more than 2 ⁇ m to the surface of heat-resistant resin powder having an average particle size of 2 ⁇ 10 ⁇ m, (5) a mixture of heat-resistant resin powder having an average particle size of 0.1 ⁇ 0.8 ⁇ m and heat-resistant resin powder having an average particle size of more than 0.8 ⁇ m but less than 2 ⁇ m, and (6) heat-resistant resin powder having an average particle size of 0.1 ⁇ 1.0 ⁇ m.
  • the amount of the heat-resistant resin particles used is 5 ⁇ 50% by weight, preferably 10 ⁇ 40% by weight based on solid content of a matrix made of the heat-resistant resin.
  • the resin forming the heat-resistant resin particles it is preferable to use amino resin (melamine resin, urea resin, guanamine resin and the like), epoxy resin and so on.
  • the uncured heat-resistant resin hardly soluble in the acid or oxidizing agent, it is desirable to use a resin composite of thermosetting resin and thermoplastic resin, or a resin composite of photosensitive resin and thermoplastic resin.
  • the former is high in the heat resistance, while the latter can form an opening for via-hole through photolithography.
  • thermosetting resin use may be made of epoxy resin, phenolic resin, polyimide resin and the like. In case of photosensitizing this resin, thermosetting group is acrylated with acrylic acid or methacrylic acid. Particularly, an acrylate of epoxy resin is most suitable.
  • epoxy resin use may be made of novolac type epoxy resin such as phenol novolac type epoxy resin, cresol novolac type epoxy resin or the like, and an alicyclic epoxy resin modified with dicyclopentadiene and so on.
  • thermoplastic resin use may be made of polyether sulphone (PES), polysulphone (PSF), polyphenylene sulphone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyether imide (PI) and so on.
  • PES polyether sulphone
  • PPS polysulphone
  • PPS polyphenylene sulphone
  • PPES polyphenylene sulfide
  • PPE polyphenyl ether
  • PI polyether imide
  • thermosetting resin photosensitive resin
  • thermoplastic resin thermoplastic resin
  • the adhesive for electroless plating is cured to from an interlaminar insulating resin layer, while an opening for the formation of via-hole is formed on the interlaminar insulating resin layer.
  • the opening for the formation of via-hole is formed by using a laser beam, an oxygen plasma or the like when the resin matrix of the adhesive for electroless plating is a thermosetting resin, or by light exposure and developing treatment when the resin matrix is a photosensitive resin. Moreover, the light exposure and developing treatment are carried out after a photomask depicted with circle patter for the formation of via-hole (glass substrate is favorable) is placed on the photosensitive interlaminar insulating resin layer so as to close the side of the circle pattern to the layer.
  • the surface of the interlaminar insulating resin layer provided with the opening for the formation of via-hole is roughened.
  • the surface of the adhesive layer is roughened by dissolving and removing the heat-resistant resin particles existing on the surface of the adhesive layer for electroless plating with an acid or oxidizing agent.
  • the roughened surface is formed on the interlaminar insulating resin layer.
  • the acid use may be made of inorganic acids such as phosphoric acid, hydrochloric acid, sulfuric acid and the like, or organic acids such as formic acid, acetic acid and the like. Particularly, the use of the organic acid is desirable because it hardly corrodes the metal conductor layer exposed from the via-hole.
  • the oxidizing agent it is desirable to use chromic acid, chromium sulfate and permanganate (potassium permanganate and the like).
  • Rmax maximum roughness
  • the roughness exceeds the upper limit, the interlaminar insulating resin layer itself is apt to be damaged or peeled off, while when it is less than lower limit, the adhesion property lowers.
  • the roughness is favorably 0.1 ⁇ 5 ⁇ m in the semi-additive process because the electroless plated film is removed while ensuring the adhesion property.
  • the electroless plated film is preferably an electroless copper plated film and has a thickness of 1 ⁇ 5 ⁇ m, desirably 2 ⁇ 3 ⁇ m.
  • a photosensitive resin film (dry film) is laminated onto the thus formed electroless plated film and a photomask depicted with a plating resist pattern (glass substrate is favorable) is placed on the photosensitive resin film, which is subjected to a light exposure and a developing treatment to from non-conductor portions corresponding to the plating resist pattern.
  • an electrolytic plated film is formed on the electroless plated film other than the non-conductor portions to from conductor circuits and conductor portions corresponding to via-holes.
  • the electrolytic plating it is desirable to use an electrolytic copper plating, and the thickness of the electrolytic plated film is favorably 5 ⁇ 20 ⁇ m.
  • the electroless plated film is further removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution of sodium persulfate, ammonium persulfate, iron chloride, copper chloride or the like, whereby there are obtained independent conductor circuits and via-hole each comprising two layers of the electroless plated film and the electrolytic plated film.
  • the catalyst nucleus existing on the roughened surface exposed from the non-conductor portions is dissolved and removed with a mixed solution of chromic acid, sulfuric acid and hydrogen peroxide or the like.
  • roughened surface according to the invention is formed on the conductor circuits for solder pad as a surface layer.
  • a roughened surface can be formed by spraying an etching solution comprising copper(II) complex of azole and an organic acid as previously mentioned to the surface of the conductor circuit, or by immersing the conductor circuit in such an etching solution and then bubbling it.
  • the conductor circuit is desirable to be the electroless plated film or the electrolytic plated film because it is difficult to form a roughened surface in a conductor circuit formed by etching a rolled copper foil.
  • the thus formed roughened surface may be subjected to an etching treatment, polishing treatment, oxidation treatment, oxidation-reduction treatment and the like, or may be covered with a plated film at subsequent steps.
  • the roughened surface may be covered with a metal layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal.
  • a metal layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal.
  • plating either one of electrolytic plating, electroless plating and substitution plating
  • vapor deposition electrophoretic deposition
  • sputtering or the like.
  • the roughened surface to be provided with the rust proof layer according to the invention is favorable to be formed at a maximum height of 0.5 ⁇ 10 ⁇ m, preferably 1 ⁇ 5 ⁇ m through oxidation-reduction treatment, electroless plating or etching treatment.
  • the etching there is a method of spraying an aqueous solution of copper(II) complex of azole and organic acid as an etching solution to the surface of the conductor circuit or a method of immersing the conductor circuit in the above etching solution and bubbling it.
  • a metal layer for rust proof layer made of at least one metal selected from the group consisting of titanium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead, bismuth and noble metal. This is carried out by plating (either one of electrolytic plating, electroless plating and substitution plating), vapor deposition, electrophoretic deposition or sputtering.
  • a rust proof layer may be formed on the above roughened surface or the metal layer for rust proof layer.
  • the formation of the rust proof layer is carried out by applying an anti-rust agent, or by spraying the anti-rust agent, or by immersing the conductor circuit for solder pad in the anti-rust agent.
  • the immersion method is favorable because it can evenly form the rust proof layer over the conductor circuit without damaging the roughened surface for the rust proof layer.
  • the rust proof layer can be formed on the roughened surface of the conductor circuit for solder pad or on the metal layer for rust proof layer formed on the roughened surface by immersing the roughened surface or the metal layer for rust proof layer in a tank with a depth fully immersing the conductor circuit of the printed wiring board at a temperature of 20 ⁇ 60°C for an immersing time of 10 ⁇ 600 seconds.
  • solder resist layer is formed on the conductor circuit having the above treated roughened surface.
  • a maximum particle size is not more than a thickness (15 ⁇ m) of an innerlayer copper patter as mentioned below) and 1.5 parts by weight a leveling agent (Perenol S4, trade name, made by Sannopuco Co., Ltd.) with stirring to adjust a viscosity of the resulting mixture to 45,000-49,000 cps at 23 ⁇ 1°C.
  • a leveling agent Perenol S4, trade name, made by Sannopuco Co., Ltd.
  • An embodiment of the printed wiring board according to the invention is produced according to a series of production steps shown in Figs. 15 to 32 .
  • a copper clad laminate 6 obtained by laminating a copper foil 5 of 18 ⁇ m in thickness onto each surface of a substrate 4 made of a glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm as shown in Fig. 15 .
  • the copper clad laminate 6 is subjected to an electroless plating after the formation of a drilled hole 7 as shown in Fig. 16 , and etched in form of a pattern to form innerlayer copper pattern (underlayer conductor circuits) 8 and a through-hole 9 on both surfaces of the substrate 6.
  • the substrate provided with the innerlayer copper pattern 8 and the through-hole 9 is washed with water, dried and subjected to an oxidation-reduction treatment using NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath) and NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath to form roughened surfaces 10, 11 on the innerlayer copper pattern 8 and the surface of the through-hole 9, whereby there is produced a wiring board 12 as shown in Fig. 16 .
  • a resin filler is prepared by mixing and kneading the resin composition G and the curing agent composition H.
  • the resin filler is applied onto both surfaces of the board 12 by means of a roll coater to fill in spaces between the conductor circuits 8 and the through-hole 9, which is dried by heating at 70°C for 20 minutes to form resin layers 13, 14.
  • a surface of the board is polished by a belt sander polishing with #600 belt polishing paper (made by Sankyo Rikagaku Co., Ltd.) so as not to leave the resin filler on the surface of the innerlayer copper pattern 8 and the surface of a land 11 of the through-hole 9 and buffed for removing flaws created by the belt sander polishing.
  • the other surface of the board is carried out in the same treatment as mentioned above.
  • the resin filler is cured by heating at 100°C for 1 hour, 120°C for 3 hours, 150°C for 1 hour and 180°C for 7 hours to form a wiring board 15 as shown in Fig. 17 .
  • the roughened surfaces 10, 11 on the surface layer portion of the resin filler filled in the through-hole 9 and the like and the upper surface of the innerlayer conductor circuit 8 are removed to smoothen the surface of the board, while the resin layer 13, the side face of the innerlayer conductor circuit 8 and the land surface of the through-hole 9 are strongly adhered to each other through the roughened surfaces 10a, 11 a and the inner wall face of the through-hole 9 and the resin layer 14 are strongly adhered to each other through the roughened surface 11a.
  • the printed wiring board 15 provided with the conductor circuits is degreased with an alkali, soft etched, treated with a catalyst solution containing palladium chloride and an organic acid to form a Pd. catalyst.
  • a surfactant Surfeel 465, trade name, made by Nisshin Kagaku Kogyo Co., Ltd.
  • the interlaminar resin insulating agent (for underlayer) having the viscosity of 1.5 Pa ⁇ s of the above item (7) is applied onto both surfaces of the board 18 of the item (6) by means of a roll coater within 24 hours after the preparation, left to stand at a horizontal state for 20 minutes and dried (baked) at 60°C for 30 minutes. Then, the photosensitive adhesive solution (for upperlayer) having the viscosity of 7 Pa ⁇ s of the item (7) is applied within 24 hours after the preparation, left to stand at a horizontal state for 20 minutes and dried (baked) at 60°C for 30 minutes to form an adhesive layer 19 having a thickness of 35 ⁇ m as shown in Fig. 19 . (9) As shown in Fig.
  • a photomask film 21 depicted with black circles of 85 ⁇ m ⁇ is adhered to each surface of the board provided with the adhesive layer 19 in the item (8) and exposed to a super-high pressure mercury lamp at 500 mJ/cm 2 .
  • the board is developed by spraying DMTG solution, exposed to a super-high pressure mercury lamp at 3000 mJ/cm 2 , and subjected to a heating treatment (post baking) at 100°C for 1 hour, 120°C for 1 hour and 150°C for 3 hours, whereby an interlaminar resin insulating layer (two-layer structure) 19 of 35 ⁇ m in thickness having an opening (opening for the formation of via-hole) 22 of 85 ⁇ m ⁇ with an excellent size accuracy corresponding to the photomask film 21 as shown in Fig. 21 . Moreover, the tin plated layer is partly exposed in the opening 22 for the via-hole.
  • the board provided with the opening 22 is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles existing on the surface of the interlaminar resin insulating layer 19 to thereby roughen the surface of the interlaminar resin insulating layer 19, whereby the roughened surfaces 23, 24 are formed as shown in Fig. 22 . Thereafter, it is immersed in a neutral solution (made by Shipley) and washed with water. Furthermore, a palladium catalyst (made by Atotech) is applied to the surface of the board subjected to the roughening treatment (roughened depth: 6 ⁇ m) to give a catalyst nucleus to the surface 23 of the interlaminar resin insulating layer 19 and the inner wall face 24 of the opening for the via-hole.
  • the thus formed wiring board is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plated film 25 of 0.6 ⁇ m over a whole of the roughened surface as shown in Fig. 23 .
  • electroless plating aqueous solution EDTA 50 g/L Copper sulfate 10 g/L HCHO 8 mL/L NaOH 10 g/L ⁇ , ⁇ '-bipyridyl 80 mg/L PEG 0.1 g/L
  • Electroless plating conditions Liquid temperature of 70°C, 30 minutes (12) As shown in Fig.
  • a commercially available photosensitive dry film 27 depicted with black circles 26 is attached to the electroless copper plated film 25 formed in the item (11) and a mask is placed thereon, which is exposed to a light at 100 mJ/cm2 and developed with 0.8% sodium carbonate to form plating resists 28 of 15 ⁇ m in thickness as shown in Fig. 25 . (13) Then, portions not forming the plating resist are subjected to an electrolytic copper plating under the following conditions to form an electrolytic copper plated film 29 of 15 ⁇ m in thickness as shown in Fig. 26 .
  • Electrolytic plating aqueous solution Sulfuric acid 180 g/L Copper sulfate 80 g/L Additive (Kaparasid GL, trade name, made by Atotech Japan) 1 mL/L [Electrolytic plating conditions] Current density 1 A/dm 2 Time 30 minutes Temperature room temperature (14) After the plating resist 28 is peeled and removed with 5% KOH, the electroless plated film 25 beneath the plating resist 28 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to from conductor circuits 30 of 18 ⁇ m in thickness comprised of the electroless copper plated film 25 and the electrolytic copper plated film 29 (including via-hole 31) as shown in Fig. 27 .
  • a composition for solder resist is obtained by mixing 46.67 g of a photosensitizing oligomer (molecular weight: 4000) wherein 50% of epoxy group of 60% by weight of cresol novolac type epoxy resin (made by Nippon Kayaku Co., Ltd.) dissolved in DMDG, 15.0 g of 80% by weight of bisphenol A-type epoxy resin (Epikote 1001, trade name, made by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 1.6 g of an imidazole curing agent (made by Shikoku Kasei Co., Ltd.
  • 2E4MZ-CN 3 g of a polyvalent acrylic monomer as a photosensitive monomer, 1.5 g of polyvalent acrylic monomer (made by Kyoeisha Kagaku Co., Ltd. DPE6A) and 0.71 g of a dispersion anti-foaming agent (made by Sannopuco Co., Ltd. S-65) and adding 2 g of benzophenone (made by Kanto Kagaku Co., Ltd.) as a photoinitiator and 0.2 g of Michler ketone (made by Kanto Kagaku Co., Ltd.) as a photosensitizer to the resulting mixture to adjust the viscosity to 2.0 Pa ⁇ s at 25°C.
  • a polyvalent acrylic monomer made by Kyoeisha Kagaku Co., Ltd. DPE6A
  • a dispersion anti-foaming agent made by Sannopuco Co., Ltd. S-65
  • benzophenone made by Kanto Kagaku Co., Ltd.
  • the viscosity is measured by B-type viscometer using rotor No. 4 at 60 rpm and rotor No. 3 at 6 rpm.
  • the composition 33 for solder resist is applied at a thickness of 20 ⁇ m to both surfaces of the multilayer wiring board obtained in the item (16).
  • a photomask film 35 of 5 mm in thickness depicted with a circle pattern (mask pattern) 34 is placed thereonto, exposed to a ultraviolet ray at 1000 mJ/cm 2 and developed with DMDG as shown in Fig. 30 .
  • solder resist layer 38 (thickness: 20 ⁇ m) opened (opening diameter: 200 ⁇ m) to a solder pad portion 36 (including a via-hole and its land portion 37) as shown in Fig. 31 , whereby a printed wiring board is produced.
  • the board is immersed in an electroless gold plating solution containing 2 g/L of potassium gold cyanide, 75 g/L of ammonium chloride, 50 g/L of sodium citrate and 10 g/L of sodium hypophosphite at 93°C for 23 seconds to form a gold plated layer 41 of 0.03 ⁇ m on the nickel plated layer 40.
  • an electroless gold plating solution containing 2 g/L of potassium gold cyanide, 75 g/L of ammonium chloride, 50 g/L of sodium citrate and 10 g/L of sodium hypophosphite at 93°C for 23 seconds to form a gold plated layer 41 of 0.03 ⁇ m on the nickel plated layer 40.
  • a solder paste is printed on the opening portion of the solder resist layer 38 and reflowed at 200°C to form solder bumps (solder body) 42, whereby a printed wiring board 43 having the solder bumps 42 is produced.
  • this printed wiring board are disposed usual wiring portion (line width: 75 ⁇ m) and fine wiring portion (line width: 50 ⁇ m), and further the fine wiring portion is divided into portions having a coarse wiring density (distance: 400 ⁇ m) and portions having a dense wiring density (distance: 50 ⁇ m).
  • Fig. 33 is a diagrammatically section view of a printed wiring board 44.
  • the production steps are fundamentally the same as in Example 1, except that the roughened surface in the surface layer conductor circuits (conductor circuits for solder pad) is covered with a metal layer 51 as shown in Figs. 9 ⁇ 12 at the step (17).
  • the metal nickel is used, which is applied by an electroless plating.
  • the thus formed nickel layer has a thickness of 0.04 ⁇ m.
  • solder bumps (solder body) 54 are formed on the opening portions of the solder resist layer 38 through the nickel plated layer 52 on the nickel layer 51 and the gold plated layer 53 thereon as shown in Fig. 33 at the steps (18) ⁇ (21).
  • Example 2 This example is fundamentally the same as in Example 2 except that tin layer through substitution plating is used instead of the nickel layer through the electroless plating as a metal layer covering the roughened surface of the conductor circuits for solder pad.
  • This tin layer has a thickness of 0.03 ⁇ m.
  • This example is fundamentally the same as in Example 2 except that zinc layer through electroless plating is used instead of the nickel layer through the electroless plating as a metal layer covering the roughened surface of the conductor circuits for solder pad.
  • This zinc layer has a thickness of 0.05 ⁇ m.
  • This example is fundamentally the same as in Example 2 except that a metal layer through vapor deposition is used instead of the nickel layer through the electroless plating as a metal layer covering the roughened surface of the conductor circuits for solder pad.
  • This metal layer is made of iron and cobalt and has a thickness of 0.05 ⁇ m.
  • a printed wiring board 45 shown in Fig. 34 is produced through the following steps.
  • This example is fundamentally the same as in Example 6 except that the formation of the roughened surface is carried out by etching with an etching solution containing 10 parts by weight of imidazole copper(II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, i.e. "Mechetchbond", trade name, made by Mech Corporation under spraying while transferring through rolls to obtain a roughened surface having a thickness of 3 ⁇ m. Thereafter, the rust proof layer is formed on the roughened surface by spraying the same anti-rust agent as in Example 6 at room temperature.
  • an etching solution containing 10 parts by weight of imidazole copper(II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, i.e. "Mechetchbond", trade name, made by Mech Corporation under spraying while transferring through rolls to obtain a roughened surface having a thickness of 3 ⁇ m.
  • the rust proof layer is formed on the roughened surface by spraying the same anti-rust agent as
  • Example 6 This example is fundamentally the same as in Example 6 except that the roughened surface having a maximum height of 3 ⁇ m is formed by graphitization-reduction treatment using NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath) and NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath. Thereafter, a rust proof layer is formed on the roughened surface by applying a solution of 10% by weight of tollyltriazole as an anti-rust agent to both surfaces through a roll coater.
  • Fig. 35 is a partial section view of a printed wiring board 46 in this example.
  • This board is produced in the same manner as in Example 6 except that tin layer 109 having a thickness of 0.03 ⁇ m is formed by substitution plating after the formation of the roughened layer 39 and then a rust proof layer 110 is formed on the tin layer 109 by immersing the tin layer 109 of the conductor circuit for solder pad in a solution containing 10% by weight of tollyltriazole as an anti-rust agent at a temperature of 50°C for 1 minute.
  • Example 6 This example is fundamentally the same as in Example 6 except that the roughened surface having a maximum height of 3 ⁇ m is formed by etching with an etching solution containing 10 parts by weight of imidazole copper(II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, i.e. "Mechetchbond", trade name, made by Mech Corporation under spraying while transferring through rolls.
  • a nickel layer having a thickness of 0.04 ⁇ m is formed on the roughened surface by electroless plating.
  • a rust proof layer is formed on the roughened surface by immersing the nickel layer in a solution containing 5% by weight of 1,2,3-benzotriazole and 5% by weight of tollyltriazole as an anti-rust agent at a temperature of 55°C for 45 seconds.
  • Example 6 This example is fundamentally the same as in Example 6 except that the roughened surface having a maximum height of 3 ⁇ m is formed by graphitization-reduction treatment using NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath) and NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath.
  • zinc layer having a thickness of 0.05 ⁇ m is formed on the resulting roughened surface by sputtering and a rust proof layer is formed thereon by spraying a solution containing 5% by weight of 1,2,3-benzotriazole and 5% by weight of tollyltriazole as an anti-rust agent onto the zinc layer at room temperature.
  • the roughened surface is formed on the conductor circuit as a surface layer by graphitization-reduction treatment using NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath) and NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath
  • Example 2 This example is fundamentally the same as in Example 2 except that the roughened surface is formed on the conductor circuit as a surface layer by graphitization-reduction treatment using NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath) and NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath.
  • NaOH (10 g/L), NaClO 2 (40 g/L) and Na 3 PO 4 (6 g/L) as an oxidation bath (graphitization bath)
  • NaOH (10 g/L) and NaBH 4 (6 g/L) as a reduction bath.
  • usual wiring portions and fine wiring portions as well as coarse wiring density portion and dense wiring density portion are formed likewise Example 1.
  • a surfactant Surfeel 465, trade name, made by Nisshin Kagaku Kogyo Co., Ltd.
  • Example 6 This example is fundamentally the same as in Example 6 except that the anti-rust agent is not applied to the roughened surface.
  • Example 7 This example is fundamentally the same as in Example 7 except that the roughened surface having a maximum height of 3 ⁇ m is formed by etching with an etching solution containing 10 parts by weight of imidazole copper(II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, i.e. "Mechetchbond”, trade name, made by Mech Corporation under spraying while transferring through rolls and the anti-rust agent is not applied to the roughened surface.
  • an etching solution containing 10 parts by weight of imidazole copper(II) complex, 7 parts by weight of glycolic acid and 5 parts by weight of potassium chloride, i.e. "Mechetchbond”, trade name, made by Mech Corporation under spraying while transferring through rolls and the anti-rust agent is not applied to the roughened surface.
  • Example 1 With respect to the printed wiring boards produced in Example 1 and Comparative Examples 1 and 2, the peeling test of solder resist layer is carried out after the formation of the solder resist layer and after a reliability test (under heat cycle condition). Moreover, the presence of bad continuity between conductor circuits is compared between the coarse and dense wiring density portions and also organic residue at the bottom of the opening portion is measured. The results are shown in Table 1.
  • *2 a cut section is observed by means of a microscope (x 50).
  • * 3 confirmed continuity between solder bump and BGA pad. good in the case that value of contact resistance is not more than 1 ⁇ , bad in the case that value of contact resistance exceeds 1 ⁇ *4: when a top of a pull tester is attached to the solder bump and pulled up vertically, a numerical value of the pull tester is read at a time of taking out the solder bump.
  • the peeling, cracking and the like of the solder resist layer and the solder bump are inspected after the formation of the solder bump and after the reliability test (under heat cycle condition), and the shear strength of the solder bump is measured, and the continuity test through a checker is carried out to judge the presence of wiring breakage and short-circuit.
  • the results are shown in Tables 3 and 4.
  • *2 a cut section is observed by means of a microscope (x 50). *3: confirmed continuity between solder bump and BGA pad. good in the case that value of contact resistance is not more than 1 ⁇ , bad in the case that value of contact resistance exceeds 1 ⁇ *4: when a top of a pull tester is attached to the solder bump and pulled up vertically, a numerical value of the pull tester is read at a time of taking out the solder bump.
  • *2 a cut section is observed by means of a microscope (x 50). *3: confirmed continuity between solder bump and BGA pad. good in the case that value of contact resistance is not more than 1 ⁇ , bad in the case that value of contact resistance exceeds 1 ⁇ *4: when a top of a pull tester is attached to the solder bump and pulled up vertically, a numerical value of the pull tester is read at a time of taking out the solder bump.
  • the resin residue is observed in the printed wiring boards of the comparative examples, while the resin residue is not observed in the printed wiring boards of the examples. Further, as shown in Tables 3 and 4, in the printed wiring boards of Examples 6 ⁇ 11, no peeling and cracking of the solder resist layer and the solder bump is caused and the continuity and shear strength of solder bump are excellent as compared with the printed wiring boards of Comparative Examples 5 and 6. And also, the strength between the solder resist layer and the solder bump is sufficiently maintained and the wiring breakage and short-circuit are not caused even after the reliability test.
  • the roughened surface having a given shape is formed on the surface of the conductor circuit for solder pad and the solder resist layer is strongly adhered thereto through the roughened surface, so that the sufficient adhesion property between the conductor circuit and the solder resist layer can be ensured when the solder resist layer is removed in portions forming the solder bumps to decrease the contact area between the conductor circuit and the solder resist layer or even when the conductor circuit is comprised of fine wiring and the wiring density is coarse.
  • the residue of the solder resist forming resin is not left on the roughened surface exposing to the opening portion for the formation of the solder bump, so that the adhesion property to the metal beneath the solder bump is excellent and the bad continuity is not caused in the portions forming the solder bumps.
  • the shape and strength having excellent adhesion properties to the solder resist layer and to the metal beneath the solder bump are held by covering the roughened surface of the conductor circuit for solder pad with the metal layer, so that the strength of the solder bump is considerably increased and the dropping off of the solder bump can be prevented.
  • the roughened surface of the conductor circuit for solder pad is protected with the rust proof layer to prevent the deterioration of the conductor circuit for solder pad and to maintain the shape of the roughened surface having excellent adhesion properties to the solder resist layer and to the solder pad, so that when the conductor circuits for solder pad are finely wired and formed at a coarse wiring density, the adhesion property between the conductor circuit and the solder resist layer is enhanced, and even when the portions forming the solder bumps are exposed to a high temperature or a high pressure, the bad continuity is not caused in the solder bump forming portions because the conductor circuit is strongly adhered to the solder resist layer without peeling.
  • the roughened surface of the conductor circuit for solder pad is covered with the metal layer for rust proof layer made of a given metal and protected with the rust proof layer, so that even when a part of the solder resist layer is opened so as to form a solder pad, the surface of the conductor circuit for solder pad maintains the shape having an excellent adhesion property to the solder pad and the resin for the solder resist layer is not left in the opening portion and hence the adhesion properties and strengths between the conductor circuit for solder pad and the solder resist layer and between the conductor circuit and the solder pad are improved and the solder bump having an excellent adhesion property to the metal beneath the solder bump is formed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Claims (5)

  1. Verfahren zur Herstellung einer gedruckten Leiterbahnplatine, die Leiterbahnschaltungen für Lötaugen, dünne Leitungsführungen, die jeweils eine Leiterbahnbreite von nicht mehr als 50 µm aufweisen, eine auf den Leiterbahnschaltungen für Lötaugen und den dünnen Leitungsführungen ausgeformte Lötstopplackschicht, und einen zur Anordnung eines Lotkörpers in der Lötstopplackschicht ausgeformten Öffnungsteilbereich aufweist, wobei das Verfahren die Schritte aufweist:
    (a) Ausformen einer aufgerauten Oberfläche auf den Leiterbahnschaltungen für Lötaugen und den dünnen Leitungsführungen durch Behandlung mit einer ätzenden Lösung die einen Kupfer II Komplex und eine organische Säure enthält;
    (b) Ausformen der Lötstopplackschicht auf den Leiterbahnschaltungen für Lötaugen und den dünnen Leitungsführungen;
    (c) Ausformen des Öffnungsteilbereichs zum Freilegen der Leiterbahnschaltung für das Lötauge in der Lötstopplackschicht;
    (d) Entfernen eines Harzes, das in der Lötstopplackschicht auf der Leiterbahnschaltung für das Lötauge enthalten ist in dem Öffnungsteilbereich, und
    (e) Ausformen einer Lotperle auf der Leiterbahnschaltung für das Lötauge in dem Öffnungsteilbereich.
  2. Verfahren zur Herstellung einer gedruckten Leiterbahnplatine gemäß Anspruch 1, wobei die Leiterbahnschaltung für das Lötauge und die dünne Leitungsführung eine darauf ausgeformte stromlos aufgebrachte Schicht und eine elektrolytisch aufgebrachte Schicht aufweist.
  3. Verfahren zur Herstellung einer gedruckten Leiterbahnplatine gemäß Anspruch 1, wobei der Öffnungsteilbereich ein Durchgangsloch und dessen Anschlussflächenteil aufweist.
  4. Verfahren zur Herstellung einer gedruckten Leiterbahnplatine gemäß Anspruch 1, das weiterhin das Ausformen einer vergoldeten Schicht auf dem Öffnungsteilbereich aufweist.
  5. Verfahren zur Herstellung einer gedruckten Leiterbahnplatine gemäß Anspruch 1, wobei die aufgeraute Oberfläche durch Bearbeitung unter einem Zustand mit vorhandenem Sauerstoff ausgeformt wird.
EP08075294A 1998-07-08 1999-07-01 Leiterplatte und Herstellungsverfahren dafür Expired - Lifetime EP1940209B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP20867198 1998-07-08
JP11123926A JP2000315854A (ja) 1999-04-30 1999-04-30 プリント配線板とその製造方法
JP11139539A JP2000082871A (ja) 1998-07-08 1999-05-20 プリント配線板及びその製造方法
EP99926882A EP1102523A4 (de) 1998-07-08 1999-07-01 Leiterplatte und verfahren zu ihrer herstellung

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP99926882A Division EP1102523A4 (de) 1998-07-08 1999-07-01 Leiterplatte und verfahren zu ihrer herstellung
EP99926882.4 Division 1999-07-01

Publications (3)

Publication Number Publication Date
EP1940209A2 EP1940209A2 (de) 2008-07-02
EP1940209A3 EP1940209A3 (de) 2009-04-29
EP1940209B1 true EP1940209B1 (de) 2010-06-02

Family

ID=27314829

Family Applications (2)

Application Number Title Priority Date Filing Date
EP99926882A Ceased EP1102523A4 (de) 1998-07-08 1999-07-01 Leiterplatte und verfahren zu ihrer herstellung
EP08075294A Expired - Lifetime EP1940209B1 (de) 1998-07-08 1999-07-01 Leiterplatte und Herstellungsverfahren dafür

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP99926882A Ceased EP1102523A4 (de) 1998-07-08 1999-07-01 Leiterplatte und verfahren zu ihrer herstellung

Country Status (6)

Country Link
EP (2) EP1102523A4 (de)
KR (1) KR100492465B1 (de)
CN (1) CN1316175A (de)
DE (1) DE69942467D1 (de)
TW (2) TW535481B (de)
WO (1) WO2000003570A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100361565B1 (ko) * 1997-07-08 2002-11-22 이비덴 가부시키가이샤 인쇄 배선판 및 이의 제조방법
US7129158B2 (en) 2001-09-28 2006-10-31 Ibiden Co., Ltd. Printed wiring board and production method for printed wiring board
US6843407B2 (en) 2001-10-12 2005-01-18 Asustek Computer, Inc. Solder bump fabrication method and apparatus
AT500807B1 (de) * 2004-01-23 2006-11-15 Austria Tech & System Tech Verfahren zum herstellen eines leiterplattenelements sowie leiterplattenelement
DE102004030800B4 (de) * 2004-06-25 2017-05-18 Epcos Ag Verfahren zur Herstellung einer keramischen Leiterplatte
CN100355327C (zh) * 2005-03-25 2007-12-12 华为技术有限公司 一种印制电路板及其制造方法
CN101810063B (zh) 2008-09-30 2012-10-10 揖斐电株式会社 多层印刷线路板以及多层印刷线路板的制造方法
CN101795537A (zh) * 2010-03-09 2010-08-04 施吉连 一种微波高频电路板防焊印刷工艺
CN102338754A (zh) * 2010-07-22 2012-02-01 牧德科技股份有限公司 电路板的电源层及接地层的缺陷检测方法
CN102560576B (zh) * 2012-02-21 2015-01-14 合肥工业大学 一种作为焊点反应阻挡层的Ni-Cu-P三元合金涂层及其电镀制备工艺
CN103929900A (zh) * 2014-03-31 2014-07-16 深圳崇达多层线路板有限公司 一种断接金手指的制作方法
CN108558413B (zh) * 2018-07-02 2021-05-18 上海安费诺永亿通讯电子有限公司 一种陶瓷基电子线路的制备方法
CN112349695B (zh) * 2020-09-28 2022-04-19 中国电子科技集团公司第二十九研究所 一种四层布线lcp封装基板、制造方法及多芯片系统级封装结构
KR20240009274A (ko) * 2022-07-13 2024-01-22 주식회사 아이에스시 도전성 입자, 도전성 입자의 제조방법 및 검사용 커넥터

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3645772A (en) * 1970-06-30 1972-02-29 Du Pont Process for improving bonding of a photoresist to copper
JPS63126297A (ja) 1986-11-14 1988-05-30 イビデン株式会社 多層プリント配線板並びにそれの製造方法と無電解めっき用絶縁剤
JP2781954B2 (ja) * 1994-03-04 1998-07-30 メック株式会社 銅および銅合金の表面処理剤
CN1117512C (zh) * 1994-12-01 2003-08-06 揖斐电株式会社 多层印刷电路板及其制造方法
JPH08242064A (ja) * 1995-03-01 1996-09-17 Ibiden Co Ltd プリント配線板
JP2923524B2 (ja) * 1995-08-01 1999-07-26 メック株式会社 銅および銅合金のマイクロエッチング剤並びにマイクロエッチング方法
JP3229923B2 (ja) * 1996-03-01 2001-11-19 イビデン株式会社 多層プリント配線板およびその製造方法
EP1802186B1 (de) * 1996-11-20 2011-05-11 Ibiden Co., Ltd. Leiterplatte

Also Published As

Publication number Publication date
WO2000003570A1 (fr) 2000-01-20
DE69942467D1 (de) 2010-07-15
EP1940209A2 (de) 2008-07-02
CN1316175A (zh) 2001-10-03
EP1940209A3 (de) 2009-04-29
KR100492465B1 (ko) 2005-05-31
EP1102523A1 (de) 2001-05-23
KR20010083090A (ko) 2001-08-31
EP1102523A4 (de) 2005-11-30
TW535480B (en) 2003-06-01
TW535481B (en) 2003-06-01

Similar Documents

Publication Publication Date Title
EP0999731B1 (de) Gedruckte Leiterplatte umfassend Leiterbahnen für Lot-Anschlußflächen
US6376052B1 (en) Multilayer printed wiring board and its production process, resin composition for filling through-hole
EP0952762B1 (de) Leiterplatte und verfahren zur herstellung dieser
EP1940209B1 (de) Leiterplatte und Herstellungsverfahren dafür
US6762921B1 (en) Multilayer printed-circuit board and method of manufacture
EP1035758A1 (de) Klebstoff zur stromlosen plattierung, rohstoffzusammensetzung zur herstellung eines klebstoffs zur stromlosen plattierung und gedruckte leiterplatte
JP4511626B2 (ja) 多層プリント配線板の製造方法
EP1194025B1 (de) Mehrschichtige leiterplatte
JP4746252B2 (ja) 多層プリント配線板
JP4321913B2 (ja) プリント配線板
JP2000315854A (ja) プリント配線板とその製造方法
JP2000332395A (ja) プリント配線板
JP2000022309A (ja) プリント配線板
JP3995794B2 (ja) 無電解めっき用接着剤およびプリント配線板
EP1656004B1 (de) Mehrschichtige gedruckte Leiterplatte und ihr Herstellungsverfahren
JP2000082871A (ja) プリント配線板及びその製造方法
JP2002208775A (ja) プリント配線板
JP2000252622A (ja) プリント配線板およびその製造方法
JP2000327934A (ja) 粗化面形成用樹脂組成物およびプリント配線板
JP2000269652A (ja) プリント配線板

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080414

AC Divisional application: reference to earlier application

Ref document number: 1102523

Country of ref document: EP

Kind code of ref document: P

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FI GB NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FI GB NL

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

AKX Designation fees paid

Designated state(s): DE FI GB NL

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AC Divisional application: reference to earlier application

Ref document number: 1102523

Country of ref document: EP

Kind code of ref document: P

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FI GB NL

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 69942467

Country of ref document: DE

Date of ref document: 20100715

Kind code of ref document: P

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20100602

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100602

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100602

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20110303

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 69942467

Country of ref document: DE

Effective date: 20110302

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20120627

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20120627

Year of fee payment: 14

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20130701

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69942467

Country of ref document: DE

Effective date: 20140201

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140201

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20130701