Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/762—Charge transfer devices
  • H01L29/765—Charge-coupled devices
  • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
  • H01L29/76816—Output structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14806—Structural or functional details thereof
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
  • H04N23/95—Computational photography systems, e.g. light-field imaging systems
  • H04N23/951—Computational photography systems, e.g. light-field imaging systems by using two or more images to influence resolution, frame rate or aspect ratio
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/42—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/50—Control of the SSIS exposure
  • H04N25/57—Control of the dynamic range
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/711—Time delay and integration [TDI] registers; TDI shift registers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14825—Linear CCD imagers

Definitions

• a CCD device can be defined as being a semiconductor device wherein, due to the movement of electric charges, storage and collection of charges is possible. These charge transfer devices are used in dynamic, variable storage elements, which characteristically have a high information density.
• CCD sensors intended for X-ray imaging the charges used for image generation, which are formed on physical pixels, can be combined, binned. Binning in a CCD sensor produces virtually larger image pixels. However, in certain situations, handling the charge of these combined pixels may be problematic. Especially at higher signal levels, the signal coming from the image area may be so large that, with the selected binning, the charges can not be combined within the CCD sensor without a risk of satura- tion of the output amplifier.
• sensitivity may refer to resolution within background noise, in other words, to the signal size that can be resolved from background noise.
• a typical non-cooled CCD device working in MPP mode has a dynamic range of about 10.000:1 ... 20.000:1.
• the figure giving the dynamic range represents the ratio of saturation voltage to RMS noise. If this dynamic range is effectively utilized, then it will be possible to exploit as many greyness
• CONFIRMATION levels as the A/D conversion used allows For example, in the case of 14 bits, the total number of greyness levels available will be 16.384.
• the signal amplifier and A/D converter (A/D, Analog-to-Digital) connected after the sensor are designed with an aim to enable the entire dynamic range produced by the CCD sensor to be utilized.
• A/D Analog-to-Digital
• the quantization step of the A/D converter is slightly below the CCD sensor's own noise level.
• the charge received and contained in a pixel may be so large that it can not be handled in a binning situation in the read-out register and/or in the charge well of the output amplifier without a risk of saturation.
• the method and system of the invention have the advantage of making it possible to expand the dynamic range of the CCD sensor and thus to prevent the sensor or a part of it from getting saturated.
• Fig. 1 presents a device for increasing the dynamics according to a preferred embodiment
• Fig. 2 illustrates the structure of image data
• Fig. 3 presents by way of example a method for performing imaging and a logic for controlling the AGC function of an FPGA device during imaging
• Fig. 4 presents a table showing the typical charge handling capaci- ties of the CCD sensor used
• 2x2 binning 2 pixels having a 50-% charge can be summed to one output A and 3 pixels with a 100-% charge to a second output B without overflow.
• 3x3 binning 3 pixels having 44% of the charge can be summed to output A and 3 pixels having 88% of the charge to output B without overflow.
• 4x4 binning 4 pixels with a 25-% charge can be summed to output A and 4 pixels with a 50-% charge can be summed to output B without overflow.
• Fig. 1 presents a CCD sensor for increasing the dynamics according to a preferred embodiment.
• reference number 1-1 represents an entire CCD sensor module, a detector.
• the active area of the detector, which com- prises charge-receiving pixels, is indicated by reference number 1-2.
• This image-forming surface in question may be a substantially even structure of any shape.
• the image information of a two-dimensional CCD sensor can be read out using a read-out register 1-4 placed on at least one edge, the register being functionally connected with said active area. Into this register it is possible to load e.g. one pixel column at a time.
• the pixels in the pixel col- umn may be combined with each other, i.e. binned.
• the sensor also comprises means for transferring the charges to an output 1-4a, 1-4b of the read-out register 1-4. After the transfer, the register can be read e.g. serially by transferring the charge one pixel at a time, binned or without binning, into a charge well 1- 6, 1-8 of the output amplifier, from where it can be further transferred out 1-10, 1-2 from the CCD sensor 1 -1.
• the charges can be transferred in the register in a desired direction, in the direction of a lower-capacity output well or in the direction of a higher-capacity output well.
• the choice of the output well to be used during imaging is optimized dynamically during im- aging, so that the output well to be used and/or the size of the binning are/is selected e.g. by electronics, a suitable selection program or a combination of these.
• An output well 1-6, 1-8 of the output amplifier may be located at either end of the register 1-4, or alternatively two or more wells and/or amplifiers may be placed at one end of the register or at least one well may be placed at each end of the register.
• the read-out register has at each end of it at least one charge well, read-out well 1-6, 1-8 and amplifier functionally connected with it.
• An amplifier and/or buffer and/or buffer amplifier may be functionally connected with the well.
• the dual amplifiers in question may be designed for different uses.
• one of the amplifiers can be optimized for a so-called slow-scan mode, in which case the noise can be optimized to be as small as possible at the cost of speed.
• the other amplifier may be optimized for a so-called high- speed mode, in which case the reading rate can be optimized to be as fast as possible, but at the cost of noise.
• the output amplifier's charge wells have had the same capacity.
• at least two output wells having different capacities are pro- symbolized.
• the capacities preferably differ from each other substantially e.g. so that the larger output well has a capacity about twice that of the smaller output well. Other ratios can be used as well. If the number of wells is greater than two, then the capacities of at least two wells may differ from each other.
• the invention and its preferred embodiments are based on the use of at least two charge wells of different capacities and on the possibility of dynamically selecting during read-out the output well to be used. This selection can be made depending on the signal, on the basis of signal data, e.g. image signal.
• this arrangement provides the advantage of allowing saturation of the internal shift wells and read-out wells (not of the image area) of the CCD sensor to be avoided.
• the A/D converter can be prevented from beingsaturated. Both situations are very likely to occur when the charges of pixels are being com- bined, i.e. binned, with pixels larger than 2x2.
• Fig. 2 illustrates the structure of an image data set.
• the lowest 14 data bits (AD0-AD13: Fig. 6: 6-51 , 6-53, 6-55, 6-57) may come from the 16-bit summer (Fig. 6: 6-41 , 6-42, 6-43, 6-44) of the image data processing module of the FPGA device (Fig. 6: 6-40) (FPGA, Field Programmable Gate Array) and from the register (6-45, 6-46, 6-47, 6-48) which can store the intermediate sums.
• This summer can be reset before the sampling of each pixel, and the 14-bit result obtained from the A/D converter can be added once to this summer. It is also possible to add the value +1 to the sum to ensure that the result is always greater than 0.
• This result is a 14-bit number and the high- est 2 bits (ADDO and ADD1 ) are zeros.
• each chip of the CCD sensor may have two outputs (Output A and Output B, one of which may give a double signal with the same radiation), one is able to note that the overall dynamics of the system is 17 bits, i.e. 131 072 greyness levels (16384 x 4 x 2).
• One CCD sensor may consist of one or more, e.g. four chips (Fig. 6: 6-21 , 6-22, 6-23, 6-24) seamlessly connected one after the other. A separate clock signal can be applied to each chip.
• two identical CCD sensors are used. Each chip has two outputs (Fig. 6: 6-25 ... 6- 32). One of these may be a more sensitive so-called high-sensitivity output, i.e. A output, and the other one may be a less sensitive so-called high-capacity output, i.e. B output.
• one CCD sensor may have a total of 8 digitizing outputs, of which e.g. only four outputs are used simultaneously.
• the ratio of the capacities of the A and B outputs is very precisely Vz, i.e. the signal of the B output is equal to half the signal of the A output with the same amount of radiation.
• each one of the different chips can handle data obtained from a given part of the patient and/or function in a different mode, and each chip can be controlled individually or separately.
• the output in use can be selected (switches 6-33 ... 6-36 in Fig. 6) e.g. manually via a control register.
• the AGC function or a test function may decide about the output. All 8 outputs can be digitized by A/D converters, the number of which may be e.g. three.
• Each A/D converter may contain a 3-input multiplexer, i.e. selector, so the total number of channels to be digitized in this case is 9.
• An extra tenth channel is in test use, which can be applied to measure the noise of the electronics and the A/D conversion.
• Fig. 6 presents a situation where the selecting element 6-33 ... 6-36 after the output wells 6-25 ... 6-32 routes one of the wells to one A/D converter 6-37.
• the selection element may also form part of the A/D converter and it may be e.g. an analog or digital switch.
• Fig. 6 also illustrates a possible solution 6-100 for bringing clock signals and/or control signals from the FPGA element 6-40 to the CCD sensor 6- 20.
• AGC function refers to automatic control of level or gain.
• the gain of the programmably variable PGA amplifiers within the A/D converters, the gain of which amplifiers can be adjusted e.g. in the range 1 ... 6.
• This gain can be adjusted separately for each CCD chip, and the adjustment is used primarily for the optimization of basic sensitivity in accordance with the imaging conditions (Pan/Ceph).
• the AGC method can be utilized in a camera e.g. in the following two ways. Either one of the output amplifiers A or B of each CCD sensor can be used as far as applicable. Since the B amplifier has a signal handling capacity about twice that of the A amplifier, virtually one additional bit is obtained in the A/D conversion. Alternatively, it is also possible to use binning performed outside the CCD sensor. However, this is only possible when binning done in the direction of the read-out register. If in cases of high binning, e.g. 4x4 binning, the B output amplifier is getting saturated, then it is possible to shift to a lower binning within the CCD sensor, e.g. to 4x2 binning.
• the pixel values can now be sampled twice by the A/D converter, and the summing can be performed e.g. within the FPGA de- vice in an arithmetic unit. Multiple summing of the offsets caused by the electronics can be compensated for by computer software. This external summing may even be in the form of 4x1 binning and 4 summing operations.
• the overall dynamics can be increased to 17 bits, of which 14 bits are obtained from the A/D conversion, 1 bit from the output of the A or B amplifier and 2 bits from the external summing, which, as stated above, can be performed 4 times.
• Fig. 3 illustrates by way of example a method for performing imaging and presents the control logic controlling the automatic gain control (AGC) of the FPGA device during imaging.
• Imaging is normally started with a selected initial value, default binning.
• output A of each CCD sensor chip can be used.
• the read-out register of each chip can be controlled individually, it is possible to choose on a chip-specific basis the direction in which the charge is to be shifted. As stated, the charge can be shifted either in the direction of output A (1 -8: Fig. 1 ) or in the direction of output B (1 -6: Fig. 1 ).
• % of the range of the A/D converter then it is possible to shift to using the less sensitive output, output B, in those chips that meet this condition. If all the outputs are below the first threshold value, then a check can be made at stage 3-6 to determine whether all the currently used CCD-sensor outputs produced a signal below a second predefined threshold value, e.g. 25%, from the A/D converter. If all the outputs are below the second threshold value, then a check can be made at stage 3-8 to establish whether the smallest register-direction binning outside the CCD sensor has already been reached.
• a second predefined threshold value e.g. 25%
• stage 3-4 If at stage 3-4 at least one output exceeds 75% of the signal from the A/D converter, then the procedure can go on to stage 3-14. Here a check can be made to see whether any one of the outputs having produced a signal exceeding 75% is a B output. If not, then for the exceeding A outputs of the sensor it is possible to shift to using the B output on the next vertical column at stage 3-16.
• the signal still exceeds % of the range of the A/D converter in any one of the A/D converters of the CCD sensor chips although a shift to using output B has been made, i.e. where the B output is digitized, then at stage 3- 18 a check can be made to determine whether the maximum register-direction external binning has already been reached. If the register-direction external maximum binning has not yet been reached, then at stage 3-20 on the next vertical column it is possible to shift to using a register-direction arithmetic ex- ternal binning size increased by one step e.g. for all chips. If necessary, the binning can be changed gradually from 4x4 level to 1x4 level and back to 4x4 level.
• the structure and timing of the FPGA device can be optimized even in regard of this property.
• the use of the A output can be re- sumed for all CCD sensors whose B output has a level below the second threshold value, e.g. below 25%. If external maximum binning in the register- direction has already been reached, then the procedure can move on from stage 3-18 to stage 3-24. Likewise, after stages 3-10, 3-12, 3-16 and 3-22 the procedure can move on to stage 3-24, to await the digitization of the next vertical column.
• the camera head can independently make its conclusions regarding binning and the A/B outputs to be used, in accordance with predefined conditions.
• the logic of the FPGA device can be so constructed that it comprises a hysteresis to prevent jumping from one output to another.
• the image data being produced can be marked by the camera head to allow the computer software to carry out corresponding actions required in the processing of image data regardless of e.g. how the virtual pixels have been produced.
• the status diagram in Fig. 3 can be presented in the following form.
• the start-up it is possible to set out in a predetermined manner with all chips of the CCD sensor.
• the starting situation may be fixed and always the same: output A for all CCD sensors, normal selected CCD sensor pixel binning, no external binning outside the CCD sensor.
• imaging can always be started from maximum sensitivity with the selected pixel size.
• External binning outside the CCD sensor to be implemented by summing can also be defined separately, if it is not desired that the AGC function automatically shifts to the lowest possible sensitivity.
• the FPGA device executes a calibration sequence in which both the A direction and the B direction can be read alternately forwards or backwards. Dur- ing this calibration, the AGC function can be automatically disabled, and, when selected, it can only be activated after the calibration sequence.
• the procedure can shift to using a smaller register-direction binning internally within the entire sensor if, of the A/D conversions of the B output of any one of the chips of the CCD sensor 1 ... 16 pes, still exceed 75%.
• possible chip-specific shifts from output B to output A can be implemented, this allowing possible increases in sensitivity.
• decreases in sensitivity can be disabled.
• simultaneous AB sensitivity decreases can be prevented if at the same time a shift to external binning is made. Otherwise, the signal of these outputs may fall to one fourth instead of one half.
• the number m can be selected in the range of 1 ... 16 and the default value can be considered as being the value 1.
• the actual number to be used may depend on e.g. how many defective, saturated rows producing too large a signal there are at most in one and the same CCD chip.
• a corresponding procedure can be followed when the Ceph method is being used in a CCD sensor head containing two CCD sensor packages.
• the FPGA device of the CCD sensor (DIMAX2) is able to separately control the read-out direction of the register of a total of eight discrete chips and to collectively control the vertical binning of all the chips.
• Arranging for the vertical binning to be differently sized for different chips of the CCD sensor is also possible, although it involves more complexity in both the hardware and software required.
• the system noise and X-ray quantum noise present in the signal may also be different in magnitude on different outputs (output A / output B) and/or with AD binning.
• the noise may be reduced when binning is done using an A/D converter. If necessary, this can be taken into account in the software, where noise can be summed artificially onto those areas where it is smaller due to the binning method.
• dark current can be reduced several times, depending on the binning method. This can be accomplished e.g. mathematically and via software. If necessary, dark current calibration and gain calibration can be performed for both the A output and the B output.
• the FPGA device allows measurement of the signals of both outputs.
• Fig. 4 presents a table showing typical charge handling capacities of a CCD sensor used.
• column 4-2 represents the capacity and column 4-4 represents the number of electrons. It can be seen from the table that, when the capacity of one pixel (33 ⁇ m x 33 ⁇ m) is 1 million electrons, the capacity of the read-out register is 3 million electrons, the capacity of output amplifier A is 2.4 million electrons and the capacity of output amplifier B 4.8 million elec- trons. The guaranteed minimum capacities are at a level about 20% lower.
• Fig. 5 presents by way of example a charge capacity distribution in units capable of electron charge transfer.
• Block 5-2 represents four pixels in the image area with a typical saturation, which is about 1 million charges, at a minimum 800000 charges.
• the saturation value of each pixel is about 0.8 ... 1Me.
• Block 5-4 represents four summing register pixels with a typical saturation value, about 3 million charges, and the value at its minimum, about 2.4 million charges. Thus, the saturation value of each pixel is about 2.4
• Block 5-6 represents the typical saturation and minimum values of four read-out registers, 3 million charges and 2.4 million charges, respectively.
• Block 5-8 represents a typical saturation value of output well B, about 4.8 million charges, and minimum value, about 4 million charges, respectively.
• the output signal 5-9 of output well B is typically about 3 volts, at a minimum about 2 volts.
• Block 2-10 again represents a typical saturation value of output well A, about 2.4 million charges, the minimum value of this amount of charge being 2 million charges.
• the output signal 2-11 of output well A is typically about 3 volts, at a minimum about 2 volts.
• the basic sensitivity is about 60 mV / mR with 3x3 binning.
• the pixel size is about 99 microme- ters.
• the output wells have to be designed to be sufficiently small to avoid a loss of sensitivity of the CCD device.
• the output voltage 5-9, 5-11 is then suitable for the A/D conversion, so that it is suf- ficient in respect of both signal-to-noise ratio and resolution. This may involve limitations, even when output wells of different capacities are used.
• the largest average charge to be handled for the whole capacity of e.g. a 33- ⁇ m pixel before saturation of the output well, is about 15% of the value obtained when the A output is used and about 30% of the value obtained when the B output is used.
• the largest average charge to be handled for the whole capacity of e.g. a 33- ⁇ m pixel before saturation of the output well, is about 26.6% when the A output is used and about 13.3% when the B output is used.
• output well B is large enough to hold this entire 4-Me capacity. Therefore, with this binning the largest average charge to be handled, for the whole capacity of e.g. a 33- ⁇ m pixel before saturation of the output well, is about 60% when the A output is used, but about 100% when the B output is used. If no binning is done, the total signal level is about 1Me, i.e. the same as the level of the pixel. In this case, both the internal registers and the output wells can handle the signal without a risk of saturation.
• the sensitivity and therefore the dynamics can thus be increased by several different methods.
• the dynamics can be increased e.g. by simply changing the binning.
• the binning can be changed by shifting to a higher or lower binning level.
• the binning can be changed several times and the binning can be changed e.g. externally outside the CCD sensor.
• control signal can be defined e.g. beforehand, before changing the binning.
• the control signal may also be based on a direct or indirect signal, which may be dependent on e.g. the amount of light seen by the CCD sensor.
• the control signal may be based on the signal read out from the CCD sensor.
• the control signal may also be based on some other signal.
• the dynamics of the arrangement can be changed during imaging or before or after imaging.
• the binning can be changed e.g. between the image area and the shift register and/or between the shift register and the output register.
• the aim of the invention and its preferred embodiments is thus to expand the dynamic range of the CCD sensor e.g. by external means to be as wide as possible.
• the amplifiers can be optimized in respect of noise and speed e.g. for real-time TDI read-out of an X-ray image when the capacities of the charge wells are different.
• This procedure allows the dynamic range handled by the CCD sensor to be e.g. doubled or quadrupled when larger binning sizes, e.g. over 2x2 binning, are used.
• the signals of both output amplifiers can be digitized either simultaneously or alternately. The choice of which one of the two output amplifier signals is to be used depends on the signal itself.
• An arrangement according to the invention and its preferred embodiments can be integrated on a single CCD chip using one or more microcir- cuits. It is also possible to additionally integrate e.g. PGA amplifiers in the CCD pre-stages of the device. The gain of these amplifiers is adjustable e.g. in the range of x1 ... x6 in 64 steps (at present x1 ).
• PGA amplifiers in the CCD pre-stages of the device.
• the gain of these amplifiers is adjustable e.g. in the range of x1 ... x6 in 64 steps (at present x1 ).

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