EP1898426A2 - Mit Hilfe eines Zeilendecoders löschbarer und programmierbarer Speicher mit Phasenumwandlung - Google Patents

Mit Hilfe eines Zeilendecoders löschbarer und programmierbarer Speicher mit Phasenumwandlung Download PDF

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Publication number
EP1898426A2
EP1898426A2 EP07015337A EP07015337A EP1898426A2 EP 1898426 A2 EP1898426 A2 EP 1898426A2 EP 07015337 A EP07015337 A EP 07015337A EP 07015337 A EP07015337 A EP 07015337A EP 1898426 A2 EP1898426 A2 EP 1898426A2
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EP
European Patent Office
Prior art keywords
word line
control
voltage
vpulsei
signal
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EP07015337A
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English (en)
French (fr)
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EP1898426A3 (de
Inventor
Thierry Giovanazzi
Francesco La Rosa
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STMicroelectronics SA
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STMicroelectronics SA
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Publication of EP1898426A2 publication Critical patent/EP1898426A2/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0071—Write using write potential applied to access device gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/754—Dendrimer, i.e. serially branching or "tree-like" structure

Definitions

  • the present invention relates to the field of programmable nonvolatile memories and electrically erasable and including memories comprising phase change memory cells (PCM).
  • PCM phase change memory cells
  • phase change material compositions such as Mendeleev Table VI column-based alloys such as Te Tellurium or Se selenium
  • phase change can be be obtained with a voltage of a few volts and a current of a few hundred microamperes only, which allows the integration of phase change memory points in semiconductor chips implanted.
  • FIG. 1 represents the architecture of a memory plane MA of the type described by EP 1 450 373 .
  • the memory plane MA comprises memory cells CELi, j, k arranged in a matrix manner and each connected to a word line WLi of rank i and to a bit line BLjk of rank j (j ranging from 0 to m) belonging to a column COLk of rank k.
  • Each memory cell CELi, j, k comprises a selection switch TS, for example an NMOS transistor, and a phase change memory point P.
  • the anode of the memory point P is connected to a bit line BLjk and its cathode is connected via the transistor TS to a low potential or to a switchable line at a low potential, for example ground.
  • the gate terminal of transistor TS is connected to a word line WLi.
  • the memory point P has two stable states SET and RST (contraction of "RESET") corresponding to the two types of resistivity mentioned above.
  • SET state which corresponds, for example, to the storage of a logic "1”
  • the memory point has a first series resistance, for example 5 to 10 K ⁇
  • RST state corresponding to the storage of a "0" logic
  • the memory point has a second series resistance, for example 100 to 200 K ⁇ .
  • the state "SET” will be called the “SET state” and “state erased” the state RST.
  • the transition from the programmed state to the erased state is ensured by applying to the memory point a pulse RPULSE of the type represented in FIG. 3B, presenting a plateau of a duration tRST of a few tens of nanoseconds, for example 100 nanoseconds, and an extinction time Tq1 ("Tquench") as fast as possible, not to exceed in practice a few nanoseconds.
  • the pulse RPULSE is controlled voltage or current and has a maximum voltage Vp of a few volts and a maximum current Ip of a few hundred microamperes, which cause Joule effect a heating making the material amorphous.
  • the transition from the erased state to the programmed state is ensured by applying to the memory point a SPULSE pulse of the type shown in FIG. 3B, of a duration tSET.
  • the pulse has a plateau of a few tens of nanoseconds, for example 50 nanoseconds, and a long extinction time Tq2, for example 300 nanoseconds.
  • Tq2 for example 300 nanoseconds.
  • the SPULSE pulse has a ramp decreasing from a time tRAMP calculated from the time t0 of its emission, the duration of the ramp being equal to tSET-tRAMP.
  • the SPULSE pulse is also controlled in voltage or current and has a maximum voltage Vp of a few volts and a maximum current Ip of a few hundred microamperes, followed by the ramp voltage or current decreasing which has the effect of recrystallizing the material.
  • the extinction time Tq2 of the pulse SPULSE is quite long while the extinction time Tq1 of the pulse RPULSE must instead be very short to prevent recrystallization.
  • a reading of the memory point P then makes it possible to determine whether the latter exhibits the first or second series resistor, and a binary value 1 or 0 is associated with the resistance value read.
  • Such a reading is generally conducted under a low voltage so as not to modify the state of the memory point by causing erasure or spurious programming.
  • a reading voltage of low value for example 0.5 V, is sufficient to read the memory point while being low enough not to cause a change of the programmed state or cleared memory point.
  • phase change memory points in a memory made on a semiconductor substrate is an essential objective for the industrial exploitation of this memory technology, because low cost of integrated circuits.
  • the means for controlling the memory cells, in particular the erasing and programming means must be made rationally, inexpensively and not cumbersome in terms of the semiconductor surface.
  • FIG. 4 represents a conventional phase-change memory architecture of the type described by the application.
  • EP 1 450 373 The memory shown comprises a memory plane MA and memory cells of the type described above.
  • the memory also comprises a column selection circuit CSEL1 connected to the bit lines BL (BL0k, ... BLjk, ... BLmk).
  • the selection circuit CSEL1 comprises BK bit line selection blocks (BK0k, ... BKjk, ... BKmk) one block per bit line.
  • Each selection block BK comprises, in series, transistors TP1, TP2 of the PMOS type and a TN1 transistor of the NMOS type. These transistors are controlled by selection signals YMk, YNk, YOk provided by a column decoder CDEC1.
  • the pulses RPULSE or SPULSE are provided by write circuits WRCT (WRCT0, ... WRCTj, ... WRCTm).
  • the pulses RPULSE or SPULSE are applied to the bit lines via isolation transistors TIW, a multiplexing bus BMUX and selection blocks BK.
  • the isolation transistors TIW are turned on by means of a gate signal YW, the signals YM and YN are set to 0 (ground of the circuit) and the signal YO is brought to a voltage grid of high value so that the voltage Vp or current Ip is transferred without loss.
  • a line decoder RDEC applies to a word line WLi a selection signal SWLi which polarizes the gates of the selection transistors TS of the memory cells connected to this word line, and puts these transistors in the on state.
  • This method of erasure programming has the disadvantage of being relatively complex to implement.
  • the write circuits WRCT are complex to realize because the profile and the duration of the pulses RPULSE or SPULSE must be controlled with great precision, in particular the times of extinction Tq1 and Tq2.
  • the present invention thus provides a method for simple application to memory cells of voltage or current pulses having specified durations, profiles and extinction times.
  • the present invention also provides a memory comprising means for implementing this method.
  • the present invention provides an integrated circuit comprising a non-volatile memory comprising memory cells each comprising a memory point and a selection transistor having a control terminal connected to a word line, a line decoder for providing data.
  • word line select signals at least one voltage generator or current generator for supplying memory cells with an erase or programming voltage or current
  • word line drivers interposed between the line decoder and the lines of words, arranged to apply to a word line selected by the line decoder control pulses whose profile corresponds to a pulse profile of voltage or erase current or programming to be applied to memory points, and thus control by means of the selection transistors the amplitude and duration of the voltage or current erasing or programming applied to the memory points.
  • the integrated circuit comprises a control circuit providing the word line drivers with a first control signal whose profile determines the profile of the control pulses.
  • control circuit comprises a ramp generator for giving a control pulse a profile comprising a voltage ramp.
  • the pull-down switch of a word line driver is sized to pull the word line to a low level in a few nanoseconds after the word line has been biased with a maximum voltage that can apply the word line driver.
  • the integrated circuit comprises a control circuit providing the word line drivers with a second control signal indicating the end of a control pulse.
  • the integrated circuit comprises a control circuit providing the word line drivers with a second control signal indicating the beginning and the end of a control pulse.
  • the pull-down switch is controlled by the second control signal, so as to pull the word line down when the second control signal indicates that a control pulse is complete.
  • the word line drivers are arranged to apply to a word line a control pulse when the word line decoder provides a word line select signal and when the start of a control pulse is indicated by the second control signal.
  • the pull-down switch of a word line driver is the low-pass transistor of an inverting gate comprising a pull-up transistor for applying to the word line concerned a control pulse.
  • the input of the inverting gate is controlled by the second control signal, so as to draw the word line to a low level when the second control signal indicates that a control pulse is complete.
  • the input of the inverting gate is controlled by the second control signal and a word line selection signal, so as to: apply to the word line concerned a control pulse when the second signal control indicates the start of a pulse and the word line selection signal indicates that the word line is selected, and draw the word line to a low level when the second control signal indicates that the pulse of control is complete.
  • the word line drivers each comprise a pull-up switch to accelerate the high transition of the inverting gate input when the second control signal indicates that a control pulse is completed.
  • the memory point of a memory cell is a phase change memory point.
  • the memory point of a memory cell is connected to a bit line through which it receives the erasure or programming voltage or current, and is connected to a low potential by means of intermediate of the selection transistor of the memory cell.
  • the selection transistor of a memory cell is a MOS transistor.
  • the invention also relates to a method for controlling the application of erasing or erasing voltage or current pulses to memory cells each comprising a memory point and a selection transistor having a control terminal connected to a line of wherein the method comprises the steps of: applying an erase or programming voltage or current to the memory cells, and applying to the word line the control pulses whose profile corresponds to a voltage pulse pattern or erasing or programming current to be applied to memory points, in order to control by means of the selection transistors the amplitude and the duration of the erasing or programming voltage or current applied to the memory cells.
  • the method comprises a step of controlling the profile of the control pulses with a ramp generator, to give control pulses a profile comprising a voltage ramp.
  • the method comprises the steps of: providing a pull-down switch sized to quickly pull the word line down at the end of a control pulse, discharging a parasitic capacitance of the line of word, and turn on the low-pull switch at the end of a control pulse.
  • the pull-down switch is sized to pull the word line down in nanoseconds after the word line has been biased with a voltage.
  • the method comprises the steps of: providing a word line driver for applying the control pulses to the word line, arranging the pull-down switch in the word line driver, and providing to the word line driver a control signal indicating the end of a control pulse and causing the closing of the pull-down switch.
  • the method comprises a step of providing in the word line driver an inverting gate comprising the low-pull transistor and a pull-up transistor for applying the control pulses to the word line concerned.
  • the method comprises a step of controlling the input of the inverting gate by means of the control signal and a word line selection signal, so as to: apply to the word line a control pulse when the control signal indicates the start of a pulse and the selection signal indicates that the word line is selected, and draw the word line at a low level when the control signal indicates that the control pulse is complete.
  • the selection transistor of a memory cell is a MOS transistor.
  • FIG. 5 schematically represents a memory architecture according to the invention.
  • the memory described here as an exemplary embodiment of the invention is a word-programmable erasable memory in which the number of bits per word is defined by the number of bit lines contained in a column.
  • the invention also applies to a erasable memory and bit programmable in which the notion of column is not implemented (c that is, in which a column corresponds to a bit line and only one).
  • Each memory cell of the memory plane MA comprises a selection transistor TS and a phase change memory point P.
  • the memory point P is connected via the transistor TS to a low potential, or to a switchable line at a low potential, the low potential preferably being the ground of the circuit.
  • the transistors TS are here NMOS transistors, but bipolar transistors could also be used and in general any type of switch having a control terminal allowing a progressive control of the conductivity of the switch.
  • the memory also includes an RDEC line decoder, a CDEC2 column decoder, a column select circuit CSEL2, a read circuit RCT and an erase circuit or program EPCT.
  • the decoder RDEC and the decoder CDEC2 respectively receive the least significant and least significant bits of an address AD of a memory word to be selected (word of 8 memory cells or more according to the number of bit lines per column).
  • the RDEC decoder provides SWL signals (SWL0, ... SWLi, .... SwLn) for selecting word lines WL.
  • the decoder CDEC2 provides column selection signals YM, YN at the rate of two selection signals (YMk, YNk) per column of rank k (COLk).
  • LTC locks receive data through a DTB data bus at a rate of data (bit) by latch, and are activated by an erase signal ES and a separate PS programming signal.
  • an LTC latch delivers the erase or programming signal Vp / Ip when the erase signal ES has an active value (for example 1) and simultaneously receives a bit at 0 on a data input.
  • an LTC latch delivers the erase or programming signal Vp / Ip when the programming signal PS has an active value and simultaneously receives a bit at 1 on its data input.
  • the selection circuit CSEL2 comprises a selection block SB (SBjk, SBj'k) for each bit line BL (BLjk, BLj'k).
  • the bit line selection blocks belonging to the same column COLk (for example the blocks SBjk, SBj'k represented) receive the same selection signals YM, YN (for example the signals represented YMk, YNk).
  • the LTC latches do not provide the RPULSE erasing or SPULSE programming pulses described above.
  • the latches simply provide a fixed value Vp / Ip signal and the modulation of this signal is done by means of the TS transistors of the memory cells, as will be described later.
  • the structure of the locks is very simple. These locks are simple voltage or current switches of a type as known in the art and are for example used in the prior art to apply a high programming voltage Vpp to the bit lines in the EEPROM or FLASH memories comprising floating gate transistors.
  • the erase or programming signal Vp / Ip is applied simultaneously to all the TPI isolation transistors by means of a single switch for the entire memory plane.
  • a word line WL selected in erasure or programming receives VPULSE control pulses (VPULSEi) equal to VPULSE (RST) or VPULSE (SET), which drive the terminals of gate of TS transistors for selecting memory cells connected to this word line.
  • VPULSEi VPULSE control pulses
  • RST VPULSE
  • SET VPULSE control pulses
  • the VPULSE control pulse (RST) shown in FIG. 6A is a voltage pulse of value Vx with a profile substantially similar to that of the pulse RPULSE shown in FIG. 3A. This pulse is used to control the selection transistors TS during a memory cell erase phase. It presents in particular a duration tRST identical to the desired duration of the signal RULSE, and is followed by a very steep falling edge of duration Tq1 of the order of a few nanoseconds.
  • the VPULSE control pulse (SET) shown in FIG. 6B is a profile voltage pulse substantially similar to that of the SPULSE signal shown in FIG. 3B and is used to control the TS selection transistors during a phase of FIG. memory cell programming.
  • This pulse of duration tSET has a plateau of value Vx and of duration tRAMP of the order of 50 nanoseconds, followed by a falling edge with a low slope ranging from Vx to zero, of a duration Tq2 equal to tSET-tRAMP, by example 300 nanoseconds.
  • the CONTCT circuit also provides the DRV drivers with an EPULSE synchronization signal enabling them to know when a VPULSE (RST) or VPULSE (SET) control pulse ends.
  • this synchronization signal allows the word line pilots in particular to draw themselves at the low potential (here the ground) the word lines that have received the voltage Vx, by quickly discharging parasitic capacitors Cs ( Csi) present on these word lines.
  • setting the word lines to 0 is provided by the pilots themselves, rather than by the CONTCT circuit, and makes it possible to obtain a very steep descent edge Tq1 at the end of the VPULSE pulse ( RST).
  • FIG. 7 represents an embodiment of the CONTCT circuit.
  • This comprises an LCT logic control circuit, an "OR” type gate G1, an inverting gate IV1, a RAMPGEN ramp generator electrically powered by the voltage Vx, a timer TMR ("timer") clocked by a signal D CK clock, a CP comparator and, optionally, a TPULSE output transistor, here of PMOS type.
  • the TPULSE transistor has its source terminal connected to an output node ND1 of the RAMPGEN generator, and its drain terminal supplies the control signal VPULSE.
  • the circuit LCT receives two external command signals RSTS and SETS respectively indicating that an erase pulse VPULSE (RST) or programming VPULSE (SET) must be applied to word lines.
  • the LCT circuit provides the signal EPULSE ("Enable Pulse") which is here equal to 1 for the duration of the pulse.
  • the signal EPULSE is sent to the DRV drivers via the gate G1, which receives on another input a READ signal. This READ signal makes it possible to force the signal EPULSE to 1 during reading phases, in order to force the pilots into the on state during the reading of memory cells.
  • the signal EPULSE is also applied to the generator RAMPGEN and is applied to the gate terminal of the transistor TPULSE via the inverting gate IV1, so that the transistor TPULSE becomes on when the signal EPULSE is equal to 1.
  • the generator RAMPGEN supplies on the output node ND1 a voltage VDR which is equal to the voltage Vx as long as the circuit LCT does not set an ERAMP signal ("Enable Ramp").
  • the voltage VDR decreases and tends to 0 with a slope which is set so that the transition from Vx to 0 corresponds substantially to the extinction time Tq2 of a pulse SPULSE (FIG. the difference between the instant tSET and the instant tRAMP (Figs 3B and 6B).
  • the timer TMR determines the instants tRAMP and tRST, respectively the moment when a downward voltage ramp has to be produced by the circuit PULSCT after the start of the pulse VPULSE (SET), and the instant when a pulse VPULSE (RST ) must end.
  • the timer receives from the circuit LCT two CTRAMP and CTRST signals indicating which of the two delays must be calculated.
  • the activation of the timer is triggered by the signal VPULSE, when it goes from 0 to the voltage Vx on the drain terminal of the TPULSE transistor.
  • the timer supplies the circuit LCT with a signal TRAMP equal to 1.
  • the timer provides the circuit LCT with a signal TRST equal to 1.
  • FIGS. 8A to 8G respectively represent the signals SETS, EPULSE, TRAMP, ERAMP, STP, the voltage VDR and the signal VPULSE.
  • the SETS signal is set to 1 (Fig. 8A) and the LCT circuit sets the signal EPULSE to 1 (Fig. 8B).
  • the transistor TPULSE becomes on and the signal VPULSE becomes equal to VDR equal to the voltage Vx (Fig. 8G), because the voltage VDR has been previously stabilized (Fig. 8F) by applying the voltage Vx to the generator RAMPGEN.
  • the timer TMR sets the signal TRAMP to 1 (Fig.
  • the timer TMR sets the signal TRST to 1 (FIG 9C) and the circuit LCT then sets the signal EPULSE to 0 (FIG 9B).
  • the transistor TPULSE is blocked, so that the drain of this transistor goes into the high impedance state.
  • the voltage VDR remains equal to Vx, so that the output node ND1 of the generator remains preloaded to supply the voltage Vx again.
  • the very short extinction time Tq1 of the pulse VPULSE (RST) (FIG 6A) is not controlled by the CONTCT circuit whose output passes here at high impedance, and this control is provided locally. by the DRV word line drivers, in a manner to be described later.
  • FIG. 10 represents an exemplary embodiment of the RAMPGEN ramp generator. It comprises a PMOS type transistor TP1, NMOS type transistors TN1, TN2, TN3, TN4, TN5, a follower FW and an inverting gate IV2 electrically powered by the voltage Vx, an IGEN current generator supplying a current Iref and a ramp capacitor Cr.
  • the source terminal of the transistor TP1 receives the voltage Vx, the drain terminal of this transistor is connected to that of the transistor TN1 at a point forming the output node ND1 of the generator, supplying the voltage VDR.
  • the source terminal of transistor TN1 is connected to ground.
  • FIGS. 11A to 11E The operation of the RAMPGEN generator between the instants tRAMP and tSET is illustrated in FIGS. 11A to 11E which respectively represent the signal ERAMP ', the signal Vpull, the voltage Vc (node ND2), the voltage Vg (node ND3) and the voltage of VDR output (node ND1).
  • the signal ERAMP ' is at 0 and the signal Vpull is at 1 (Vx).
  • the transistor TP1 is on and the output voltage VDR is equal to Vx.
  • the capacitor Cr is charged, the transistors TN4 and TN5 are on and the node ND2 (voltage Vc) is connected to ground.
  • the DRVi driver comprises inverting gates IV3, IV4, IV5 electrically powered by the voltage Vx, an IDRIVE output inverting gate, three NMOS transistors including a pull-up transistor TPU (pull-up), a pull-down transistor TPD ("pull-down"), and another TAPU high-pull transistor.
  • the IDRIVE gate is formed by a PMOS type TDRIVE transistor and an NMOS type TDOWN transistor in series, the two transistors having their gate terminals interconnected.
  • the transistor TDRIVE receives the control signal VPULSE on its drain terminal. Its drain terminal is connected to the drain terminal of the TDOWN transistor whose source terminal is connected to ground.
  • Doors IV3, and IV4 are connected head to tail to form an LDRIVE lock (volatile memory point).
  • the input of this latch is connected to the input of the IDRIVE inverting gate as well as to the drain terminal of the TPU transistor and to the drain terminal of the TAPU transistor.
  • the output of the latch is connected to the drain terminal of the TPD transistor.
  • the source terminal of the TPD transistor is connected to ground and the source terminal of the TAPU transistor receives the voltage Vx.
  • the transistor TPU receives the word line selection signal SWLi on its source terminal (supplied by the decoder CDEC, see Fig. 5 or 7) and receives on its gate terminal the signal EPULSE.
  • the transistors TPD and TAPU receive on their gate terminals the inverted signal / EPULSE provided by the gate IV5.
  • the selection of the word line SWLi is ensured by the decoder CDEC which sets the signal SWLi to 0.
  • the transistor TPU becomes on and forces 0 the input of the lock LDRIVE and therefore the entrance to the IDRIVE gate.
  • the transistor TDRIVE turns on and applies the control signal VPULSE to the word line.
  • the signal EPULSE returns to 0, the signal / EPULSE goes to 1 and transistors TPD and TAPU are on.
  • the transistor TPD sets the output of the LDRIVE lock to 0, the input of which thus switches to 1.
  • the TAPU Accelerated Pull Up Transistor
  • the TDOWN transistor has a width-to-gate length ratio (W / L) which is chosen according to the importance of the parasitic capacitance of the word line, which depends on the length of the word line and the number of TS selection transistors connected to it (the capacitors gate-source noise of transistors TS adding to intrinsic parasitic capacitance of the word line).
  • the driver DRVi is controlled by the signal EPULSE which marks both the beginning of a control pulse VPULSEi (making the transistor TDRIVE passing) and the end of a pulse (by blocking the transistor TDRIVE and simultaneously making the TDOWN transistor passing).
  • EPULSE the signal which marks both the beginning of a control pulse VPULSEi (making the transistor TDRIVE passing) and the end of a pulse (by blocking the transistor TDRIVE and simultaneously making the TDOWN transistor passing).
  • the transistor TPULSE of the circuit CONTCT described above in relation to FIG. 7, is not necessary since the beginning and the end of a pulse VPULSEi on the word line WLi are controlled by the transistor TDRIVE. If the TPULSE transistor is removed, the VPULSE signal is identical to the VDR voltage supplied by the RAMPGEN generator and is no longer a pulsed control signal.
  • FIGS. 13A to 13E respectively represent the selection signal SWLi, the signal EPULSE, the signal ERAMP, the signal VDR / VPULSE, and the control pulse VPULSEi.
  • the left-hand part of these figures illustrates the application of a SPULSE programming pulse to memory cells and the right-hand part of the figures illustrates the application of an erase pulse RPULSE, ie the application of a VPULSE pulse, respectively. (SET) and a VPULSE pulse (RST) to the selection transistors TS.
  • SET erase pulse
  • RST a VPULSE pulse
  • the signals illustrated differ only from those described above by the fact that the signal VPULSE is not controlled temporally by the signal EPULSE and that the temporal delimitation of the control pulses (beginning and end of the pulses) is only found on the signal VPULSEi (effect of the transistor TDRIVE), both for the VPULSE pulse (SET) and the VPULSE pulse (RST).
  • the CONTCT circuit can be divided into two separate control circuits, one being equipped with the ramp generator and controlling the profile of the control pulses, the other being equipped with the timer and the voltage comparator and ensuring the control of the duration of the control pulses.
  • the function of the comparator determination of the end of the VPULSE pulses (SET)) can also be ensured by the timer if the slope of the voltage ramp is stable with the aging of the integrated circuit or as a function of the temperature.
  • the precise shape of the RPULSE and SPULSE pulses shown in Figs. 3A, 3B and the corresponding shape of the VPULSE (RST) and VPULSE (SET) control pulses shown in Figs. 3A, 6B can also be modified.
  • the SPULSE pulse and the control pulse corresponding VPULSE (SET) may not include the plateau time ranging from t0 to tRAMP. These pulses are then formed only by a decreasing ramp.
  • the signal ERAMP is then sent at the same time as the signal EPULSE and it is no longer necessary for the timer TMR to provide the signal TRAMP.
  • the memory plane may be of the erasable and bit programmable type.
  • erasure or programming of the memory cells is done individually and sequentially (one after the other).
  • a bit write may be preferred to a word write according to the technological constraints involved in the design of the memory, in particular to avoid having to collect a significant resulting current equal to the sum of the erase and programming currents crossing each of the cells. concerned when writing all the memory cells of a word collectively.
  • the present invention generally relates to any type of integrated circuit comprising a memory, from the memories marketed in the form of integrated circuits to complex integrated circuits comprising a memory and various other elements using the memory, for example microcontrollers.

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EP07015337A 2006-09-05 2007-08-06 Mit Hilfe eines Zeilendecoders löschbarer und programmierbarer Speicher mit Phasenumwandlung Withdrawn EP1898426A3 (de)

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JP2010067332A (ja) * 2008-09-12 2010-03-25 Elpida Memory Inc 相補型相変化メモリセル及びメモリ回路
WO2010076834A1 (en) * 2008-12-31 2010-07-08 Ferdinando Bedeschi Reliable set operation for phase-change memory cell
EP2684192B1 (de) * 2011-03-11 2019-05-08 Ovonyx Memory Technology, LLC Vorrichtungen und verfahren zur programmierung einer speicherzelle
US8854872B2 (en) 2011-12-22 2014-10-07 International Business Machines Corporation Drift mitigation for multi-bits phase change memory
US8614911B2 (en) 2011-12-22 2013-12-24 International Business Machines Corporation Energy-efficient row driver for programming phase change memory
US8605497B2 (en) 2011-12-22 2013-12-10 International Business Machines Corporation Parallel programming scheme in multi-bit phase change memory
KR101891153B1 (ko) 2012-02-14 2018-08-23 삼성전자주식회사 저항성 메모리 장치, 이의 동작 방법, 및 이를 포함하는 메모리 시스템
US9563371B2 (en) 2013-07-26 2017-02-07 Globalfoundreis Inc. Self-adjusting phase change memory storage module
US9286160B2 (en) 2014-02-07 2016-03-15 Stmicroelectronics S.R.L. System and method for phase change memory with erase flag cells
WO2016167756A1 (en) * 2015-04-15 2016-10-20 Hewlett Packard Enterprise Development Lp Resistive random access memory (rram) system
IT201800006005A1 (it) * 2018-06-04 2019-12-04 Un convertitore analogico-digitale e digitale-analogico, relativo circuito integrato, sistema elettronico e procedimento

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