EP1361583A1 - Speicherzellenprogrammierungsverfahren mit Durchbruch von Antischmelzsicherungen - Google Patents

Speicherzellenprogrammierungsverfahren mit Durchbruch von Antischmelzsicherungen Download PDF

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Publication number
EP1361583A1
EP1361583A1 EP03007639A EP03007639A EP1361583A1 EP 1361583 A1 EP1361583 A1 EP 1361583A1 EP 03007639 A EP03007639 A EP 03007639A EP 03007639 A EP03007639 A EP 03007639A EP 1361583 A1 EP1361583 A1 EP 1361583A1
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EP
European Patent Office
Prior art keywords
breakdown
elements
fuse
antifuse
voltage
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EP03007639A
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English (en)
French (fr)
Inventor
Benjamin Duval
Fabrice Marinet
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present invention relates to a programming method a row of anti-fuse memory cells, comprising a breakdown step of at least N anti-fuse elements present in memory cells, the breakdown of an anti-fuse element comprising applying a breakdown voltage to the anode of the anti-fuse element.
  • anti-fuse memory cells in integrated circuits allows zones to be produced at low cost non-volatile memory with average storage capacity but sufficient to store permanent low data length like an integrated circuit serial number, code secret, configuration data for analog quantities of the integrated circuit, etc.
  • memories of the fuse type or antifuse constitute an advantageous alternative to memories non-volatile based on the principle of charge retention electric, for example using gate transistors floating.
  • a fuse-type memory cell includes an element fuse, for example a polysilicon fuse, which is initially conductive and becomes non-conductive when slammed, the breakdown can be done by laser or obtained by application of a breakdown voltage.
  • element fuse for example a polysilicon fuse
  • an anti-fuse memory cell includes a anti-fuse element, usually an oxide layer, which is initially insulating and becomes conductive after being slammed, the breakdown causing the appearance of a conductive path in oxide.
  • a anti-fuse element usually an oxide layer, which is initially insulating and becomes conductive after being slammed, the breakdown causing the appearance of a conductive path in oxide.
  • the anti-fuse memories have a time of rather long programming, which is a major drawback in some applications, for example as part of a large-scale production of integrated circuits including each an anti-fuse memory zone to be programmed.
  • the collective breakdown of 20 anti-fuse elements requires the application of a breakdown voltage during a duration of approximately 50 ms. This duration is not negligible in the microelectronics, where programming times are usually in a few tenths of a millisecond or in milliseconds rather than tens of milliseconds.
  • FIG. 1 illustrates the conventional arrangement of N anti-fuse elements AF1, AF2 ... AF N during the breakdown of the anti-fuse elements.
  • the anti-fuse elements are represented as capacitors and the insulating material present between the electrodes of the capacitors forms the anti-fuse element proper.
  • the cathodes of the anti-fuse elements are connected to ground and the anodes are connected to a common node N1.
  • the node N1 is connected to a voltage source Vhv by means of a switch SWg.
  • the switch SWg is closed for a predetermined time t (N), during which the anti-fuse elements receive the breakdown voltage Vhv on their anodes.
  • the breakdown of the anti-fuse material causes a series resistance Rc to appear between the electrodes which makes the anti-fuse element conductive.
  • these anti-fuse elements are arranged in a row of memory cells comprising selection means, access and read which are not shown here in a for simplicity, programming the row of cells memory corresponding to the breakdown of the anti-fuse elements.
  • FIG. 2 represents a curve giving the time of breakdown t (N) as a function of the number N of anti-fuse elements collectively slammed. It appears that the time t (N) is not constant and depends on the number N. More particularly, this curve is not linear and tends to grow pseudo-exponentially with the number N.
  • the present invention aims to reduce the time of breakdown of a group of N antifuse elements.
  • the present invention aims to solve the problem of rapidly increasing breakdown time as a function of the number N of anti-fuse elements to snap.
  • the present invention relates to a method of programming of anti-fuse memory cells allowing decrease the breakdown time of a group of N elements antifuse.
  • the present invention provides a method of programming a row of memory cells anti-fuse in parallel comprising a step of breakdown of at minus N antifuse elements present in memory cells, the breakdown of an anti-fuse element including the application a breakdown voltage on the anode of the anti-fuse element, in which the anti-fuse elements are slammed sequentially by groups of P antifuse elements with P less than N and at least equal to 1, the anti-fuse elements of a same group receiving the breakdown voltage simultaneously, the breakdown of a group of anti-fuse elements following intervening immediately after snapping a group of items previous antifuse.
  • P is equal to 1, the elements anti-fuse being slammed individually one after the other.
  • P is chosen from several possible values so that the total breakdown time of the N anti-fuse elements is optimal.
  • the number P of elements anti-fuse slammed simultaneously is not constant during the programming of the row of memory cells.
  • the method comprises a step detection of the breakdown of the anti-fuse elements.
  • P anti-fuse elements following are not slammed as long as the snap of P elements previous antifuse was not detected.
  • the breakdown of an element anti-fuse is detected when a voltage above a threshold determined appears on the cathode of the anti-fuse element while its anode receives the breakdown voltage.
  • the method is applied to a memory comprising rows of cells arranged in rows of word and in bit lines programming a row of cells including selecting a word line and the sequential application of the breakdown voltage to the lines bit, by groups of P bit lines simultaneously receiving the breakdown voltage.
  • the method is applied to a row of anti-fuse memory cells with architecture differential and each comprising two anti-fuse elements, the programming of each cell including the breakdown of a anti-fuse element chosen from the two anti-fuse elements of the cell according to the value of a binary data to program, the breakdown of the row of cells including the sequential breakdown of a single anti-fuse element in each row cell.
  • the present invention also relates to a memory integrated circuit anti-fuse comprising at least one row of anti-fuse memory cells in parallel, memory cells being programmable by the breakdown of N anti-fuse elements present in memory cells, programming means of the row of cells by applying a voltage of breakdown on an anode of each anti-fuse element to snap, in which the programming means comprise means to apply the breakdown voltage sequentially to groups of P antifuse elements, P being less than N and less than 1, the anti-fuse elements of the same group receiving the breakdown voltage simultaneously, the breakdown of a next group of anti-fuse elements intervening immediately after the breakdown of a previous group of anti-fuse elements.
  • P is equal to 1 and the means are arranged to individually apply the breakdown voltage at the anti-fuse elements, so as to slam the anti-fuse elements one after the other.
  • the number P of elements antifuse in groups of slammed antifuse elements simultaneously is not constant during the programming of a row of memory cells.
  • the memory includes means for detecting the breakdown of anti-fuse elements, delivering a breakdown detection signal.
  • the programming means are arranged so as not to apply the breakdown voltage to a group of anti-fuse elements following as long as the breakdown from a previous group is not detected.
  • the detection means include at least one comparator comprising a first input connected to the cathode of at least one anti-fuse element, one second input receiving a reference voltage and an output delivering the breakdown detection signal.
  • the memory comprises a sequencer circuit and switches controlled by the circuit sequencer for sequentially applying breakdown voltage to the anti-fuse elements, the sequencer circuit receiving the breakdown detection signal.
  • the memory comprises several rows of cells arranged in word lines and lines of bit, each bit line comprising a distribution line of the breakdown voltage, the programming means being arranged to select a word line and apply sequentially the breakdown voltage at the distribution lines of the bit, in groups of P bit lines simultaneously receiving the breakdown voltage.
  • the memory includes memory cells with differential architecture and each comprising two anti-fuse elements in parallel, and switches for selecting a snap-on anti-fuse element among the two depending on the value of a binary data to save.
  • the non-linear relationship existing between the breakdown time t (N) and the number N of anti-fuse elements to be snapped collectively is due to the fact that the breakdown time of an anti-fuse element considered individually depends on the intensity of the current available for breakdown, and is all the longer as this current is low.
  • Vhv a breakdown voltage applied to the anodes of N anti-fuse elements AF1, AF2 ... AF N in parallel, as illustrated in FIG. 1, all the anti-fuse elements do not flare at exactly the same time.
  • the present invention is based on the simple but no less inventive idea of limiting the number of elements to be snapped simultaneously by subdividing a group of N antifuse elements to be snapped into N / P groups of P antifuse elements, and by proceeding to N / P breakdown cycles of P anti-fuse elements.
  • t (P) the collective breakdown time of P antifuse elements
  • TP the total duration of breakdown according to the method of the invention
  • the number P is preferably chosen so that the total breakdown time TP is optimal.
  • the number P optimal is equal to 1. Indeed the breakdown time of an element isolated antifuse is statistically shorter than half the breakdown time of two anti-fuse elements and is fine obviously much shorter than the breakdown time of N anti-fuse elements divided by N. In addition to the limitations of the voltage / current source, this is also due to limitations on the size of switches and the dimensioning of the conductive tracks used for distribute high voltage, which must bear the sum of all breakdown currents.
  • the breakdown time of an oxide anti-fuse element is 0.5 ms while the breakdown time of 20 anti-fuse elements is 50 ms.
  • An obstacle to the implementation of the first aspect of the invention lies in determining the breakdown time t (P) to be applied to each of the groups of P anti-fuse elements. Although an experimental determination of t (P) is possible, the drift of technology between batches of integrated circuits may make this time insufficient. Conversely, the choice as a precaution of a time t (P) very long could lose some or all of the benefits of method of the invention.
  • the duration of breakdown of a group of P antifuse elements either determined in real time thanks to a breakdown detection of each anti-fuse element.
  • the detection of the breakdown of each anti-fuse element is obtained by observing the voltage present on the cathode of the anti-fuse element, while the latter receives the voltage Vhv on its anode. so that the cathode voltage is floating, the anti-fuse element is electrically insulating and is not slammed.
  • the anti-fuse element becomes conductive well still highly resistive and the cathode voltage starts to ascend.
  • the breakdown is considered detected when the cathode voltage reaches a determined value Vref, which corresponds to a certain value of electrical resistance of the anti-fuse element.
  • Vref a resistive and / or capacitive element should preferably be provided on the cathode, in order to form a bridge with the anti-fuse element voltage divider.
  • this element resistive and / or capacitive is generally present by the mere fact of the presence of selection transistors connecting the cathodes of anti-ground elements.
  • the general switch SWg connecting the node N1 to the voltage Vhv is deleted and is replaced by N individual switches SWA1, SWA2, SWA3 ... SWA N each arranged between the anode of an antifuse element and the node N1.
  • each anti-fuse element is here connected to ground via a resistor, respectively R11, R12, R13 ... R1 N.
  • This resistance generally corresponds to the drain-source resistance of a transistor for selecting the anti-fuse element, as will appear later in the description of an example of anti-fuse memory according to the invention.
  • each anti-fuse element is also connected to a node N2 by means of an individual switch, respectively SWB1, SWB2, SWB3 ... SWB N.
  • the node N2 is connected to the positive input of a comparator CMP whose negative input receives the voltage Vref.
  • the output of the CMP comparator delivers a SHIFT signal which is applied to an offset control input of a SREG shift register comprising N cascaded cells C1, C2 ... C N.
  • the shift register comprises N outputs each corresponding to a cell, respectively delivering signals SEL1, SEL2, SEL3, ... SEL N.
  • the signal SEL1 drives the switches SWA1 and SWB1
  • the signal SEL2 drives the switches SWA2 and SWB2, etc., the signal SEL N driving the switches SWA N and SWB N.
  • the breakdown process of the N anti-fuse elements proceeds as follows.
  • the SREG register is set to 0, the breakdown voltage Vhv is applied to the node N1 and a bit at "1" is loaded in the first cell C1 of the SREG register.
  • the signal SEL1 goes to 1, the other signals SEL2 ... SEL N being at 0, so that the switches SWA1, SWB1 close.
  • the voltage Vhv is found on the anode of the first anti-fuse element AF1, the cathode of which is connected to the positive input of the comparator CMP. When the element AF1 begins to become conductive, a cathode voltage Vc1 appears.
  • the signal SHIFT at the output of the comparator goes to 1.
  • the bit to 1 shifts in the next cell C2 while the cell C1 goes back to 0.
  • the signal SEL2 goes to 1, the signal SEL1 returns to 0 and the other signals SEL3 ... SEL N remain at 0.
  • the switches SWA1, SWB1 open and the switches SWA2, SWB2 close.
  • the voltage Vhv is found on the anode of the second antifuse element AF2 and the cathode of the antifuse element AF2 is connected to the positive input of the comparator CMP.
  • a cathode voltage Vc2 appears and causes a new shift of the SREG register. The process continues until all of the anti-fuse elements are struck.
  • the comparator CMP and the switches SWB1 to SWB N make it possible to detect the breakdown of each element, and to control the transition to the next breakdown cycle.
  • the time given to each breakdown cycle is thus subject to its minimum value, which may be different from one anti-fuse element to another.
  • the threshold Vref corresponds to a certain value of electrical resistance of the anti-fuse element, a resistance of less than 100 K ⁇ being considered in practice as representative of a satisfactory breakdown.
  • To calculate the threshold Vref account is taken of the fact that the slammed anti-fuse element forms with the series resistance R11 to R1 N a voltage divider bridge.
  • a voltage Vref representing 20% of the voltage Vhv, or 2V for a voltage Vhv of 10V, can be chosen.
  • FIG. 4 represents an exemplary embodiment in CMOS technology of AFMEM anti-fuse memory according to the invention.
  • AFMEM memory conventionally includes a plan MA memory ("memory array") comprising memory cells antifuse CELi, j, an RDEC line decoder receiving as input an AD line address, a DREG data register ("data register "), a SENSE reading circuit and a central unit CPU.
  • the AEMEM memory is implemented here in an integrated circuit including a central unit or CPU controlling operations writing and reading from memory. So the CPU loads in the DREG register of the data to be recorded in the memory plan and reads data read from the plan at the output of the SENSE circuit memory.
  • the memory includes the switches SWA1 to SWA N described above, a PSEQ programming sequencer with wired logic to drive the SWA switches, and a control circuit CONTC to control the breakdown process of anti-fuse elements and deliver a VERIF signal applied to the PSEQ sequencer.
  • the switches SWA1 to SWA N are here MOS transistors connected by their drain to the node N1 which receives the voltage Vhv.
  • the sequencer delivers the selection signals SEL1, SEL2 .... SEL N described above, so as to turn on, one after the other, the transistors SWA1 to SWA N.
  • FIG. 5 represents the architecture of a memory cell antifuse CELi, j, here a differential architecture common to all the cells of the memory plane.
  • the memory cell includes two anti-fuse elements AFAj, AFBj. Element anodes AFAj, AFBj are connected to an input PIN1 of the cell.
  • the cathode of the AFAj element is connected to the drain of a transistor T1 whose source is connected to ground, and to the drain of a transistor T2 whose source is connected to an output OUT1 of the cell.
  • the cathode of the AFBj element is connected to the drain of a transistor T3 whose source is connected to ground, and to the drain of a transistor T4 whose source is connected to an OUT2 output of the cell.
  • the grid of transistor T1 is connected to an input IN1 of the cell by through a transistor T5.
  • the gate of transistor T3 is connected to an input IN2 of the cell via of a transistor T6.
  • the gates of the transistors T5, T6 are connected to an SIN input of the cell.
  • the grids of transistors T2, T4 are connected to a PIN2 input of the cell via a transistor T7 whose gate is connected to the SIN input.
  • Selecting a memory cell for writing or reading is done by applying a selection signal to 1 (supply voltage Vcc of the integrated circuit) on the SIN input of the cell, which makes transistors T5, T6, T7 on.
  • the writing of a Bi bit in a memory cell is done by applying the Bi bit to the IN1 input and the reverse / Bi bit to the IN2 input.
  • the breakdown voltage Vhv is applied to the input PIN1 and causes the breakdown of the element AFAj or of the element AFBj depending on whether the bit Bi is at 1 (transistor T1 passing) or at 0 (bit / Bi at 1, transistor T3 on).
  • the breakdown of the element AFAj or AFBj is detected by monitoring its cathode voltage, via the transistor T2 or T4 and the output OUT1 or OUT2 of the cell.
  • the pair of transistors T2, T4 is used during the programming process as one of the switches SWB (SWB1 to SWB N ) described above (fig. 3).
  • the reading of a bit in the memory cell is done in applying a Vread voltage on its PIN1 and PIN2 inputs, and observing outputs OUT1 and OUT2. If output OUT1 is at 1 (Vread voltage) and output OUT2 at 0, this means that the data loaded in the memory cell is the logical "1" (AFAj element slammed). If the output OUT1 is at 0 and the output OUT2 to 1, this means that the data loaded in the cell memory is the logical "0" (AFBj element slammed).
  • Figure 6 shows in more detail the architecture of the MA memory map as well as those of the CONTC circuit and the circuit SENSE.
  • the SENSE circuit includes sense amplifiers SENSE1, SENSE2 ... SENSE N each comprising two inputs RIN1, RIN2 and one output DOUT (see SENSEj in the figure).
  • Each sense amplifier includes for example three inverting gates S1, S2, S3 (see SENSE1 in the figure).
  • the doors S1, S2 are connected head to tail, the input of the gate S1 being connected to the input RIN1 and the input of the gate S2 connected to the input RIN2.
  • the door S3 has its input connected to the output of one of the doors S1, S2 and its output forms the output DOUT of the sense amplifier.
  • the CONTC circuit includes two comparators CMP1, CMP2 receiving on their negative inputs the voltage Vref.
  • the exits comparators are applied to the input of an XOR gate (OR EXCLUSIVE) whose output delivers the VERIF signal.
  • the differential anti-fuse memory cells CELi, j are arranged in N bit lines BLj (BL1, BL2, ... BL N ) and in K word lines WLi, to form rows of N memory cells each , a row corresponding to a word line.
  • Each word line WLi includes a selection line SWLi connected to the SIN inputs of the line memory cells of word.
  • the SWLi line receives a SELWLi selection signal issued by the RDEC decoder, which is 1 when the address received corresponds to the word line considered.
  • each read line LR1j is connected to the positive input of the comparator CMP1 and each read line LR2j is connected to the positive input of the comparator CMP2.
  • Each distribution line LP1j is connected to the node N1 via a transistor SWAj of corresponding row j (SWA1, SWA2, ... SWA N ).
  • the lines LP1j are also connected to a common auxiliary line AUXL, making it possible to apply the voltage Vread to the lines LP1j during reading phases.
  • the Vread voltage is applied to the AUXL line via an IT isolation transistor controlled by a READ signal.
  • Selecting a row of write memory cells or read is done by applying an AD address to the decoder RDEC. This then delivers a selection signal SELWLi equal to 1 (supply voltage Vcc of the integrated circuit) on the line SWLi designated by the address AD.
  • the SELWLi signal is found on the SIN entries of the cells in the word line, making them transistors T5, T6, T7 passing in each of the cells.
  • Memory cells are read by applying the Vread voltage on the LP1j lines (via the AUXL line) and on the LP2j lines, and by selecting a word line to read using the RDEC decoder.
  • the selected cells each have an output OUT1 or OUT2 which goes to 1, and each of the sense amplifiers SENSE1 to SENSE N delivers a data item.
  • the writing of data in a word line WLi selected by the RDEC decoder is obtained by programming each of the cells of the word line, the programming of each cell corresponding to the breakdown of an anti-fuse element AFA or AFB.
  • the data is previously recorded in the DREG register. This data takes the form of a series of bits B1, B2, ... B N , each bit Bj being applied to a line LDlj and each inverted bit / Bj applied to a line LD2j.
  • the voltage Vhv is applied to the node N1.
  • the voltage Vread is also applied to the lines LP2j so that the transistors T2, T4 of the cells selected (fig. 5) are on and that the outputs OUT1, OUT2 deliver an anode voltage allowing the comparators CMP1, CMP2 to control the breakdown process. It goes without saying that any other voltage making it possible to make the transistors T2, T4 pass.
  • the CPU applies a START signal to the PSEQ sequencer, which then sets the signal SEL1 to 1, all the other signals SEL2 to SEL N remaining at 0. Only the transistor SWA1 is on and only the first cell in the row to be programmed receives the voltage Vhv.
  • One of the two anti-fuse elements AFAj, AFBj receives the voltage Vhv, according to the value of the data present on the inputs IN1, IN2 (bits B1 and / B1).
  • the cathode voltage present on the positive input of one of the comparators CMP1, CMP2 switches the output of a comparator to 1 while the output of the other comparator remains at 0.
  • the VERIF signal goes to 1, which triggers the programming cycle of the next cell.
  • the sequencer PSEQ then sets the signal SEL2 to 1 and resets the signal SEL1 to 0, all the other signals SEL3 to SEL N remaining at 0.
  • the transistor SWA2 turns on and the second cell of the row to be programmed receives the voltage Vhv.
  • the VERIF signal returns to 1 and triggers the programming cycle for the next cell, and so on until the N cells are programmed.
  • the sequencer sends a READY signal.
  • the PSEQ sequencer is for example produced from the state diagram shown in FIG. 7.
  • the sequencer has an idle state of IDLE and. switches to a PROG1 state (programming of the first cell) on reception of the START signal.
  • the sequencer switches to a PROG2 state (programming of the second cell) on reception of the VERIF signal at 1, then switches to a PROG3 state on reception of the VERIF signal at 1, and so on to a PROG N state.
  • the sequencer in the PROG N state returns to the IDLE state by transmitting the READY signal when the VERIF signal goes to 1.
  • a time delay can be provided in the event that a cell fails to be programmed (anti-fuse element n ' never reaching the slammed state).
  • the sequencer switches to an ERROR state where it does not transmit the READY signal, and can only be returned to the IDLE state by the application of a RESET signal.
  • the programming sequencer is of course susceptible various other alternative embodiments and can also take the form of a shift register, as described more high, the signal VERIF being then used as signal of shift (SHIFT).
  • the number P of anti-fuse elements in each group of anti-fuse elements slammed simultaneously may not be constant during the programming of a row of memory cells.
  • the N / P ratio is not an integer
  • the last group of cells programmed simultaneously can be equal to the remainder of the division of N by P. For example, if a row of cells comprises 10 cells and the programming is carried out in groups of three, three simultaneous programming cycles of three cells may be provided, followed by a programming cycle of a single cell.
  • Vread voltage to the grids of the T2 transistors, T4 during the breakdown process, to make these conductors and monitor the cathode voltage of the elements anti-fuse from outputs OUT1 and OUT2, another voltage could be applied to them, for example the voltage Vhv.
  • an anti-fuse memory according to the invention can also comprise several columns of N bit lines each.
  • monitor cathode voltage e.g. logic gates having determined switching thresholds, amplifiers differentials, etc.
  • the memory cell selection time being negligible compared to the programming time
  • the time necessary to snap 200 anti-fuse elements is around of 200 * 0.5 or 100 ms with the method according to the invention.
  • This breakdown time is around 50 ms * 10, i.e. 500 ms with the process according to the prior art.
  • the gain in terms of time programming is thus 400 ms for the breakdown of 200 anti-fuse elements.

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EP03007639A 2002-04-04 2003-04-03 Speicherzellenprogrammierungsverfahren mit Durchbruch von Antischmelzsicherungen Withdrawn EP1361583A1 (de)

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FR0204184A FR2838233A1 (fr) 2002-04-04 2002-04-04 Procede de programmation de cellules memoire par claquage d'elements antifusible
FR0204184 2002-04-04

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI640995B (zh) * 2017-04-27 2018-11-11 力旺電子股份有限公司 記憶胞與記憶體胞陣列及其相關操作方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6775197B2 (en) 2002-11-27 2004-08-10 Novocell Semiconductor, Inc. Non-volatile memory element integratable with standard CMOS circuitry and related programming methods and embedded memories
US6816427B2 (en) * 2002-11-27 2004-11-09 Novocell Semiconductor, Inc. Method of utilizing a plurality of voltage pulses to program non-volatile memory elements and related embedded memories
US6775171B2 (en) * 2002-11-27 2004-08-10 Novocell Semiconductor, Inc. Method of utilizing voltage gradients to guide dielectric breakdowns for non-volatile memory elements and related embedded memories
US7321502B2 (en) * 2004-09-30 2008-01-22 Intel Corporation Non volatile data storage through dielectric breakdown
US7102951B2 (en) * 2004-11-01 2006-09-05 Intel Corporation OTP antifuse cell and cell array
US7323761B2 (en) * 2004-11-12 2008-01-29 International Business Machines Corporation Antifuse structure having an integrated heating element
US7377485B2 (en) * 2006-02-28 2008-05-27 Commander Products Llc Replacement motorized drive unit for boat lifts
US8129815B2 (en) 2009-08-20 2012-03-06 Power Integrations, Inc High-voltage transistor device with integrated resistor
KR101385251B1 (ko) 2008-04-02 2014-04-17 삼성전자주식회사 멀티 레벨 안티 퓨즈 및 그 동작 방법
US7715219B2 (en) * 2008-06-30 2010-05-11 Allegro Microsystems, Inc. Non-volatile programmable memory cell and memory array
US8164125B2 (en) 2010-05-07 2012-04-24 Power Integrations, Inc. Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit
US8305826B2 (en) * 2010-05-07 2012-11-06 Power Integrations, Inc. Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit
JP6103815B2 (ja) * 2012-04-13 2017-03-29 ラピスセミコンダクタ株式会社 不揮発性メモリ回路、及び半導体装置
FR2990291A1 (fr) 2012-05-03 2013-11-08 St Microelectronics Sa Procede de controle du claquage d'un antifusible
KR20140011790A (ko) * 2012-07-19 2014-01-29 삼성전자주식회사 멀티 레벨 안티퓨즈 메모리 장치 및 이의 동작 방법
JP2016134515A (ja) * 2015-01-20 2016-07-25 ソニー株式会社 メモリセルおよびメモリ装置
US9536926B1 (en) * 2015-12-22 2017-01-03 International Business Machines Corporation Magnetic tunnel junction based anti-fuses with cascoded transistors
DE112016006170B4 (de) * 2016-01-08 2021-07-29 Synopsys, Inc. Puf-werterzeugung unter verwendung einer anti-schmelzsicherungs-speicheranordnung
CN116486875A (zh) * 2022-01-17 2023-07-25 长鑫存储技术有限公司 反熔丝存储器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497475A (en) * 1993-02-05 1996-03-05 National Semiconductor Corporation Configurable integrated circuit having true and shadow EPROM registers
US5684732A (en) * 1995-03-24 1997-11-04 Kawasaki Steel Corporation Semiconductor devices
US6055173A (en) * 1995-08-31 2000-04-25 Micron Technology, Inc. Circuit for programming antifuse bits
US6229733B1 (en) * 1999-03-24 2001-05-08 Texas Instruments Incorporated Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide
US20020136076A1 (en) * 2001-03-21 2002-09-26 Bendik Kleveland Memory device and method for sensing while programming a non-volatile memory cell
WO2002078003A2 (en) * 2001-03-21 2002-10-03 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US136076A (en) * 1873-02-18 Improvement in molasses-pitcher tops
US3131605A (en) * 1963-01-14 1964-05-05 Oilgear Co Flat valve for hydraulic machine
DE1703347A1 (de) * 1968-05-06 1972-01-13 Mannesmann Meer Ag Hydrostatische Axialkolbenmaschine
US3585901A (en) * 1969-02-19 1971-06-22 Sundstrand Corp Hydraulic pump
GB1272971A (en) * 1969-03-13 1972-05-03 Nat Res Dev Hdyrostatic vehicle transmission
US3807283A (en) * 1970-05-18 1974-04-30 Cessna Aircraft Co Axial piston pump or motor
US3710297A (en) * 1972-02-04 1973-01-09 Nippon Denzai Ltd A stretched fuse device
US3975990A (en) * 1973-11-12 1976-08-24 Clark Equipment Company Midplane porting block for an axial piston machine
US5201692A (en) * 1991-07-09 1993-04-13 Hydro-Gear Limited Partnership Rider transaxle having hydrostatic transmission
US5230274A (en) * 1992-02-11 1993-07-27 Vickers Incorporated Variable displacement hydraulic pump with quiet timing
US6122996A (en) * 1998-11-20 2000-09-26 Hydro-Gear Limited Partnership Hydrostatic transmission
US5838625A (en) * 1996-10-29 1998-11-17 Micron Technology, Inc. Anti-fuse programming path
SE514196C2 (sv) * 1997-12-08 2001-01-22 Parker Hannifin Ab Hydraulisk roterande axialkolvmaskin

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497475A (en) * 1993-02-05 1996-03-05 National Semiconductor Corporation Configurable integrated circuit having true and shadow EPROM registers
US5684732A (en) * 1995-03-24 1997-11-04 Kawasaki Steel Corporation Semiconductor devices
US6055173A (en) * 1995-08-31 2000-04-25 Micron Technology, Inc. Circuit for programming antifuse bits
US6229733B1 (en) * 1999-03-24 2001-05-08 Texas Instruments Incorporated Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide
US20020136076A1 (en) * 2001-03-21 2002-09-26 Bendik Kleveland Memory device and method for sensing while programming a non-volatile memory cell
WO2002078003A2 (en) * 2001-03-21 2002-10-03 Matrix Semiconductor, Inc. Method and apparatus for biasing selected and unselected array lines when writing a memory array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI640995B (zh) * 2017-04-27 2018-11-11 力旺電子股份有限公司 記憶胞與記憶體胞陣列及其相關操作方法

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