Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/122—Single quantum well structures
  • H01L29/125—Quantum wire structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/122—Single quantum well structures
  • H01L29/127—Quantum box structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
  • H01L29/1608—Silicon carbide

Definitions

• the present invention relates to nanostructures with negative differential resistance
• the invention applies in particular to the field of nanoelectronics.
• it makes it possible to obtain structures that behave like one - dimensional Esaki diodes on the atomic scale.
• the conventional diode tunneling diodes or Esaki diodes are generally made of an electron-poor p-type semiconductor material and an electron-rich n-type semiconductor material. At the junction between these two materials appears a region of charge of space (in English, space-charge region), called ZCE (in English, SCR).
• the Fermi level must be in the valence band on the p side and in the conduction band on the n side, (b) the thickness of the ECA must be small enough for the tunneling probability to be sufficient, and (c) at the same energy, electrons and holes must be available in the conduction band and in the valence band, respectively.
• the Esaki diodes thus have a negative differential resistance or RDN (in English,
• a tunneling diode may be prepared by forming a two-layer heterostructure, for example from III-V semiconductor compounds. These compounds may be chosen for example from GaAs, GaP, GaN and GaAlAs.
• This document [2] discloses structures consisting of sites that are located on a particular surface. These sites are formed using the tip of a tunneling microscope and have an RDN.
• the particular surface employed is prepared by exposing a silicon (111) surface to decaborane at a temperature above 500 ° C. This surface is then treated by thermal annealing.
• the authors of the document [2] note the presence of pads whose density of electronic states is greater for regions covered with a boron atom. These regions have an RDN.
• This document discloses a method for manufacturing planar unidimensional nanostructures. They are obtained by forming parallel atomic lines, on the surface of a silicon carbide substrate, then by depositing and selectively adsorbing a material between these atomic lines, but not on these lines.
• the resulting strips can be passivated with NO, NH 3 or sulfur, or can be made electrically conductive with a metal such as potassium.
• the present invention relates to negative differential resistance nanostructures, which are of great interest in nanoelectronics, as well as to a method for manufacturing these nanostructures.
• nanostructures having a negative differential resistance can be obtained by forming certain structures, in particular quantum dots, also known as nanocrystals, or parallel atomic lines, on the surface of a silicon carbide substrate, and depositing a metal on this surface until the metal covers at least said structures.
• the subject of the present invention is a nanostructure having a negative differential resistance, this nanostructure being characterized in that it comprises:
• each structure can be a quantum pad or an atomic line.
• Quantum dot in English, quantum dot
• isolated atoms such as atoms or dimers of silicon or silver on an SiC surface.
• atomic segment the inventors mean a short atomic line, having from one to four atoms in width and one hundred atoms in length.
• aggregate in English, cluster
• the inventors mean a grouping of more than fifty atoms (in 2 or 3 dimensions), such as atoms or dimers of silicon or silver on a surface of SiC.
• the metal deposition has a thickness ranging from one to five atomic monolayers.
• the structure or structures consist of silicon.
• the structure or structures consist of carbon.
• the silicon carbide (SiC) has a cubic structure.
• the surface is a surface (100) of the cubic silicon carbide substrate.
• the metal is preferably selected from metals having a solid band (eg, Ag, Au, Cu), alkali metals, transition metals, alkaline earth metals and rare earths.
• the metal is silver.
• the present invention furthermore relates to a method of manufacturing a nanostructure having a negative differential resistance, said method being characterized in that it comprises the following steps:
• each structure or at least one plurality of said at least one structure is formed on the surface of a silicon carbide substrate, the structure being chosen from among the quantum dots, the atomic segments, the atomic lines and the aggregates. and a metal is deposited on said surface until said metal covers at least the structure or at least the plurality of said at least one structure, or the combination of two or more such structures.
• each structure can be a quantum pad or an atomic line.
• the thickness of the deposited metal represents one to five atomic monolayers of this metal.
• the structure or structures consist of silicon.
• the structure or structures consist of carbon.
• the silicon carbide has a cubic structure (polytype 3C (or ⁇ )).
• the surface is a surface (100) of the cubic silicon carbide substrate.
• the density of structures can be controlled and adjusted to make isolated structures, ranging from an isolated quantum pad, or an isolated atomic line, to a superimposed network (in English, super-lattice) structures variously distributed on the surface, for example massively parallel atomic lines, as required and according to a method known from the following document:
• control and the adjustment of the density at the surface are realized by self-organization, by means of the temperature and the annealing time, the displacement of the quantum plots according to the crystalline arrangement present.
• the quantum pads can also be moved by modulating the temperature.
• the deposited metal is preferably chosen from metals whose band d is solid, alkali metals, such as lithium or rubidium, metals such as platinum or palladium, alkaline earth metals and rare earths.
• this metal is silver.
• the thickness of the metal deposit is preferably a few atomic monolayers.
• it is preferably two to three monolayers for silver, and one to two monolayers for a metal, such as cesium, whose atoms have a large radius.
• One-dimensional nanostructures having RDNs in accordance with the invention are of great interest in the field of very fast switching and the domain of oscillators and atomic-scale devices working at very high frequencies.
• the resulting structures are thus real active components, which is unprecedented.
• FIG. 1 represents an SPS curve, or tunnel spectroscopy curve, in which the intensity I, expressed in nA, is plotted as a function of the voltage V, expressed in mV, for conditions of regulation of the emission of electrons such that the points of sonign (regulation) of the current are little different from 10 nA and the point of setpoint (regulation) of the voltage is little different from 4.9 V,
• FIG. 2 is an enlargement of zone I of the curve of FIG. 1;
• FIGS. 3 to 5 are diagrammatic sectional views of examples of nanostructures conforming to
• FIG. 6 is an STM image of an SiC surface comprising quantum lines and pads of Si which are covered with silver and have a negative differential resistance Rd,
• FIG. 7 is a schematic view of a surface carrying quantum dots formed according to the present invention.
• FIG. 8 is a schematic view of a surface on which quantum pads have been formed and organized in accordance with the invention.
• FIG. 9 is a schematic sectional view of a substrate whose surface carries a metal-covered quantum pad in accordance with the invention.
• FIG. 10 is a schematic sectional view of a substrate whose surface carries a plurality of quantum pads which are organized and covered with metal according to the invention
• FIG. 11 is a schematic top view of the surface of FIG. a substrate carrying quantum dots on which a metal is deposited through a mask.
• a surface of ⁇ -SiC (100) covered with atomic lines of Si which is based on a reconstructed surface c (4x2) is prepared.
• atomic lines For the general preparation of atomic lines, refer to the following document:
• This 3x2 surface consists of extremely dense atomic silicon lines, resting on a surface entirely composed of silicon atoms. New anneals make it possible to reduce the density of these lines in a controlled manner and make it possible, for example, to reach densities of 3x2, 5x2 or even 8x2.
• a source of money is prepared and calibrated. To do this a source of silver atoms is placed in an ultrahigh vacuum chamber and degassed neatly. The source is considered sufficiently degassed when the pressure increase in the chamber, during the time required to evaporate a monolayer of silver, does not exceed 2 x ICT 9 Pa.
• the next step is to deposit silver atoms on the previously obtained surface.
• the procedure to follow is given below.
• the SiC surface comprising the silicon atomic lines, is then introduced into the ultra-high vacuum chamber and placed about 3 cm from the silver source.
• the source is then heated by a suitable means such as the Joule effect.
• Silver atoms then evaporate from the source and settle on the SiC surface.
• the thickness of the silver deposit is controlled by means of a quartz scale.
• the silver atoms are deposited so as to cover the atomic lines of silicon.
• the amount of silver to be deposited corresponds to about three atomic monolayers.
• the silver is deposited so that it completely covers the silicon atoms of the surface and the lines formed on this surface.
• the formed surface has a c-4x2 type reconstruction.
• the resulting nanostructure has an RDN.
• STS tunneling spectroscopy
• the atomic lines of Si, which are covered with silver give an I (V) response which has a negative differential resistance. This is not the case of the surface which is also covered with silver (2x3) but located between the lines.
• the spectroscopic curve I (V) can be seen in absolute value, on a linear scale, for the covered atomic lines.
• the RDN is better highlighted in Figure 2 which is an enlargement of Part I of Figure 1, delimited by dashed lines.
• curve I (V) of FIG. 1 represents the variations of the intensity I of the current which passes through the tunneling effect between the tip of the microscope used and the sample studied, as a function of the voltage V between the tip and the sample.
• the tip of the microscope was able to scan the sample and the typical response occurred at each atomic line crossing.
• FIGS. 3 to 5 are diagrammatic sectional views of examples of RDN nanostructures according to the invention, formed on a surface (100) a silicon carbide substrate 2 having a cubic structure.
• the nanostructure of FIG. 3 comprises a single atomic line 4 of silicon on the surface of the substrate 2. This line 4 is covered with a layer of silver 6 whose thickness represents a few monolayers of silver, preferably three monolayers.
• the nanostructure of FIG. 4 comprises several parallel silicon atomic lines 8 formed on the surface (100) of the substrate 2.
• the curve 6 covers each line 8 as well as the parts of the surface (100) which are included between these lines.
• the nanostructure of FIG. 5 comprises several sets of silicon atomic lines 12 which are parallel to one another. These sets are spaced apart from each other. Moreover, in each set, a silver layer 14, the thickness of which represents a few atomic layers of silver, covers the atomic lines of this set as well as the parts of the surface (100), which lie between these lines. .
• masks may be used to deposit the silver layers at the desired locations.
• a surface of ⁇ -SiC (100) covered with atomic lines of Si which is based on a reconstructed surface c (4x2), and the steps a) and b), which were discussed above, and the following step are performed: c) Thermal annealing, typically carried out between 800 0 C and 1200 0 C, a portion of the deposited silicon is evaporated in a controlled manner until the surface has the following nanostructures: isolated quantum dots (silicon dimers), silicon atom segments or silicon aggregates. This organization of the surface can be controlled by electron diffraction.
• the silver is then deposited in a small quantity.
• the silver is advantageously deposited on the isolated quantum dots; but it can also be deposited on the surface surrounding the studs.
• the SiC surface comprising the nanostructures as defined above, is then introduced into the ultra-high vacuum chamber and placed about 3 cm from the silver source.
• the source is heated by a suitable means such as the Joule effect.
• Silver atoms then evaporate from the source and settle on the SiC surface.
• the thickness of the silver deposit is controlled by means of a quartz scale.
• the silver atoms are deposited so as to cover the silicon nanostructures.
• the amount of money to be deposited corresponds to three monolayers about atomic. In order to operate a more precise control on the depot, it is still possible to use the mask or masks mentioned above.
• the silver is deposited in such a way that it completely covers the silicon nanostructures.
• the formed surface has a c-2x4 type reconstruction.
• the new nanostructures obtained have an RDN.
• RDN the response of the surface obtained by STS, that is to say by tunneling spectroscopy (in English, scanning tunneling spectroscopy).
• the nanostructures of Si, which are covered with silver, give an I (V) response which has a negative differential resistance. This is not the case of the surface which is also covered with silver (2x3) but located between the nanostructures.
• FIG. 6 one can see the image obtained by STM, that is to say the scanning tunneling microscopy image (in English, scanning tunneling microscopy), in topographic mode, of a surface of SiC comprising quantum lines and plots of Si which are coated with silver and have a negative differential resistance Rd.
• the latter is measured by tunneling spectroscopy (STS) and is negative when passing vertically from a plot or an atomic line that has been covered with silver.
• STS tunneling spectroscopy
• FIG. 6 where the variations of Rd along a line parallel to an axis X are shown, the Y axis of FIG. 6 being perpendicular to X.
• a set of nanostructures having a negative differential resistance has therefore been manufactured. These nanostructures behave as "Esaki diodes" of low dimensionality, such as one-dimensional at the atomic scale.
• Figure 7 is a schematic view of the surface 16 of an SiC substrate, on which silicon quantum pads 18 have been formed in accordance with the invention.
• Figure 8 is a schematic view of the surface of an SiC substrate, on which silicon quantum pads 22 have been formed in accordance with the invention and then organized.
• FIG. 9 is a diagrammatic sectional view of an SiC substrate 24, the surface of which carries a silicon quantum pad 26, which was formed and then covered with a metal 28 such as silver, in accordance with the invention .
• FIG. 10 is a diagrammatic sectional view of an SiC substrate 30, the surface of which bears a plurality of silicon quantum pads 32, which have been formed in accordance with the invention and then arranged and then covered with a metal 34 such as silver, according to the invention.
• a metal 34 such as silver
• the space between the pads has also been covered with metal.
• FIG. 11 shows the surface 36 of an SiC substrate on which silicon quantum pads 38 have been formed, in accordance with the invention, and then these pads have been organized.
• this mask has an opening 42 through which the silver atoms to deposit on the surface.
• a more complex mask having several openings, or even several masks, to deposit the silver in various areas of the surface, spaced apart from each other.
• the nanostructures according to the invention behave like Esaki diodes in that, like the latter, they have an RDN.
• nanostructures are metal-semiconductor junctions. It should also be mentioned that a further advantage of the present invention lies in the fact that the surfaces carrying the nanostructures coated with a metal according to the invention can serve as an information storage device because the nanostructures are easily detectable by reading by means of of a near field effect microscope tunnel (in English, scanning tunnelling near-field microscope).
• the topography of the surface, on which the nanostructures are formed becomes a real map and that the nanostructures can be more or less spaced. It is therefore possible to store information between these nanostructures or in zones containing these nanostructures and to find the defined spaces since each zone is identifiable, which makes it possible to count them and thus to reach the searched space.
• the zones can be specifically identified for example by the number of nanostructures or by the arrangement thereof.
• silicon (metal-coated) nanostructures instead of silicon (metal-coated) nanostructures, carbon nanostructures (metal coated) can be formed and used.
• a cubic structure for the silicon carbide substrate instead of a cubic structure for the silicon carbide substrate, other structures may be used, for example a hexagonal structure or a rhombohedral structure.

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• 2006
  • 2006-06-29 WO PCT/EP2006/063692 patent/WO2007003576A1/fr not_active Application Discontinuation
  • 2006-06-29 JP JP2008518850A patent/JP2009500815A/ja active Pending
  • 2006-06-29 US US11/922,970 patent/US20100072472A1/en not_active Abandoned
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