EP1894223A2 - Matrices et detecteurs haute sensibilite, haute resolution - Google Patents

Matrices et detecteurs haute sensibilite, haute resolution

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Publication number
EP1894223A2
EP1894223A2 EP06772574A EP06772574A EP1894223A2 EP 1894223 A2 EP1894223 A2 EP 1894223A2 EP 06772574 A EP06772574 A EP 06772574A EP 06772574 A EP06772574 A EP 06772574A EP 1894223 A2 EP1894223 A2 EP 1894223A2
Authority
EP
European Patent Office
Prior art keywords
layer
avalanche
integrator
governor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06772574A
Other languages
German (de)
English (en)
Inventor
Dmitry A. Shushakov
Vitaly E. Shubin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amplification Technologies Inc
Original Assignee
Amplification Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amplification Technologies Inc filed Critical Amplification Technologies Inc
Publication of EP1894223A2 publication Critical patent/EP1894223A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J47/00—Tubes for determining the presence, intensity, density or energy of radiation or particles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the present invention relates to single-channel and multi-channel detectors capable of recording low-level signals which may include as few as several electrons.
  • the invention is an amplifying avalanche device wherein amplification is realized via a multi-layered, solid-state intelligent amplifier design.
  • Background Art The detection and recording of low-level signals is particularly challenging to sensor devices. For example, the sensitivity, selectivity, operational range, and arrayed arrangements of such devices require precision detection of signals comprising as few as several electrons.
  • One widespread approach for detecting and recording low-level signals includes charge-sensitive amplifiers on field-effect transistors having a threshold sensitivity of a few dozen electrons, as described by Albert J. P. Theu Giveaway in Solid- State Imaging with Charge-Coupled Device, published by Kluwer in 1995 (ISBN 0- 7923-3456-6).
  • Another approach includes output video signal amplifiers in a charge coupled device ensuring nearly the same sensitivity as charge-sensitive amplifiers on field-effect transistors.
  • Yet another approach to sensing weak electrical signals is the use of avalanche amplification or multiplication of signal carriers, which generally is the most sensitive and high-speed method of amplification.
  • Avalanche-type devices include those described by F.
  • Avalanche amplification is based on impact ionization arising in a strong electric field, wherein the signal carriers accelerating in an electric field ionize the atoms of the working medium of the amplifier, thus resulting in multiplication (e.g., duplication) of the signal carriers.
  • multiplication e.g., duplication
  • the internal (excessive) noise level and response time grow rapidly with an increasing multiplication factor.
  • avalanche photodiodes use a rather low multiplication factor, M, typically less than 10 3 , which prevents the detection and recording of signals consisting of several electrons in a wide band.
  • Avalanche multiplication has also been applied to recording individual ionizing particles using a Geiger-Muller counter, as described by Ekstrom in USPN 4,303,861. A particle entering such a device initiates an avalanche-like process of multiplication of the signal carriers up to a necessary recording level. More recently, this principle has been successfully used for recording single charge carriers in semiconductor avalanche-type photodiodes.
  • each channel is equipped with an integrator to accumulate an amplified charge signal packet. After receiving a required charge packet, an integrator communicates with a quantifier through a governor, which turns the channel OFF. A governor is used to control the potential of the quantifier and to drain the charge from the integrator for the purpose of transferring the channel back to its initial state. It may be appreciated, therefore, that there remains a need for further advancements and improvements thus enabling the detection of weak signals.
  • amplifying avalanche structures compatible with the system and method provided by Shushakov et al. in USPN 6,885,827, capable of further advancing and improving the detection of weak signals.
  • An object of the present invention is to provide amplifying avalanche structures compatible with the system and method provided by Shushakov et al. in USPN 6,885,827 and capable of further advancing and improving the detection of weak signals.
  • various embodiments of the amplifying avalanche structure are disclosed operating based on the principles described by Shushakov et al.
  • the present invention includes transparent and non- transparent electrodes, avalanche region, quantifier, integrator, governor, and substrate arranged to detect a weak signal composed of as few as several electrons.
  • Avalanche amplifying structures include: normal quantifier, reverse bias designs; normal quantifier, normal bias designs; lateral quantifier, normal bias designs; changeable quantifier, normal bias, adjusting electrode designs; normal quantifier, normal bias, adjusting electrode designs; and lateral quantifier, normal bias, annular integrator designs. Amplifying structures are likewise arranged to form multi-channel devices.
  • the amplifying avalanche structure operating in the Geiger mode includes two electrodes, an avalanche region, an integrator for the accumulation of a signal charge, a quantifier for turning the avalanche process ON and OFF, and a governor for draining the charge from the integrator consisting of a semiconductor structure disposed on a planar substrate, in which the governor and integrator are disposed sequentially behind one of the electrodes, the avalanche region adjoins the edge periphery of the integrator area in such a manner that there is no electric contact between the avalanche region and the governor, and the quantifier is provided by the integrator surface adjoining the avalanche region.
  • the governor may be composed of the same semiconductor material as the avalanche region but with less doping or having a wider band gap.
  • the substrate on the lower side of the amplifying avalanche structure may be a highly doped layer having the same type of conductivity and composed of the same semiconductor material as the avalanche region.
  • the substrate may also be composed of a semiconductor material of the same conductivity type as, but less doped than, the avalanche region material.
  • the substrate On the lower contact side, the substrate may have a highly doped contact layer of the same conductivity type as the avalanche region.
  • the contact to the avalanche region can be effected through an electrode disposed on the back or bottom side of the substrate or through an electrode disposed on the upper side of the substrate.
  • the entire upper surface of the amplifying avalanche structure may be covered with a dielectric layer, except for the areas on which the governor is disposed.
  • the dielectric layer is disposed on the upper surfaces of the integrator and avalanche region, and the electrode contacting the governor layer occupies the entire upper surface of the avalanche structure or the governor with upper electrode is disposed along the surface of the avalanche structure.
  • the upper electrode may be disposed along the entire surface of the avalanche structure and the electrode may be transparent.
  • the amplifying avalanche structure may include a signal-transport layer disposed along one side of the avalanche region and composed of the same semiconductor material and conductivity type with at most as much doping as the avalanche region or having a narrower band gap than the avalanche region.
  • the substrate and all layers may be composed of the same semiconductor material, examples including Si, SiC, GaN, GaAs and GaP.
  • the amplifying avalanche structure may have an additional conductive contact area disposed between the integrator and the governor in such a manner that it has no direct electric contact with the avalanche region and a blocking layer on the upper surfaces of the integrator and avalanche region having no electric contact with the upper electrode contacting the governor.
  • the dielectric layer may be applied onto the entire upper surface of the blocking layer and the upper electrode contacting the governor can occupy the entire upper surface of the avalanche structure.
  • the blocking layer may be composed of a semiconductor material of the same conductivity type and have at most as much doping as the avalanche region.
  • the blocking layer may be composed of a semiconductor material of the opposite conductivity type and have less doping than the avalanche region.
  • the avalanche amplifying structure operating in the Geiger mode disposed along a planar substrate includes two electrodes, a governor disposed between the substrate and the upper first electrode, an integrator disposed on the side periphery of the governor, and an avalanche region disposed on the external side periphery of the integrator wherein the quantifier is performed by the integrator surface adjoining the avalanche region.
  • the substrate is made of a material with the same conductance type as the avalanche region, but with a higher resistivity.
  • the amplifying structure may include a dielectric layer disposed along the upper surfaces of the integrator and avalanche region, and the upper first electrode contacting the governor layer covers the entire upper surface of the avalanche structure.
  • the amplifying structure on the upper surfaces of the integrator and avalanche region may include a blocking layer comprised of a semiconductor with the same conductance type as the avalanche region, but with a higher resistivity. No electric contact is permitted by the blocking electrode with the upper electrode in contact with the governor.
  • the amplifying avalanche structure operating in the Geiger mode includes two electrodes, an avalanche region, an integrator for the accumulation of a signal charge, a quantifier for turning the avalanche process ON and OFF, and a governor for draining the charge from the integrator, in which the governor and integrator are disposed sequentially behind one of the electrodes, the avalanche region adjoins the edge periphery of the integrator to avoid electric contact by the avalanche region with the governor, and the quantifier is provided by the integrator surface adjoining the avalanche region including a third electrode disposed on the dielectric layer contacting the avalanche region.
  • the substrate may be composed of a semiconductor material with the same conductivity type, but less doped, than the avalanche region material. Furthermore, a conductive contact area may be disposed between the integrator and the governor so as to avoid direct electric contact with the avalanche region and between the surfaces of the integrator and the avalanche region, on the one side, and the dielectric layer, on the other side, a blocking layer may be disposed of a semiconductor material of the same conductivity type as that of the avalanche region but with a lower doping impurity concentration.
  • the amplifying avalanche structure operating in the Geiger mode may include an avalanche region, an integrator for the accumulation of a signal charge, a quantifier for turning the avalanche process ON and OFF, and a governor for draining the charge from the integrator and controlling the quantifier disposed on a heavily doped substrate between two electrodes, on which there are disposed layers of an avalanche region composed of a material with the same conductivity type but having a higher resistivity.
  • the integrator may be composed of a heavily doped semiconductor material having a conductivity opposite that of the substrate, a governor of a high-impedance semiconductor material, and the quantifier provided at the interface between the avalanche region and integrator.
  • the integrator may have a low conductance in directions parallel to the substrate plane.
  • the substrate and all layers of the amplifying avalanche structure, except the governor, may be composed of the same semiconductor material.
  • the governor layer may be composed of the same material or of a material having a wider band gap than that of which the other layers and the substrate are composed.
  • the amplifying avalanche structure may include a signal- transport layer capable of generating free charge carriers and transporting the charges into the avalanche region.
  • the substrate &nd all layers may be composed of the same semiconductor material, examples including Si, SiC, GaN, GaAs and GaP.
  • the avalanche amplifying structure operating in the Geiger mode includes a planar laminated semiconductor structure mounted on a substrate between two electrodes, in which the layers of the avalanche region and governor capable of draining the charge from the integrator and controlling the quantifier are disposed sequentially one after another, and the function of the integrator capable of accumulating a signal charge and the function of the quantifier for turning the avalanche process ON and OFF are performed at the interface between the avalanche region and the governor.
  • the interface between the avalanche region and governor may have a low conductance in directions parallel to the substrate plane.
  • the avalanche amplifying structure operating in the Geiger mode may consist of a planar laminated semiconductor structure, disposed between two electrodes on a heavily doped substrate on which there are arranged in succession the layers of the avalanche region composed of a semiconductor with the type of conductance opposite that of the substrate, and a governor composed of a high impedance semiconductor material so that the quantifier is provided at the interface between the substrate and avalanche region, and the integrator is provided at the interface between the avalanche region and governor.
  • the avalanche amplifying structure operating in the Geiger mode may consist of a planar laminated semiconductor structure, disposed between two electrodes on a heavily doped substrate, on which there are arranged in succession the layers of a governor composed of a high-impedance semiconductor material, an integrator composed of a heavily doped material with the same conductance type as the substrate material, and an avalanche region composed of a semiconductor having the conductance type opposite that of the substrate so that the quantifier is provided at the interface between the avalanche region and the integrator.
  • All layers and the substrate may be composed of the same semiconductor material or all layers, except for the governor, may be composed of the same semiconductor material, and the governor layer composed of a material having a wider band gap than the other layers and substrate.
  • a signal- transport layer may be disposed between the upper electrode and the avalanche region and capable of generating free charge carriers and transporting the charges into the avalanche region.
  • All layers, except for signal-transport layer may be composed of the same semiconductor material, whereas the signal-transport layer may be composed of a narrower band gap semiconductor material or a high-resistance semiconductor material with the same conductance type as the avalanche region.
  • the substrate and all layers may be composed of the same semiconductor material, examples including Si, SiC, GaN, GaAs and GaP.
  • each individual structure can be used as a self-contained functional device similar to a Geiger avalanche photodiode, or single photon avalanche diodes (SAPDs), or internal discrete amplifier, but are also particularly well suited for integration to provide a multi-channel internal discrete amplifier, or multi-channel Geiger mode amplifier, or multi-channel SAPD array.
  • SAPDs single photon avalanche diodes
  • these devices may be completely homogeneous semiconductor devices, such as being based entirely on silicon.
  • these devices may be implemented with other materials, including compound semiconductors, and need not be homogeneous, but may include heterogeneous components.
  • monocrystalline silicon as the semiconductor material throughout the device
  • other monocrystalline, polycrystalline, elemental, and/or compound semi-conducting materials may be used to implement one or more component(s), layer(s), or part(s) of the discrete devices and/or arrays.
  • the governor may be implemented via a wider band gap material, while the signal transport region has a lower band gap material than the other layers.
  • various other insulating and conductive (e.g., metal) materials may be employed other than those explicitly described herein, as understood by those skilled in the art.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with the present invention.
  • FIG. 1A-1C are schematic cross-section views for several illustrative embodiments of the present invention comprising an avalanche amplifying structure with a reverse-bias direction of avalanche showing the positional relationship of electrodes, avalanche region, quantifier, integrator, governor, substrate, and optional signal transport layer;
  • FIG. 2A shows a sequence of material layers corresponding to the structure of FIG. IA;
  • FIGS. 2B-2C depict energy band diagrams corresponding to the material layer structure shown in FIG. 2A during various operational conditions of the amplifier;
  • FIG. 2D depicts functional components of the avalanche amplifying structure shown in FIG. IA;
  • FIG. 3 shows a cross-sectional view of a reverse-bias avalanche amplifying structure with both hole and electron integrators, in accordance with an embodiment of the present invention
  • FIG. 4 depicts functional components of the avalanche amplifying structure shown in FIG. 3
  • FIG. 5 shows a cross-sectional view of a reverse-bias avalanche amplifying structure with hole, electron integrators, and buried channel for holes, in accordance with an embodiment of the present invention
  • FIGS. 6A-6B shows a cross-sectional view of two reverse-bias avalanche amplifying structures, in accordance with embodiments of the present invention
  • FIG. 7A-7C are schematic cross-section views for several illustrative embodiments of the present invention comprising an avalanche amplifying structure with normal direction of avalanche showing the positional relationship of electrodes, avalanche region, quantifier, integrator, governor, substrate, and optional signal transport layer;
  • FIG. 8 A shows a sequence of material layers corresponding to the structure of FIG. 7A;
  • FIGS. 8B-8C depict energy band diagrams corresponding to the material layer structure shown in FIG. 8A during various operational conditions of the amplifier;
  • FIG. 9 shows a cross-sectional view of a normal-direction avalanche amplifying structure with ring guard region, in accordance with an embodiment of the present invention;
  • FIG. 10 shows a cross-sectional view of a normal-direction avalanche amplifying structure with high field implant, in accordance with an embodiment of the present invention
  • FIG. 11 shows a cross-sectional view of a normal-direction avalanche amplifying structure with backside illumination, in accordance with an embodiment of the present invention
  • FIG. 12 shows a cross-sectional view of a normal-direction avalanche amplifying structure with high field implant and hole integrator, in accordance with an embodiment of the present invention
  • FIG. 13 depicts functional components of the normal-direction avalanche amplifying structure shown in FIG. 12;
  • FIG. 13 depicts functional components of the normal-direction avalanche amplifying structure shown in FIG. 12;
  • FIG. 14 shows a cross-sectional view of a normal-direction avalanche amplifying structure with ring guard and hole integrator, in accordance with an embodiment of the present invention
  • FIG. 15A- 150 are schematic cross-section views for various illustrative embodiments of the present invention comprising an avalanche amplifying structure operating in the Geiger mode with a lateral direction of avalanche showing the positional relationship of electrodes, avalanche region, quantifier, integrator, governor, and substrate and optional dielectric layer, signal transport layer, blocking layer, contact region, and third electrode
  • FIG. 16 shows a cross-sectional view of a lateral-direction avalanche amplifying structure, in accordance with an embodiment of the present invention
  • FIG. 17 depicts functional components of the lateral-direction avalanche amplifying structure shown in FIG. 16;
  • FIG. 18 shows a cross-sectional view of a lateral-direction avalanche amplifying structure including InGaAsP, in accordance with an embodiment of the present invention;
  • FIG. 19 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a pair of electrodes aligned along one side the device, in accordance with an embodiment of the present invention;
  • FIG. 20 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with three electrodes, in accordance with an embodiment of the present invention;
  • FIG. 21 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a single large electrode aligned along one side of the device, in accordance with an embodiment of the present invention
  • FIG. 22 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a blocking layer, in accordance with an embodiment of the present invention
  • FIG. 23 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a buried channel and a single large electrode along the upper side of the device, in accordance with an embodiment of the present invention
  • FIG. 24 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a buried channel and three electrodes, in accordance with an embodiment of the present invention
  • FIG. 25 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a hole integrator and a single large electrode along the upper side of the device, in accordance with an embodiment of the present invention
  • FIG. 26 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a buried channel, hole integrator, and three electrodes, in accordance with an embodiment of the present invention
  • FIG. 25 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a hole integrator and a single large electrode along the upper side of the device, in accordance with an embodiment of the present invention
  • FIG. 26 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a
  • FIG. 27 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a hole integrator and a pair of electrodes oppositely disposed about the device, in accordance with an embodiment of the present invention
  • FIG. 28A-28B are schematic cross-section views for two illustrative embodiments of the present invention comprising an avalanche amplifying structure with a normal direction of avalanche, MIS-based with drain, and three electrodes showing the positional relationship of electrodes, avalanche region, quantifier, integrator, governor, substrate, and dielectric layer;
  • FIG. 29 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a normal direction of avalanche, MIS-based with drain, and three electrodes, in accordance with an embodiment of the present invention
  • FIG. 30A shows a sequence of material layers corresponding to the structure of FIG. 29
  • FIGS. 30B-30C depict energy band diagrams corresponding to the material layer structure shown in FIG. 3OA during various operational conditions of the amplifier
  • FIG. 3OD depicts functional components of the avalanche amplifying structure shown in FIG. 29
  • FIG. 30A shows a sequence of material layers corresponding to the structure of FIG. 29
  • FIGS. 30B-30C depict energy band diagrams corresponding to the material layer structure shown in FIG. 3OA during various operational conditions of the amplifier
  • FIG. 3OD depicts functional components of the avalanche amplifying structure shown in FIG. 29
  • FIG. 31 shows a cross-sectional view of a lateral-direction avalanche amplifying structure with a normal direction of avalanche, MIS-based with drain, and three electrodes, in accordance with an embodiment of the present invention
  • FIG. 32A shows a sequence of material layers corresponding to the structure of FIG. 31
  • FIGS. 32B-32C depict energy band diagrams corresponding to the material layer structure shown in HG. 32A during various operational conditions of the amplifier
  • FIG. 32D depicts functional components of the avalanche amplifying structure shown in FIG. 31;
  • FIG. 32A shows a sequence of material layers corresponding to the structure of FIG. 31
  • FIGS. 32B-32C depict energy band diagrams corresponding to the material layer structure shown in HG. 32A during various operational conditions of the amplifier
  • FIG. 32D depicts functional components of the avalanche amplifying structure shown in FIG. 31
  • FIG. 32A shows a sequence of material layers corresponding to the structure of FIG. 31
  • FIG. 33 is a schematic cross-sectional view for one exemplary embodiment of the present invention comprising an avalanche amplifying structure with a lateral direction of avalanche and hole integrator showing the positional relationship of electrodes, avalanche region, quantifier, integrator, governor, substrate, dielectric layer, and signal transport layer;
  • FIG. 34 is a schematic cross-sectional view of an exemplary multi-channel device composed of the lateral-direction avalanche amplifying structure shown in FIG. 33;
  • FIG. 35 shows a cross-sectional view of the multi-channel device shown in FIG. 34 composed of the lateral-direction avalanche amplifying structure shown in FIG. 33, in accordance with an embodiment of the present invention;
  • FIG. 34 is a schematic cross-sectional view of an exemplary multi-channel device composed of the lateral-direction avalanche amplifying structure shown in FIG. 33;
  • FIG. 35 shows a cross-sectional view of the multi-channel device shown in FIG. 34 composed of the
  • FIG. 36 is a top plan view of a multi-channel device shown in FIG. 37, in accordance with an embodiment of the present invention
  • FIG. 37 is a top plan view of a multi-channel device with a single electrode, in accordance with an embodiment of the present invention
  • FIGS. 38A-38B are cross-sectional views of several exemplary multi-channel devices, in accordance with several embodiments of the present invention. 5. Modes for Carrying out the Invention This application is based upon and claims priority under 35 U.S.C. ⁇ 119(e) from U.S. Provisional Applications No. 60/689,417 filed June 10, 2005 and No.
  • the description below includes single channel devices identified as (1) normal quantifier, reverse bias designs, (2) normal quantifier, normal bias designs, (3) lateral quantifier, normal bias designs, and (4) changeable quantifier, normal bias designs.
  • the designs describe and claimed herein may be arranged into a variety of array configurations providing an infinite number of array designs.
  • Various embodiments are shown with a light 26 impinging at least one electrode.
  • Low doping is generally understood to mean less than 10 15 cm, 3 and heavily doped or high doping means more than 10 17 cm "3 .
  • Devices described herein are manufactured via methods understood in the art. By way of background, functionality of the governor is provided by its higher impedance in comparison to the avalanche layer.
  • the high impedance is achieved by various approaches, described in USPN 6,885,827, including low doping level, a material with low mobility for carriers, or with artificially reduced mobility by special treatments.
  • the potential barriers between the governor layer and adjoining layers are also used to achieve the desired impedance.
  • the barrier height is regulated by the doping within the governor and adjoining layers. If the adjoining layer is metal, the barrier may be regulated by its work function.
  • the governor functions to govern or regulate the potential of the quantifier which then transfers this potential to electric field, thus switching the threshold amplifier to ON or OFF state and to drain accumulated charge from integrator so as to return the integrator to its initial state.
  • the high imaging part of impedance (due to the element inductance, shifting current phase relative to the voltage phase) provides the desired functionality of the governor meaning the governor has very low conductivity for a short time while the signal carrier is multiplied, thus all of the generated charge is accumulated effectively nearly without drain. On the other hand, after a short time (delay) the conductance becomes high (equal to the real part of impedance) allowing the accumulated charge to drain and quick return to the initial state.
  • the high imaging part of impedance is provided by material properties (low mobility of carriers) or the presence of potential barriers between the governor and adjoining layers. Material properties lead to a current delay relative to the applied voltage. Low mobility may be achieved by ion implantation (and other special treatments) or may be a property of the material itself.
  • the barrier prevents the accumulated charge (i.e., electrons) from the integrator to flow to the governor immediately and the second barrier at the other side of the governor for the other type of carriers (i.e., holes).
  • Single Channel Devices Normal Quantifier, Reverse Bias
  • the avalanche amplifying structure 1 is a generally planar structure including a first electrode 2, an avalanche region 3, a quantifier 4, an integrator 5, a governor 6, a substrate 7, and a second electrode 8 arranged and contacting in the order described.
  • the avalanche region 3 includes a plurality of semiconductor layers with a conductance opposite that of a heavily doped substrate 7.
  • the governor 6 is a weakly doped semiconductor material whereby the quantifier 4 is provided at the interface between the integrator 5 and avalanche region 3.
  • the integrator 5 is provided between the governor 6 and avalanche region 3.
  • FIG. IB an alternate embodiment of the reverse-bias avalanche amplifying structure 1 operating in the Geiger mode is shown including a first electrode 2, a governor 6, an integrator 5, an avalanche region 3, a quantifier 4, a substrate 7, and a second electrode 8 in the order described.
  • the avalanche region 3 includes a plurality of semiconductor layers with a conductance opposite that of a heavily doped substrate 7.
  • the quantifier 4 is provided at the interface between the substrate 7 and avalanche region 3.
  • the integrator 5 is provided at the interface between the governor 6 and avalanche region 3.
  • FIG. 1C an other alternate embodiment of a reverse-bias avalanche amplifying structure 1 operating in the Geiger mode is shown wherein a signal transport layer 27 is provided between the first electrode 2 and the avalanche region 3 shown in FIG. IA.
  • the quantifier 4 is provided at the interface between the integrator 5 and avalanche region 3.
  • a variety of materials are applicable to the avalanche region 3, quantifier 4, integrator 5, governor 6, substrate 7 and signal transport layer 27 in FIGS. lA-lC.
  • each layer may be composed of the same or different semiconductor materials, examples including Si, SiC, GaN, GaAs, and GaP, which are doped to provide the desired electrical properties.
  • the governor 6 may be composed of a material having a band gap wider than that of the other layers.
  • the signal transport layer 27 may be composed of a material having a band gap narrower than the other layers.
  • the first electrode 2 and/or second electrode 8 may be composed of a conductive metal or light transmissive and conductive material, examples including without limitation transparent ITO and Al-doped ZnO.
  • the avalanche region 3, quantifier 4, integrator 5, governor 6, and substrate 7 and signal transport layer 27 may include two or more layers arranged to form a laminated structure with or without inclusions or regions with yet other non-doped and doped semiconductor materials.
  • Layers and devices may include planar and non-planar shapes.
  • the sectional views may represent structures of planar and/or diametric extent.
  • the SiO 2 layer may be composed of other comparable materials. Referring now to FIG. 2A, a sequence of material layers are shown to correspond with one exemplary embodiment of the avalanche amplifying structure 1 shown in FIG. IA.
  • the device includes a transparent electrode 105, a p-Si layer 100, n + -Si layer 102, a i-Si layer 110, an n + -Si layer 109 and an electrode 106.
  • the electrode 106 preferably a metal, is electrically connected to a power supply having a positive voltage and the transparent electrode 105 is electrically connected to ground.
  • FIGS. 2B-2C band diagrams are provided to illustrate the function of the device in FIG 2A.
  • FIG. 2B shows the initial state of the device, before the appearance of a signal carrier, such that a positive voltage LU p is applied to the electrode 106, the n + -Si layer 109 has the potential of the electrode 106, and the heavily-doped n + -Si layer 102 is discharged and operating as a floated electrode to acquire nearly the same potential as the n + -Si layer 109.
  • nearly all of the voltage is applied to the p-Si layer 100.
  • the voltage should be sufficient so that the voltage drop in the p-Si layer 100 (U amp ) exceeds the avalanche breakdown value in the ON state.
  • the p-Si layer 100 is an avalanche threshold or Geiger mode amplifier.
  • the voltage applied to amplifier (U amp ) is equal to U sup -U r , where U r results from a small voltage drop in the i-Si layer 110. If U r is initially too high, it will decrease over time because of the field-enhanced thermoemission or discharging current associated with electrons from the n + -Si layer 102 to the n + -Si layer 109 over the potential barrier shown in FIG. 2B.
  • the i-Si layer 110 may be composed of an i-type, weakly doped p-type, or weakly doped n-type semiconductor material. Doping within the i-Si layer 110 regulates the potential barrier height between the governor and adjoining layers.
  • n + -Si layer 102 which corresponds to the integrator 5 in FIG. IA, discharges in the absence of charging current from the p-Si layer 100, until its potential is nearly equal to the potential of the electrode 106.
  • a free carrier electron
  • Avalanche electron current quickly increases in time and becomes larger than the flow-out current from the n + -Si layer 102 and electrons 62 generated within the p- Si layer 100 quickly charge the integrator 5 or n + -Si layer 102.
  • the described behavior decreases the voltage drop within the amplifier or the p-Si layer 100 and turns off the avalanche process so that the amplifier is switched to the OFF state.
  • the voltage drop on the amplifier is associated with the voltage rise in the i-Si layer 110 or governor 6, causing redistribution of the supplied voltage between amplifier and governor 6.
  • the governor 6 induces a delay in the discharge of the integrator 5, shifting current phase in time with respect to the avalanche current. This delay is sufficient to terminate the avalanche process within the amplifier. While not intending to be bound by theory, the discharge delay may have one or more physical causes dependent on the device state, as well as the design and properties of the governor 6.
  • thermoemission or discharge current is small in comparison to the avalanche or charging current to the integrator 5.
  • the dominant reason may include the self-limitation of the out-flow current by space-charge effects, the finite time of flight of free-carriers through the governor 6, the lower mobility of carriers within the governor 6 in comparison to those in the amplifier, or other physical mechanisms that limit current discharge or shift its phase in comparison to the avalanche current.
  • the minimal delay time sufficient to turn the amplifier to the OFF state is estimated to be in the range of about 10-400 picoseconds, depending on the device design and desired gain, thus representing the number of elementary charges accumulated within the integrator 5 in response to one signal carrier.
  • the result from the avalanche multiplication charge accumulated within the integrator 5 may be read out through the mutual capacitance of the heavily-doped n + - Si layer 102 and n + -Si layer 109 divided by the i-Si layer 110 (capacitive reader) or by detecting the integrator 5 discharge current through governor 6 or current reader. Both read out approaches lead to the appearance of charge in the electrode 106 corresponding to charge accumulated within the integrator 5. Referring now to FIG.
  • the functional scheme of the discrete amplifier is shown with reference to the corresponding physical representation of the device in FIG. 2A.
  • the functional scheme is shown including a transporter 9, a threshold amplifier 10, a quantifier 11, an integrator 12, a governor 13, and a reader 14.
  • the transporter 9 corresponds to a portion of the p-Si layer 100, where the electric field is not-zero. Free electrons collide within the transporter 9 and are delivered to the input of the threshold amplifier 10.
  • the threshold amplifier 10 corresponds to a portion of the p-Si layer 100, where the electric field is sufficient for impact ionization in the ON state. Voltage drop within the p- Si layer 100 exceeds the breakdown voltage, thus allowing the threshold amplifier 10 to operate in the Geiger mode.
  • the quantifier 11 corresponds to the interface between the p-Si layer 100 and the n + -Si layer 102.
  • the potential of the quantifier 11 regulates the avalanche process (electric field strength) in the threshold amplifier 10.
  • the transfer constant is equal to one.
  • transfer constants greater than one are possible based upon the curvature of the design which causes field concentrations so that the maximal field becomes higher for the same electric potential.
  • the quantifier 11 functions to transfer the integrator 12 potential to the field strength which defines the avalanche intensity.
  • the transfer constant may be defined as the reaction or increase of the field intensity with respect to the increase of the potential.
  • the integrator 12 is shown within the n + -Si layer 102 as it accumulates current from the threshold amplifier 10 and regulates the potential of the quantifier 11.
  • the governor 13 is shown within the i-Si layer 110, since it regulates the discharge current from the integrator 12 and delays discharge to turn the threshold amplifier 10 to the OFF state, as well as returning the device to its initial state after amplification of a charge carrier.
  • the reader 14, a capacitive variant, has a capacity comprised by the n + -Si layer 102, the i- Si layer 110, and the n + -Si layer 109.
  • FIGS. 2B-2C further show the p-Si layer 100 with an un-depleted region close to the first electrode 105.
  • a typical p-Si layer 100 is 5-6 ⁇ m wide having a resistivity of 4 Ohm-cm.
  • the width of the p-Si layer 100 may less than the depleted region width so that the electric field reaches the interface between the p-Si layer 100 and the first electrode 105, thus allowing photo- carriers generated by light close to the interface to be gathered effectively.
  • the electrode 105 may have a Shottky barrier for electrons or a p + region placed between the electrode 105 and the p-Si layer 100. It is readily apparent from the description above that the present invention operates as a Geiger counter, using a new internal scheme of quenching integrated within the device which differs from both active and passive quenching known within the art. Active quenching requires external or integrated active electronics which is not provided by the functionality described above. Passive quenching requires a resistor or a resistive layer which is not provided by the functionality described above. FIGS.
  • the device includes a transparent electrode 105, a segmented SiO 2 layer 107 (insulator), p + -Si regions 103 (heavily doped region), a p-Si region 112, a p-Si layer 100, a p " -Si layer 110, a n + -Si layer 102, a n + -Si layer 109, and an electrode 106.
  • the thickness of the p-Si layer 100 should be sufficiently small so that it is fully depleted to increase shortwave sensitivity.
  • Preferred embodiments of the p-Si layer 100 include a doping of 2-3 Ohm-cm and a thickness of 2.5-3 ⁇ m.
  • the spectral range for such a device is from 300-400 nm (shortest wavelength depending on the electrode 105 material) and up to 700-800 nm. For longer wavelength spectral sensitivity up to 1060 nm, the width of the p-Si layer 100 is increased and the doping level decreased.
  • One or more p + -Si regions 103 are included to block the injection of electrons from the transparent electrode 105 to the depleted p-Si layer 100.
  • the p + -Si regions 103 may be not necessary if the p-Si layer 100 is not fully depleted and the field does not reach the transparent electrode 105; however, generally, this would provide very low spectral sensitivity for short wavelengths that generate photo-carriers close to the top surface of the p-Si layer 100. If this area is not depleted, photocarriers will recombine and be lost. The resultant device is operable, but not optimal. However, where the field reaches the transparent electrode 105 (a more optimal variant), then p + -Si regions 103 are required to block the injection of electrons.
  • the p-Si layer 100 is 2-4 ⁇ m thick with a resistivity of 10 Ohm-cm.
  • the p-Si region 112 is preferred to be composed of the same material, have the same active impurity doping, and have lower mobility for holes in the lateral direction along the Si-SiO 2 interface of the p-Si layer 100.
  • the p-Si region 112 is formed by neutral impurities doping, irradiation, or p with n doping.
  • FIG. 4 the functional scheme for the embodiment in FIG. 3 is shown. Unlike the device in FIG. 2A, the FIG. 3 device includes two integrators 12, 16 and two governors 13, 17, thus delaying the discharge of corresponding integrators 12, 16 to function as an electron governor, as described for the i-Si layer 110 in FIG.
  • the resultant delay time depends on mobility of the holes moving along the interface in the p-Si region 112.
  • the transporter 9, threshold amplifier 10, and quantifier 11 regulate the avalanche process, transferring the electron integrator 12 potential to the threshold amplifier 10 at the interface between the n + -Si region 102 and p-Si layer 100.
  • the quantifier 17 regulates the avalanche process, transferring the hole integrator potential to the threshold amplifier 10 at the interface between the Si and SiO 2 layer 107 above the n + Si region 102 and the electron integrator 12 is placed in the n + Si region 102.
  • the hole integrator 16 is placed at the interface between the p- Si region 112 and SiO 2 layer 107 above the n + -Si region 102.
  • the electron governor 13 delays the discharge of the electron integrator 12 following the removal of the accumulated electron charge.
  • the hole governor 17 delays the discharge of the hole integrator 17 following the removal of the accumulated hole charge, which corresponds to the p-Si region 112, electron reader 14 and hole reader 18.
  • the functional scheme in FIG. 2D changes to the functional scheme in FIG. 4 when the electric field reaches the p-Si region 112 and when the p-Si layer 100 and p- Si region 112 are fully depleted.
  • FIG. 5 an alternate embodiment of the device in FIG.
  • the second governor is composed of a high-impedance semiconductor material between the first or transparent electrode 105 and the p + -Si regions 103 (heavily doped regions) and residing with the opening or cavity within the SiO 2 layer 107.
  • a second integrator is formed at the interface between the avalanche region and said second governor.
  • the buried channel 114 is a thin layer, preferably 0.3 ⁇ m, with n-doping and fabricated via methods known within the art.
  • the buried channel 114 improves the mobility of holes along interface of the channel.
  • the doping concentration within the buried channel should be sufficient so that it is fully depleted by field in the p-Si layer 100.
  • the buried channel 114 ensures that all the holes generated by the avalanche in the p-Si layer 100 quickly move along layer and are accumulated within P + -Si region 103 or hole integrator. The result is a charging of the p + -Si region 103 which increasing its potential with respect to the transparent electrode 105.
  • the p + -Si region 103 and i-Si region 113 operate in the same manner.
  • the result is a voltage drop within the i-Si region 113 and a delay in discharging and switching of the threshold amplifier to the OFF state.
  • the hole quantifier in this device is the interface between the buried channel 114 and the p-Si layer 100. Charging of the p + -Si region 103 causes a charge to the holes accumulating in buried channel 114 and a uniform increase of the potential within the buried channel 114, so that the buried channel 114 is included in the capacitance of the hole integrator.
  • FIGS. 6A-6B Alternate embodiments to the device in FIG. 5 are shown in FIGS. 6A-6B. For example in FIG. 6 A, the i-Si region 113 is eliminated from FIG. 5. Whereas in FIG.
  • each layer may be composed of the same or different semiconductor materials, examples including Si, SiC, GaN, GaAs and GaP, which are doped to provide the desired electrical properties.
  • the governor 6 may be composed of a material having a band gap wider than that of the other layers.
  • the signal transport layer 27 may be composed of a material having a band gap narrower than the other layers.
  • the first electrode 2 and/or second electrode 8 may be composed of a conductive metal or light transmissive and conductive material, examples including without limitation transparent ITO and Al-doped ZnO.
  • layers and regions may include two or more layers arranged to form a laminated structure with or without inclusions or regions with yet other non-doped and doped semiconductor materials.
  • Layers and devices may include planar and non-planar shapes.
  • the sectional views may represent structures of planar and/or diametric extent.
  • the SiO 2 layer may be composed of other comparable materials. Referring now to FIG. 7 A, a single channel element is shown for one embodiment of the avalanche amplifying structure 1 operating in the Geiger mode with a normal direction of avalanche.
  • the avalanche amplifying structure 1 is a generally planar structure including a first electrode 2, a governor 6 for draining the charge from the integrator 5 and controlling the quantifier 4, an integrator 5 which accumulates a signal charge, a quantifier 4 for turning the avalanche process ON and OFF, an avalanche region 3, a substrate 7, and a second electrode 8 arranged in the order described.
  • the quantifier 4 is formed at the interface between the integrator 5 and avalanche region 3.
  • the integrator 5 may have limited conductance in directions parallel to the plane of the substrate 7. In some embodiments, all layers may be composed of the same material. In other embodiments, it is preferred for the governor layer to be made of a semiconductor material which has a band gap which is wider than that of the remaining semiconductor layers.
  • FIG. 7B another alternate embodiment of the single channel element is shown for the avalanche amplifying structure 1 operating in the Geiger mode with a normal direction of avalanche including a signal transport layer 27 disposed between and contacting the avalanche region 3 and substrate 7 in FIG. 7A.
  • the signal transport layer 27 generates free charge carriers under the signal action and effects their transportation into the avalanche region 3.
  • FIG. 7C an alternate embodiment of the single channel element is shown for the avalanche amplifying structure 1 operating in the Geiger mode with a normal direction of avalanche including a first electrode 2, a governor 6, an avalanche region 3, a substrate 7, and a second electrode 8 arranged in the order described.
  • the avalanche region 3 and governor 6 drain the charge from the integrator 5 and control the quantifier 4.
  • the function of the integrator 5, which accumulates the signal charge, and the function of the quantifier 4, which turns the avalanche process ON and OFF, is performed at the interface between the avalanche region 3 and the governor 6.
  • the interface between the avalanche region 3 and the governor 6 may have limited conductance in directions parallel to the plane of the substrate 7.
  • the amplifying avalanche structure 1 operating in the Geiger mode with a normal direction of avalanche to include an avalanche region 3, an integrator 5 for the accumulation of a signal charge, a quantifier 4 for turning the avalanche process ON and OFF, and a governor 6 for draining the charge from the integrator 5 and controlling the quantifier 4 collectively composing a planar laminated semiconductor structure disposed on a heavily doped substrate 7 between a pair of electrodes 2, 8.
  • the avalanche region 3 may be composed of a material of the same conductivity but higher resistivity, an integrator 5 composed of a heavily doped semiconductor material having a conductivity opposite that of the substrate 7, a governor 6 composed of a high-impedance semiconductor material, and quantifier 4 provided at the interface between the avalanche region 3 and integrator 5.
  • FIG. 8 A a sequence of material layers are shown including an electrode 106, a p-Si layer 100, a n + -Si region 102, an i-Si layer 110 and a transparent electrode 105.
  • FIGS. 8B-8C show band diagrams describing the function aspects corresponding to the device layers in FIG. 8A Referring now to FIGS.
  • the device includes a silicon substrate with orientation [100] and resistivity of 10-100 Ohm-cm, thus having a wide depleted region.
  • the n + -Si region 102 is heavily doped and has a width less than 0.5 ⁇ m.
  • the i- Si layer 110 has a width which is less than several ⁇ m's. The device is intended for red-infrared wavelengths, when it is possible to neglect light absorption in the n + -Si region 102 and the i-Si layer 110.
  • Alternate embodiments of the present invention may include an i-Si layer 110 composed of a semiconductor having band gap wider than silicon, one example being non-doped ZnO, to decrease the light absorption within the layer and to increase short wavelength sensitivity (green-blue).
  • Such embodiments have an epitaxial p-Si layer 100 with a resistivity of 1-10 Ohm-cm. Operation is nearly identical to a similar reverse bias design, as illustrated by the band diagrams for the ON and OFF states in FIGS. 8B-8C. The main difference being that electron and hole current may take part when discharging the n + -Si layer 102 (integrator) through the i-Si layer 110 (governor).
  • FIG. 9-12 and 14 refer to specific embodiments of the illustrative devices.
  • a cross-sectional view of a normal-direction avalanche amplifying structure 1 with ring guard region is shown and described including a transparent electrode 105, a SiO 2 layer 107, a i-Si layer 110, a n + -Si guard ring 108, a n + -Si layer 102, an epitaxial p-Si layer 100, a p + -Si layer 90 (substrate), and an electrode 106.
  • the i-Si layer 110 (governor) is dimensionally smaller than the device, preferably several ⁇ m's in diameter, to minimize light absorption.
  • the i-Si layer 110 may be composed of a semiconductor having a band gap wider than silicon, one example being non-doped ZnO.
  • a signal light 26 enters the epitaxial p-Si layer 100 (avalanche region) through the n + -Si layer 102 (integrator).
  • the n + -Si layer 102 is thin, typically less than 0.4 ⁇ m, to minimize light absorption within the layer.
  • the n + -Si guard ring 108 suppresses edge effects and ensures the avalanche process is uniform over the area underlying the n + -Si layer 102 (integrator).
  • the epitaxial p-Si layer 100 has a resistivity of 1-2 Ohm-cm and a width of a few ⁇ m's to minimize thermogeneration current within the depleted region. In red-infrared embodiments, the epitaxial p-Si layer 100 has a higher width of tens of ⁇ m's and higher resistivity. The precise values of the width and resistivity for the epitaxial p-Si layer 100 are calculated via methods understood in the art to achieve the desired spectral sensitivity and other parameters of the device. Operation of the described device and its functional elements (integrator, quantifier, governor, substrate, and avalanche region) are as described above. Referring now to FIG.
  • a normal-direction avalanche amplifying structure 1 with high-field implant including a transparent electrode 105, a SiO 2 layer 107, an i-Si layer 110, a n + -Si region 102, a p-implantation layer 101, an epitaxial p-Si layer 100, a p + -Si layer 90 (substrate), and an electrode 106.
  • the high field implant is used to suppress edge effects in place of the diffused guard ring in FIG. 9. This approach minimizes the unused area of the device where avalanche is not present.
  • the p-implantation layer 101 is a thin region beyond the n + -Si region 102.
  • the i-Si layer 110 is a few ⁇ m's in diameter to minimize light absorption within the layer.
  • the i-Si layer 110 may be composed of a semiconductor having a band gap wider than silicon, one example being non-doped ZnO.
  • Infrared embodiments of the device may operate with backside illumination (rich-through) where the field tail penetrates the low-doped epitaxial p-Si layer 100 so as to effectively gather photocarriers with high time resolution, while having a low operating voltage.
  • the i-Si layer 110 (governor) has a small diameter, as described above for FIG. 9. Referring now to FIG.
  • a normal-direction avalanche amplifying structure with backside illumination is shown and described including an electrode 106, a SiO 2 layer 107, an i-Si layer 110, a n + -Si layer 102, a n " -Si guard ring 108, an epitaxial p-Si layer 100, a p " -Si layer 104, a p + -Si layer 103, and a transparent electrode 105. Operation of the device is as described above in FIG. 9, except that the transporter-photoconverter is provided within the p " -Si layer 104.
  • the i-Si layer 110 is a few ⁇ m's in diameter to minimize light absorption within the layer.
  • the i-Si layer 110 may be composed of a semiconductor having a band gap wider than silicon, one example being non-doped ZnO.
  • the p ' -Si layer 104 (substrate) has a high resistivity (low doped) and is fully depleted at the operating voltage.
  • the described device is capable of detecting infrared light with a wavelength up to 1.06 ⁇ m.
  • the avalanche event occurs within the p-Si layer 100 which has a higher doping in comparison to the transport-photoconversion region comprised by the p " -Si layer 104.
  • the width and doping of the p-Si layer 100 is selected so that the electric field does not fall to zero, but has a long tail which penetrates into the p " -Si layer 104 stopped by the highly doped p + -Si layer 103.
  • the width of the p " -Si layer 104 should be sufficient to provide structural strength to the device, preferably up to a few hundred ⁇ m's. Field strength in the p " -Si layer 104 should be insufficient for avalanche, but high enough so that a free carrier may move within it at a saturated speed (104 V/cm), as calculated via methods understood in the art.
  • the p + -Si layer 103 should be as thin as possible to minimize light absorption within the layer.
  • the p + -Si layer 103 should not be fully depleted and its width should be sufficient to block electron injections from the transparent electrode 105 to the p " -Si layer 104.
  • Various antireflection coating understood in the art may be added to the device via methods also understood in the art. Referring now to FIG.
  • a normal-direction avalanche amplifying structure 1 with high field implant and hole integrator including a transparent electrode 105, a SiO 2 layer 107, a n + Si layer 102, a p-Si layer 101, an epitaxial p " -Si layer 100, a p + -Si region 130, an epitaxial i-Si layer 113, a p + -Si layer 90 (substrate), and an electrode 106.
  • the device differs from FIG. 10 in that a hole integrator is provided by the p + -Si layer 130 and the epitaxial i-Si layer 113 is added as the hole governor, instead of the electron integrator.
  • FIG. 13 the functional components of the normal-direction avalanche amplifying structure 1 from FIG. 12 are shown and described.
  • the transporter 9 corresponds to the depleted part of the epitaxial p ' -Si layer 100
  • threshold amplifier 10 corresponds to the p-Si layer 101
  • electron quantifier 11 corresponds to the interface between the n + -Si layer 102 and the p-Si layer 101
  • electron reader 14 corresponds to the transparent electrode 105
  • hole quantifier 15 corresponds to the interface between the p " -Si layer 100 and the p + -Si layer 130
  • hole integrator 16 corresponds to the p + -Si layer 130
  • hole governor 17 corresponds to the epitaxial i-Si layer 113
  • hole reader 18 corresponds to the electrode 106 through capacitance comprised by the p + -Si region 130, the epitaxial i-Si layer 113, and the p + - Si layer 90 (HF part of the signal), and current though the epitaxial i-Si layer 113 to the electrode 106 (LF part of the signal).
  • the device switches the avalanche amplifier OFF following the removal of the accumulated charge in the integrator.
  • the width and doping level of the epitaxial p " -Si layer 100 are designed so that the layer is fully depleted.
  • the epitaxial i-Si layer 113 may be composed of a p-type or n-type material that regulates the barrier height for holes.
  • the size, form of the p + -Si layer 130, and distance of the p + -Si layer 130 from the n + -Si layer 102 are regulating parameters which influence timing, jitter, maximal overvoltage, gain at fixed over- voltage, and other performance characteristics.
  • the advantages of this embodiment are that there are no additional layers ahead of the avalanche region, unlike the conventional design of any avalanche Geiger photodetector or non-Geiger APD, and no additional light absorption.
  • the quenching system is placed behind the working region allowing its use with Geiger photodetectors. The result is the ability to operate with DC voltage and a quenching system which is much more efficient than conventional passive and active quenching methods. Referring now to FIG.
  • a normal-direction avalanche amplifying structure 1 with ring guard and hole integrator including a transparent electrode 105, a SiO 2 layer 107, a n + -Si layer 102, a n " -Si guard ring 108, an epitaxial ⁇ " -Si layer 100, a p + -Si region 130, an epitaxial i-Si layer 113, a p + -Si layer 90 (substrate), and an electrode 106.
  • the device differs from FIG. 12 in that the high field implant design is substituted with a guard ring design.
  • Single Channel Devices - Lateral Quantifier, Normal Bias A variety of materials are applicable to layers and regions in FIGS.
  • each layer may be composed of the same or different semiconductor materials, examples including Si, SiC, GaN, GaAs and GaP, which are doped to provide the desired electrical properties.
  • the governor 6 may be composed of a material having a band gap wider than that of the other layers.
  • the signal transport layer 27 may be composed of a material having a band gap narrower than the other layers.
  • the first electrode 2 and/or second electrode 8 may be composed of a conductive metal or light transmissive and conductive material, examples including without limitation transparent ITO and Al-doped ZnO.
  • layers and regions may include two or more layers arranged to form a laminated structure with or without inclusions or regions of yet other non-doped and doped semiconductor materials.
  • Layers and devices may include planar and non-planar shapes.
  • the sectional views may represent structures of planar and/or diametric extent.
  • the SiO 2 layer may be composed of other comparable materials. Referring now to FIG. 15A, an avalanche amplifying structure 1 operating in the Geiger mode with a lateral direction of avalanche is shown and described including a first electrode 2, a governor 6, an integrator 5 and an avalanche region 3, a substrate 7, and a second electrode 8 in a layered arranged in the order described.
  • the avalanche region 3, substrate 7, and second electrode 8 are of comparable lateral extent.
  • the first electrode 2 and governor 6 are slightly smaller in extent as compared to the integrator 5.
  • the avalanche region 3 includes a hole through its thickness within which resides the integrator 5.
  • the hole and integrator 5 should be sufficiently larger than the governor 6 to avoid contact direct contact between the governor 6 and the avalanche region 3.
  • the periphery of the integrator 5 should directly contact the avalanche region 3 so that the interface between the two materials functions as a ring-shaped quantifier 4.
  • the integrator 5 is responsible for accumulating a signal charge.
  • the quantifier 4 controls the ON and OFF states of the avalanche process.
  • FIGS. 15B-150 represent variations of the device in FIG. 15 A.
  • a dielectric layer 19 composed of one or more materials understood in the art surrounds the periphery of the governor 6.
  • the dielectric layer 19 is preferred to both cover and contact the integrator 5 and avalanche region 3 without providing an electrical conduit between the governor 6 and avalanche region 3.
  • the second electrode 8 is removed from the substrate 7 and replaced with a ring-shaped structure. The second electrode now contacts the avalanche region 3 and is disposed about the governor 6 and electrode 2 which extend above the surface including the integrator 5 and avalanche region 3.
  • FIG. 15D the first electrode 2 in FIG.
  • the governor 6 extends above the dielectric layer 19 and has a T- shaped structure so as to cover the uppermost surface of the dielectric layer 19.
  • the first electrode 2 contacts the T-shaped governor 6 about the integrator 5.
  • the first electrode 2 in FIG. 15E is now extended to contact and cover the T-shaped governor 6 so as to have lateral extents as large as the second electrode 8.
  • the substrate 7 and second electrode 8 are extended laterally beyond the edge of the avalanche region 3.
  • a signal transport layer 27 is disposed about and contacts the periphery of the avalanche region 3. It is preferred for the signal transport layer 27 to be as thick as the avalanche region 3.
  • the signal transport layer 27 is composed of a semiconductor material also comprising the avalanche region 3; however, a less doped composition.
  • an electrically conductive contact region 25 is disposed between the governor 6 and integrator 5.
  • the contact region 25 is of lesser lateral extent as compared to the integrator 5 so as to avoid direct electrical contact with the governor 6.
  • a blocking layer 24 is disposed about and contacts the periphery of the contact region 25.
  • the blocking layer 24 covers the integrator 5 and avalanche region 3.
  • the blocking layer 24 is composed of a semiconductor material of the same type as the avalanche region 3.
  • the blocking region 24 does not contact the first electrode 2.
  • a dielectric layer 19 is disposed about and contacts the periphery of the governor 6 in FIG.
  • the dielectric layer 19 also completely contacts and covers the blocking layer 24 opposite of the avalanche region 3.
  • the first electrode 2 contacts the governor 6 only.
  • FIG. 15 J the first electrode 2 in FIG. 151 is extended laterally to now contact and cover both governor 6 and blocking layer 24.
  • a third electrode 50 replaces a segment of the first electrode 2 from FIG. 15D with a gap there between.
  • the first electrode 2 contacts the governor 6.
  • the third electrode 50 contacts the dielectric layer 19.
  • FIG. 15L a third electrode 50 replaces a segmented of the first electrode 2 from FIG. 15J with a gap there between.
  • the first electrode 2 contacts the governor 6.
  • the third electrode 50 contacts the dielectric layer 19.
  • the integrator 5 includes a hole within which the governor 6 resides so as to contact the integrator 5 about the periphery of the governor 6.
  • the governor 6 now resides on the substrate 7.
  • the first electrode 2 contacts the governor 6 only.
  • a dielectric layer 19 is disposed about and contacts the periphery of the governor 6 from FIG. 15M which extends beyond the integrator 5.
  • the first electrode 2 is extended laterally to now contact and cover the governor 6 and the dielectric layer 19.
  • FIG. 150 the first electrode 2 only covers and contacts the governor 6 in FIG. 15N.
  • FIGS. 16 and 18-27 refer to specific embodiments of the illustrative devices. Referring now to FIG.
  • a lateral-direction avalanche amplifying structure 1 is shown and described including a transparent electrode 105, a p ⁇ -Si layer 110, an SiO 2 layer 107, a p " -Si layer 100, a n + -Si region 102, a p-Si region 103, a p + -Si layer 91 (substrate), and an electrode 106.
  • FIG. 17 shows the functional components of the lateral-direction avalanche amplifying structure 1.
  • the components identified in FIG. 16, excluding electrodes 105, 106, may be composed of one or more semiconductor material, one example being Si having a doping type and concentration to achieve the desired electrical properties.
  • the SiO 2 layer 107 may be composed of other comparable materials.
  • the transparent electrode 105 and p " -Si layer 110 are preferred to be several ⁇ m's in diameter to minimize light absorption therein.
  • the transparent electrode 105 and p " -Si layer 110 may be composed of a semiconductor having a wider band gap than silicon, one example being non-doped ZnO.
  • the n + -Si region 102 (integrator) is fabricated to have a diameter as small as possible.
  • the electrode 106 may be composed of a metal, examples including Al, Ni, NiCr, Mo or the like, or a transparent conductive material, examples including ITO or Al-doped ZnO. ON and OFF switching of this embodiment is nearly the same as the device in FIGS.
  • the threshold amplifier 10 has a lateral orientation and the threshold amplifier 10, quantifier 11, integrator 12, and governor 13 are not arranged in a linear fashion.
  • the p-Si region 103 is preferred to have a higher doping concentration than the p " -Si layer 100.
  • Avalanche multiplication occurs only at the edges of the junction in the p-Si region 103 and both transporters 9 and threshold amplifiers 10 in FIG. 16B are oriented in the lateral direction, parallel to the p + -Si layer 91. Accordingly the carriers generated at the top of p " -Si layer 100 are effectively gathered by the threshold amplifiers 10.
  • the other elements within the functional scheme operate as previously described.
  • the p-Si region 103 is preferred to have a width, typically l ⁇ m, and doping level, typically 1 Ohm-cm resistivity, so that the lateral field component exits the region (rich-through in lateral direction) and penetrates the p " -Si layer 100 along Si- SiO 2 interface, thus gathering signal carriers and transporting them to the p-Si region 103 (threshold amplifier).
  • the p-Si region 103 may be composed of the same doping as in the p " -Si layer 100; however, the n + -Si region 102 (integrator) is preferred to be thin, typically less than 0.4 ⁇ m.
  • the lateral direction of avalanche is provided by the edge breakdown effect.
  • the p-Si region 103 may be used without rich-though and have a diameter equal to the device diameter so that it fully separates the SiO 2 layer 107 from the p " -Si layerlOO.
  • the lateral-direction devices described herein provide high sensitivity for short wavelength applications down to near UV and high gathering efficiency for longer wavelength applications up to 700-800 nm.
  • the geometrical factor for such devices representing the amplified photocarriers divided by the total number of generated photo-carriers, is rather close to unity.
  • a lateral-direction avalanche amplifying structure 1 including a pair of transparent electrodes 105, a Si 3 N 4 layer 93 (insulator), an n " InP layer 110, a p + InP region 102, a n InP layer 100, a n InGaAsP layer 140 (buffer), a n InGaAs layer 150 (absorber), a n InP layer 160 (epitaxial), and a n + InP layer 90 (substrate, orientation [100]).
  • Layers have a doping type and a polarity opposite of the embodiment above.
  • the application of LiGaAsP does not affect the overall functional scheme (governor-integrator-quantifier-amplifier) of the device.
  • the desired wavelength is defined by the absorption layer band gap and width, which has a range of 1.06-1.6 ⁇ m.
  • the wide-band material from which the amplifier and substrate are composed (InP) is transparent for this wavelength.
  • the separation of the amplifier from the absorber allows for increased quantum efficiency, since neither the amplifier nor the substrate enclose the absorber from light.
  • the insulator or Si 3 N 4 layer 93 replaces the SiO 2 layer 107 described above because it provides a better performance match with the InGaAs- InP layers.
  • the additional buffer layer between absorber and n InP layer 100 improves their heterobarrier properties, specifically their frequency response.
  • Transparent electrodes 105 may be composed of ITO or Al-doped ZnO.
  • the device may be illuminated from any side and antireflection coatings added via methods understood in the art.
  • the p + InP region 102 operates as an integrator such that its interface with the neighboring n InP layer 100 functions as the quantifier.
  • the n- InP layer 110 is the governor responsible for the delay in the integrator discharge (sufficient to turn OFF the threshold amplifier) and for returning the threshold amplifier to the initial stage by removing the accumulated charge from it.
  • the avalanche region or threshold amplifier corresponds to the n InP layer 100.
  • n InP layer 100, n InGaAsP layer 104, and n InGaAs layer 150 are fabricated via methods understood in the art.
  • the field strength is sufficient for avalanche multiplication within the n InP layer 100 and to cause a field tail which is sufficiently low within the absorber to prevent tunneling and avalanche current.
  • the field tail gathers the generated photoca ⁇ iers from the absorber to amplifier, thus allowing the absorber to be fully depleted.
  • the absorber width is sufficient for effective light absorption at the desired wavelength.
  • the absorber may be made with no field penetration from the n InP layer 100, but with varying band gap that allows photocarriers to reach the depleted n InP layer 100 while avoiding tunneling current in the absorber.
  • FIG. 19 a lateral-direction avalanche amplifying structure 1 with transparent electrode 150 and electrode 106 aligned along one side the device is shown and described.
  • the device is an alternate embodiment of the device in FIG. 16, wherein now a ring electrode 106 passes through the SiO 2 layer 107 and is attached to a p + -Si region 104 embedded within the p " -Si layer 100. Furthermore, the electrode 106 in FIG. 16 is replaced with a SiO 2 layer 107, as shown in FIG. 19.
  • the electrodes 106 may be composed of a metal or transparent conductive material.
  • the p + -Si region 104 blocks injection of electrons from the electrode 106 into the p " -Si layer 100.
  • the doping depth for the P + -Si region 104 is small, typically 0.3 ⁇ m.
  • the width of the p + -Si region 104 is minimized and preferred to extend slightly beyond the edge of the electrode 106.
  • the distance between the n + -Si region 102 and p + -Si region 104 should be sufficient so that the lateral component of the field from the p-Si region 103 is small and does not cause tunnel currents within the p + -Si region 104. Functionality of this device is as described above for FIG. 16.
  • the device is an alternate embodiment of the device in FIG. 16, wherein a ring-shaped electrode 117 is disposed about the transparent electrode 105 and contacting the SiO 2 layer 107.
  • Electrode 117 is composed of a transparent conductive material examples of which are provided above. The electrode 117 allows additional tuning of the device characteristics, including but not limited to spectral sensitivity, response time for different wavelengths, and compensates the fixed charge in the protective oxide. A DC voltage is applied to the electrode 117 in a manner that allows optimization of the device.
  • the protective SiO 2 layer 107 should be sufficiently thick, typically 0.7 ⁇ m, to prevent the avalanche process within the p or p " layer 100 and the p-Si layer 103 caused by the vertical component of the electric field from electrode 117. Functionality of this device is as described above for FIG. 16. Referring now to FIG. 21, a lateral-direction avalanche amplifying structure 1 with a single electrode aligned along one side of the device is shown and described.
  • the device is an alternate embodiment of the device in FIG. 16, wherein the transparent electrode 105 completely covers the top surface of the SiO 2 layer 107.
  • the primary advantage of this embodiment is that more volume of the p " -Si layer 100 is depleted improving the collection of photoca ⁇ iers and response time of the device.
  • the protective SiO 2 layer 107 should be sufficiently thick, typically 0.7 ⁇ m, to prevent the avalanche process within the p or p " -Si layer 100 and the p-Si layer 103 caused by the vertical component of the electric field from electrodes 105. Functionality of this device is as described above for FIG. 16, Referring now to FIG. 22, a lateral-direction avalanche amplifying structure 1 with blocking layer is shown and described.
  • the device is an alternate embodiment of the device in FIG. 16, wherein the blocking layer is a n-Si layer 120 disposed between the SiO 2 layer 107 and the p or p " -Si layer 100.
  • the n-Si layer 120 is preferred to be thin, typically 0.3 ⁇ m, with doping type opposite to that of p or p " -Si layer 100.
  • the p or p " -Si layer 100 forms a buried channel under the Si-SiO 2 interface to improve the transport of photocarriers along the interface.
  • the blocking layer is fabricated via methods understood in the art. An advantage of this device includes improved stability because the avalanche process is moved away from interface and injection of hot carriers into SiO 2 is thereby suppressed.
  • FIG. 23 shows an alternate embodiment to this design wherein the transparent electrode 105 completely covers the p " -Si layer 110 and SiO 2 layer 107. FTG.
  • FIG. 24 shows an alternate embodiment to this design wherein the transparent electrode 105 separately contacts the p " Si layer 110 and a third electrode 117 separately contacts SiO 2 layer 107. Functionality of these devices is as described above for FIG. 16.
  • FIG. 25 a lateral-direction avalanche amplifying structure 1 with a hole integrator and a single electrode along one side of the device is shown and described.
  • the device differs from the device in FIG. 21 in that the transparent electrode 105 now fills the volume occupied by the p--Si layer 110 and an i-Si layer 113 is provided between the p or p " Si layer 100 and the p + -Si layer 91 (substrate).
  • the p-Si layer 103 is wider than previous embodiments.
  • FIG. 26 a lateral-direction avalanche amplifying structure 1 with a blocking layer, hole integrator, and two electrodes along one side of the device is shown and describe.
  • the device differs from the device in FIG. 24, wherein the transparent electrode 105 now fills the volume once occupied by the p " -Si layer 110 (electron integrator), the p-Si layer 103 is -wider, and a i-Si layer 113 (hole governor) and p + -Si layer 130 are disposed between the p-Si layer 100 and the p + -Si layer 91.
  • FIG. 27 eliminates the electrode 117 and n-Si layer 120 shown in FIG. 26.
  • each layer may be composed of the same or different semiconductor materials, examples including Si, SiC, GaN, GaAs and GaP, which are doped to provide the desired electrical properties.
  • the governor 6 may be composed of a material having a band gap wider than that of the other layers.
  • the signal transport layer 27 may be composed of a material having a band gap narrower than the other layers.
  • the first electrode 2 and/or second electrode 8 may be composed of a conductive metal or light transmissive and conductive material, examples including without limitation transparent ITO and Al-doped ZnO.
  • layers and regions may include two or more layers arranged to form a laminated structure with or without inclusions or regions of yet other non-doped and doped semiconductor materials.
  • Layers and devices may include planar and non-planar shapes.
  • the sectional views may represent structures of planar and/or diametric extent.
  • the Si ⁇ 2 layer may be composed of other comparable materials. Referring now to FIG. 28 A, an avalanche amplifying structure 1 with a normal direction of avalanche, MES-based with drain, and two electrodes is shown and described including a third electrode 50 contacting a dielectric layer 19, a first electrode 2 contacting a governor 6, an avalanche region 3, a substrate contacting both avalanche region 3 and governor 6, and an second electrode 8 contacting the substrate 7.
  • the dielectric layer 19 contacts both avalanche region 3 and governor 6.
  • the avalanche region 3 contacts the side periphery of the governor 6.
  • the quantifier 4 and integrator 5 are provided at the interface between the dielectric layer 19 and avalanche region 3 when an electric potential is applied between the first and second electrodes 2, 8 and the Geiger (over breakdown) avalanche mode is created in the avalanche region 3, and the third electrode 50 with an applied voltage at which the charge stored on the integrator 5 drains through the governor 6 to the first electrode 2.
  • FIG. 28B shows the device from FIG. 28A wherein the integrator 5 is provided at the interface between the dielectric layer 19 and the avalanche region 3 and the quantifier 4 is provided between the avalanche region 3 and the substrate 7.
  • the device includes a transparent electrode 105, an electrode 117, a SiO 2 layer 107, an i-Si layer 110, a p-Si layer 100, a p ' Si layer 104 (epitaxial), a p + Si layer 120 (substrate), and an electrode 106. While the present device operates in the Geiger mode, it differs from the previous examples described above.
  • the p-Si layer 100 along with the SiO 2 layer 107 and the electrode 105 operate as a MIS structure which is fully depleted because the minority carriers drain current from p-Si layer 100 along the Si- SiO 2 interface to the i-Si layer 110 and then to electrode 117.
  • Voltage to the electrode 105 should be sufficiently high to provide a Geiger mode avalanche in the p-Si layer 100.
  • Voltage applied to electrode 117 should be sufficient to drain current from p-Si layer 100 to the i-Si layer 110, but smaller than is necessary for avalanche breakdown in the i-Si layer 110.
  • Avalanche within the p ' -Si layer 104 is absent, even though it has a higher potential than p-Si layer 100, due to its lower doping.
  • Contact between the electrode 117 and i-Si layer 110 is preferred to be non-injecting, thus including a Shottky barrier to block injection of electrons.
  • a thin n + layer may be provided along the top of i-Si layer 110 to block electron injection.
  • the transparent electrode 105 may be composed of ITO or ZNO with a high conductivity.
  • the electrodes 106 and 107 may be composed of a metal or transparent conductive material.
  • FIG. 30A shows a sequence of material layers corresponding to the structure of FIG. 29 and FIGS. 30B-30C depict energy band diagrams corresponding to the material layer structure shown in FIG. 30A during various operational conditions of the amplifier.
  • FIG. 30D graphically depicts the functional components of the avalanche amplifying structure shown in FIG. 29.
  • the electric field strength within the p-Si layer 100 is sufficient for impact ionization when a positive voltage is applied to transparent electrode 105.
  • the normal operating voltage should exceed the breakdown voltage, thus initiating the Geiger mode.
  • avalanche multiplication occurs near the Si-SiC> 2 interface within the p-Si layer 100, as shown in Fig. 28C by the free carriers or electrons 62.
  • the process is self-sustaining due to the avalanche multiplication, wherein the current filament with current density grows exponentially in time.
  • Filament electrons are accumulated at the Si-SiO 2 interface. The mobility of these electrons is not high so they are accumulated locally, thus screening the electric field within the filament area and terminating the avalanche process.
  • the Si-SiO 2 interface operates as a HF integrator with a time constant, defined by the mobility of electrons spreading along the interface.
  • the initial electrons 62 result in a calibrated charge package or FIRST package, as shown in FIG. 3OD.
  • the appearance of this package at the interface results from the oxide capacitance and corresponds to the charge package at the electrode 105 (FJF reader), where it may be detected.
  • the resultant charge flow along the interface to the LF integrator and the region where the current filament occurred is restored to the initial state.
  • the interface lead also the HF governor, removes charge from the HF integrator with a delay sufficient to turn the threshold amplifier OFF.
  • the Si-Si ⁇ 2 interface functions as the quantifier as it is defined by the field within the p-Si layer 100. Each current filament occupies a rather small area, typically less than several square ⁇ m's.
  • the device operates as a multi-channel photon counter if the p-Si layer 100 is large enough in comparison to the charge spots resulting from the filaments.
  • FIG. 31 the amplifying structure 1 with a normal direction of avalanche, MIS-based with drain, and electrodes is shown and described.
  • a n + -Si layer 120 is provided immediately between the i-Si layer 110 and the p ' -Si layer 104, as compared to FIG. 29.
  • the p-Si layer 100 with an exemplary resistivity of 1 Ohm-cm, and SiO 2 layer 107 operate as a MIS structure which is fully depleted because the minority carriers drain current from the p-Si layer 100 along the Si-SiO 2 interface to the p + -Si layer 120.
  • current charging to the LF integrator p + -Si layerl20
  • the LF integrator is in a steady-state due to the discharge current (both holes 64 and electrons 62) through the LF governor (i-Si layer 110).
  • the charge-discharge mechanism of the LF integrator is the same as described for FIG. 9.
  • FIG. 32A shows a sequence of material layers corresponding to the structure of FIG. 31 and FIGS, 32B-32C depict energy band diagrams corresponding to the material layer structure shown in FIG. 32A during various operational conditions of the amplifier.
  • FIG. 32D graphically depicts the functional components of the avalanche amplifying structure shown in FIG. 31.
  • the electric field strength within the p-Si layer 100 is sufficient for impact ionization when a positive voltage is applied to transparent electrode 105.
  • the normal operating voltage should exceed the breakdown voltage, thus initiating the Geiger mode.
  • avalanche multiplication occurs near the Si-SiO 2 interface within the p-Si layer 100, as shown in Fig. 32C by the free carriers or electrons 62.
  • the process is self-sustaining due to the avalanche multiplication, wherein the current filament with current density grows exponentially in time.
  • the filament electrons are accumulated at the Si-SiO 2 interface.
  • the mobility of these electrons is not high so they are accumulated locally, thus screening the electric field within the filament area and terminating the avalanche process.
  • the Si-SiO 2 interface operates as a HF integrator with a time constant, defined by the mobility of electrons spreading along the interface.
  • the capacity and discharge current of the LF integrator should be sufficient so that the LF integrator does not change its state after the collection of the FIRST charge package; however, the integrating-relaxation time of the LF integrator will be higher than that of HF integrator.
  • the integration time is regulated by the voltage applied to the electrode 117.
  • Several charge packages may be gathered within the integration time and the field is decreased in the p-Si layer 100 because charge is not removed from it.
  • the LF integrator accumulates a SECOND charge package, also shown in FIG. 32D, consisting of a predefined number of FIRST packages. As represented in FIG.
  • FIG. 32D several amplification channels may exist simultaneously within the p-Si layer 100 depending on the number of free carriers, each initiating the multiplication process where they hit.
  • Three such processes or virtual channels are shown in FIG. 32D.
  • Each virtual channel has the same set of functional elements, including reader 9, threshold amplifier 10, quantifier 11, HF (high frequency) integrator 12, HF governor 13, and HF reader 14. All HF governors within the virtual channels are connected to a single LF (low frequency) integrator 21 which accumulates FIRST packages after they are drained through the HF governors 13.
  • This second stage of the discrete amplifier functional scheme, forming the SECOND calibrated packages, includes a LF integrator 21, a LF governor 22, a LF reader 23, all shown in FIG. 32D.
  • the described device allows one to detect a few- photon pulses as a digital or calibrated or signal on the electrode 117 while non-signal pulses caused by thermogeneration at the same electrode 117 are easily discriminated. Voltage regulation of the LF integration time at the electrode 117 allows the device to detect the pulse length of light with PET applicability. Also, one can count single- photon events with high time resolution by reading the signal at the electrode 105, with photon counter applicability. Multi-Channel Devices
  • the single-channel avalanche amplifying devices described above may be integrated into a variety of multi-channel devices, providing full functionality for a photodetector with discrete amplification as described in USPN 6,885,827.
  • the present invention includes all avalanche amplifying devices wherein the interface between two layers within a semiconductor laminate disposed between two or more electrodes function as either a quantifier, an integrator, or a quantifier and integrator either separately or in combination.
  • FIG. 33 an avalanche amplifying structure 1 with a lateral direction of avalanche and hole integrator is shown and described.
  • the device includes a first electrode 2, a contact layer 25, an avalanche region 3, a signal transport layer 27, a dielectric layer 19, an integrator 5, a governor 6, a substrate 7, and a second electrode 8.
  • FIG. 34 the structure from FIG.
  • array means two or more avalanche amplifying structures 1 arranged in a geometric pattern. Abutting pairs of avalanche amplifying structures 1 are preferred to be separated by a gap not less than 0.5 ⁇ m.
  • the gap between integrators 5 may be filled with a semiconductor material which also composes the avalanche region, a lightly doped semiconductor material of same conductivity type as the integrator 5, or a dielectric material. It is preferred for avalanche amplifying structures 1 to be geometrically and dimensionally identical.
  • Avalanche amplifying structures 1 may include a variety of regular and arbitrary shapes including triangles, rectangles, squares, polygons, and circles.
  • a third electrode 50 may be added to the structure as described above.
  • First electrodes 2, second electrodes 8, and third electrodes 50, and substrates 7 may be comprised of separate single continuous sheets onto which other layers within the avalanche amplifying structures 1 are attached.
  • First electrodes, second electrodes, and third electrodes may be composed of a transparent.
  • a dielectric layer 19, blocking layer 24, or conductive region 25 may be added to the structure to enhance the performance of the avalanche amplifying structure 1, as described above.
  • FIG. 35 a schematic illustration of the multi-channel device in FIG. 34 including the single channel element from FIG. 33 is shown and described.
  • the device includes three transparent electrodes 105, n + -Si regions 102, a p-Si layer 103, p + regions 130, a p-Si layer 100, an i-Si layer 113, a p + -Si layer 90, and an electrode 106.
  • the device is fabricated on a silicon substrate with doping having a resistivity of 0.01 Ohm-cm, an orientation [100] and a thickness of 350 ⁇ m.
  • the i-Si layer 113 is an epitaxial silicon without doping with a width so that the distance between p + -Si regions 130 and p + -Si layer 90 is 2 ⁇ m.
  • the p + -Si regions 130 include p + type doping is the first epitaxial layer and are dimensionally sized to be small.
  • the second epitaxial layer or p-Si layer 100 has a width so that the distance between n + -Si regions 102 and p + -Si regions 130 is 5 ⁇ m.
  • the p-Si layer 100 layer is p-doped with a resistance of 7-10 Ohm-cm.
  • the third p-doped epitaxial layer has resistance of 1 Ohm- cm and a width of 2 ⁇ m.
  • the n + -Si layer 102 is fabricated by diffusion with a n-type impurity.
  • the top surface is oxidized with a thickness of 0.5 ⁇ m, then ITO is deposited and etched (via lithography) to form electrodes 105.
  • the electrodes 105 have a diameter of 2 ⁇ m and all are connected with each other and the metal contact plate by a transparent conductor 105.
  • the metal electrode 106 is fabricated via methods understood in the art. Channels may be packed to form a variety of patterns and shapes. The distance between channels is typically 10-14 ⁇ m. This distance may be in the range 8- 30 ⁇ m in order to optimize quantum efficiency at a desired wavelength, timing resolution, and minimize channel interaction or cross-talk. Lower interaction is achieved with larger distances; however, larger distances decrease the quantum efficiency. Thus, the optimum distance depends on end use of the device.
  • FIG, 36 shows an exemplary top plan view of a multi-channel device wherein seven transparent electrodes 105 are disposed about a device having a transparent cover 150. A pair of wires 152 from the device to a contact plate 151 is shown so as to communicate signals to a recording device.
  • FIG. 37 shows a device having a single transparent cover 150.
  • FIGS. 38A-38E several additional exemplary multi-channel devices are shown and described.
  • the multi-channel device is composed of three avalanche amplifying structures 1 with a normal direction of avalanche, as provided in FIG. 7 A above.
  • the avalanche amplifying structures 1 include a first electrode 2, a governor 6, an integrator 5, a quantifier 4, an avalanche region 3, a substrate 7, and a second electrode 8 arranged in the order described.
  • Individual integrators 5 and quantifiers 4 are separated by a distance not less than 0.5 ⁇ m.
  • the space between integrators 5 includes a dielectric layer 19 composed of a semiconductor material, preferably lightly doped, of which the avalanche region 3 is composed.
  • the integrators 5 and quantifiers 4 are preferred to be equidistant from each other having a distance not less than 0.5 ⁇ m.
  • the integrators 5 and quantifiers 4 may be shaped in the form of a regular polygon, a square, a hexagon, or a circle.
  • the first electrodes 2 may be disposed over the whole working area of the multi-channel device.
  • the first electrode may be a mesh electrode which contacts the governor 6 above all of the individual integrators 5.
  • the multi-channel device is composed of three avalanche amplifying structures with a lateral direction of avalanche, as provided in FIG. 15D.
  • the avalanche amplifying structures 1 include a first electrode 2, a governor 6, an integrator 5, a substrate 7 and a second electrode 8, arranged in the order described.
  • the integrator 5 is disposed within a hole along the avalanche region 3 so that contact between the two elements provides a ring-shaped quantifier 4.
  • First electrode 2, second electrode 8, integrators 5 and governor 6 are separated from other each by a distance not less than 0.5 ⁇ m.
  • the space between integrators 5 includes a dielectric layer 19 composed of a semiconductor material, preferably lightly doped, of which the avalanche region 3 is composed.
  • the integrators 5 and quantifiers 4 are preferred to be equidistant from each other having a distance not less than 0.5 ⁇ m.
  • the first electrodes 2 may include a solid electrode which covers the entire working area of the structure. Likewise, it is possible for the first electrodes 2 to be composed of a mesh electrode which provides electrical contact with the governor 6 above the individual integrators 5.
  • the governor 6 may be disposed exclusively under the mesh structure of the first electrode 2.
  • the integrators 5 may be spaced equidistant from each other having a distance no less than 0.5 ⁇ m.
  • the integrators 5 and quantifiers 4 may be shaped in the form of a regular polygon, a square, a hexagon, or a circle.
  • the multi-channel device is composed of three avalanche amplifying structures 1 with a lateral direction of avalanche, as provided in FIG. 15C above.
  • the avalanche amplifying structures 1 include a first electrode 2, a governor 6, an integrator 5, an avalanche region 3, and a substrate 7, arranged in the order described.
  • the second electrode 8 is a ring-shaped structure which contacts the avalanche region 3 opposite of the substrate 7.
  • the quantifier 4 is vertically disposed and between the integrator 5 and avalanche region 3 so that the contact region between the two elements provides a ring-shaped quantifier 4.
  • the second electrode 8 is a mesh-type element so that its electric contact with the governor 6 and integrator 5 is avoided.
  • the avalanche regions 3 and second electrodes 8 are covered by a dielectric layer 19 so that the first electrode 2 electrically contacting the governor 6 within each avalanche amplifying structure 1 has no electrical contact with the second electrode 8, avalanche region 3, and integrator 5.
  • the multi-channel device is composed of three avalanche amplifying structures 1 with a lateral direction of avalanche.
  • the avalanche amplifying structures 1 include a first electrode 2, a governor 6, an integrator 5, a substrate 7, and a second electrode 8, arranged in the order described.
  • the quantifier 4 is vertically disposed and between the integrator 5 and avalanche region 3 which surrounds the integrator 5 so that the contact region between the two elements provides a ring- shaped quantifier 4.
  • a dielectric layer 19 is provided between a third electrode 50 and the avalanche region 3.
  • a second dielectric layer 19 is also provided above the third electrode 50 and contacts the governors 6.
  • the dielectric layers 19 electrically isolate the first electrode 2 and third electrode 50 from elements composing the structure.
  • the third electrode 50 does not contact the governors 6.
  • Integrators 5 and governors 6 are equidistance from each other at a distance no less than 0.5 ⁇ m.
  • the multi-channel device is composed of three avalanche amplifying structures 1 with a normal direction of avalanche, as provided in FIG. 1.
  • the avalanche amplifying structures 1 include a first electrode 2, an avalanche region 3, a quantifier 4 disposed between the interface of the avalanche region 3 and integrator 5, an integrator 5, a governor 6, a substrate 7, and a second electrode 8, arranged in the order described.
  • First electrode 2, second electrode 8, integrators 5 and governor 6 are separated from other each by a distance not less than 0.5 ⁇ m.
  • the space between integrators 5 includes a dielectric layer 19 composed of a semiconductor material, preferably lightly doped, of which the avalanche region 3 is composed.
  • the integrators 5 and quantifiers 4 are preferred to equidistant from each other having a distance not less than 0.5 ⁇ m.
  • the first electrodes 2 may include a solid electrode which covers the entire working area of the structure. Likewise it is possible for the first electrodes 2 to be composed of a mesh electrode which provides electrical contact with the governor 6 above the individual integrators 5.
  • the governor 6 may be disposed exclusively under the mesh structure of the first electrode 2.
  • the integrators 5 may be spaced equidistant from each other having a distance no less than 0.5 ⁇ m.
  • the integrators 5 and quantifiers 4 may be shaped in the form of a regular polygon, a square, a hexagon, or a circle.
  • the description above indicates that a great degree of flexibility is offered in terms of the present invention.
  • the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein. 6.
  • Industrial Applicability As is evident from the explanation above, the described invention includes various intelligent amplifying avalanche structures operating on the principles described herein. Devices are applicable as self-contained highly sensitive instruments capable of recording and counting individual electrons and photons. Devices are also applicable within arrayed configurations. Accordingly, the described invention is expected to be used within photodetectors, electron amplifiers, chemical and biological sensors, and chemical and biological chips with lab-on-a-chip applications. Structures have immediately applicability to devices critical to homeland defense.

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Abstract

L'invention concerne des structures d'amplification en avalanche (1) comprenant des électrodes (2) et (8), une région d'avalanche (3), un quantificateur (4), un intégrateur (5), un gouverneur (6) et un substrat (7) agencés de façon à détecter un signal faible composé de quelques électrons. Le quantificateur (4) régule le processus d'avalanche. L'intégrateur (5) accumule une charge de signal. Le gouverneur (6) draine l'intégrateur (5) et commande le quantificateur (4). Les structures d'amplification en avalanche (1) comprennent: des dispositifs de polarisation inverse à quantificateur normal; des dispositifs de polarisation normale à quantificateur normal; des dispositifs de polarisation normale à quantificateur latéral; des dispositifs de polarisation normale à quantificateur interchangeable et à électrodes variables; des dispositifs de polarisation normale à quantificateur normal, et à électrodes variables; et des dispositifs de polarisation normale à quantificateur latéral et à intégrateurs annulaires. Les structures d'amplification en avalanche (1) sont disposées de façon à former des matrices de dispositifs multicanaux. Ces structures sont particulièrement destinées à des dispositifs critiques de la défense du territoire.
EP06772574A 2005-06-10 2006-06-10 Matrices et detecteurs haute sensibilite, haute resolution Withdrawn EP1894223A2 (fr)

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WO2006135683A2 (fr) 2006-12-21
CA2613195A1 (fr) 2006-12-21
JP2008544496A (ja) 2008-12-04
IL188040A0 (en) 2008-03-20
WO2006135683A3 (fr) 2007-03-22
RU2406181C2 (ru) 2010-12-10
KR20080074084A (ko) 2008-08-12
RU2008100029A (ru) 2009-07-20

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