EP1758126A3 - Nanoscale selection circuit - Google Patents

Nanoscale selection circuit Download PDF

Info

Publication number
EP1758126A3
EP1758126A3 EP06022522A EP06022522A EP1758126A3 EP 1758126 A3 EP1758126 A3 EP 1758126A3 EP 06022522 A EP06022522 A EP 06022522A EP 06022522 A EP06022522 A EP 06022522A EP 1758126 A3 EP1758126 A3 EP 1758126A3
Authority
EP
European Patent Office
Prior art keywords
nanoscale
wires
selection circuit
selecting
nanoscale wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06022522A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1758126A2 (en
Inventor
Andre Dehon
Patrick D. Lincoln
Charles M. Lieber
John Savage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SRI International Inc
California Institute of Technology
Brown University
Harvard University
Original Assignee
SRI International Inc
California Institute of Technology
Brown University
Harvard University
Stanford Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SRI International Inc, California Institute of Technology, Brown University, Harvard University, Stanford Research Institute filed Critical SRI International Inc
Publication of EP1758126A2 publication Critical patent/EP1758126A2/en
Publication of EP1758126A3 publication Critical patent/EP1758126A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/81—Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/943—Information storage or retrieval using nanostructure

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Micro-Organisms Or Cultivation Processes Thereof (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Prostheses (AREA)
  • Silicon Compounds (AREA)
  • Ropes Or Cables (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
EP06022522A 2002-07-25 2003-07-24 Nanoscale selection circuit Withdrawn EP1758126A3 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US39894302P 2002-07-25 2002-07-25
US40039402P 2002-08-01 2002-08-01
US41517602P 2002-09-30 2002-09-30
US42901002P 2002-11-25 2002-11-25
US44199503P 2003-01-23 2003-01-23
US46535703P 2003-04-25 2003-04-25
US46738803P 2003-05-02 2003-05-02
EP03796282A EP1525586B1 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP03796282A Division EP1525586B1 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Publications (2)

Publication Number Publication Date
EP1758126A2 EP1758126A2 (en) 2007-02-28
EP1758126A3 true EP1758126A3 (en) 2007-03-14

Family

ID=32097212

Family Applications (3)

Application Number Title Priority Date Filing Date
EP06022522A Withdrawn EP1758126A3 (en) 2002-07-25 2003-07-24 Nanoscale selection circuit
EP03796281A Withdrawn EP1525585A2 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces
EP03796282A Expired - Lifetime EP1525586B1 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Family Applications After (2)

Application Number Title Priority Date Filing Date
EP03796281A Withdrawn EP1525585A2 (en) 2002-07-25 2003-07-24 Stochastic assembly of sublithographic nanoscale interfaces
EP03796282A Expired - Lifetime EP1525586B1 (en) 2002-07-25 2003-07-24 Sublithographic nanoscale memory architecture

Country Status (7)

Country Link
US (2) US6900479B2 (https=)
EP (3) EP1758126A3 (https=)
JP (2) JP2006512782A (https=)
AT (2) ATE360873T1 (https=)
AU (2) AU2003298529A1 (https=)
DE (2) DE60325903D1 (https=)
WO (2) WO2004034467A2 (https=)

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US20060175601A1 (en) * 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
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Also Published As

Publication number Publication date
ATE360873T1 (de) 2007-05-15
EP1525586B1 (en) 2007-04-25
US20040113138A1 (en) 2004-06-17
AU2003298530A8 (en) 2004-05-04
AU2003298529A1 (en) 2004-07-29
EP1525585A2 (en) 2005-04-27
WO2004061859A3 (en) 2005-02-03
US6963077B2 (en) 2005-11-08
ATE421147T1 (de) 2009-01-15
WO2004034467A3 (en) 2004-08-26
DE60313462T2 (de) 2008-01-03
DE60325903D1 (de) 2009-03-05
WO2004061859A2 (en) 2004-07-22
AU2003298530A1 (en) 2004-05-04
US6900479B2 (en) 2005-05-31
EP1525586A2 (en) 2005-04-27
AU2003298529A8 (en) 2004-07-29
EP1758126A2 (en) 2007-02-28
JP2006512782A (ja) 2006-04-13
WO2004034467A2 (en) 2004-04-22
DE60313462D1 (de) 2007-06-06
JP2005539404A (ja) 2005-12-22
US20040113139A1 (en) 2004-06-17

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