Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F2221/2101—Auditing as a secondary aspect

Definitions

• the invention relates to an arrangement with an integrated circuit and an integrated circuit with function modules, the function modules comprising a central processing unit, by means of which data can be processed and programs can be executed, and a cache memory.
• Previously tamper-proof systems with high security requirements regularly consist of several discrete assemblies, to which different functions are assigned, for example a central processing unit, an encryption unit and various memories are each regularly an independent unit that is connected to the other units.
• the requirement of several assemblies and their combination and coordination with each other goes hand in hand with high costs in series production.
• the object of the invention is to create an arrangement of the type mentioned at the outset which satisfies the highest requirements of security against manipulation and at the same time is suitable for series production at lower costs.
• the object according to the invention is achieved by means of an integrated circuit of the type mentioned at the outset, which comprises an encryption unit as a function module, by means of which data or program code can be encrypted and decrypted.
• an encryption unit as a functional module of the integrated circuit is an element of this component, the additional provision, assembly and adjustment to surrounding components can be saved in the manufacture and development of an arrangement with an integrated circuit according to the invention.
• the encryption unit is difficult to separate from the integrated circuit, of which it is a component, and attempts at manipulation are therefore doomed to fail.
• an integrated circuit according to the invention in particular the separation of individual function modules, is particularly difficult if the integrated circuit is designed as a semiconductor chip, in particular if individual function modules interlock like a puzzle, in such a way that individual function modules are no longer discreetly recognizable.
• Particularly complex geometrical entanglements can be selected here, so that the semiconductor structures mixed together can be analyzed with the intention of manipulation, can no longer be recognized as separable.
• the function modules comprise a first memory in which cryptological keys are stored.
• the integration of such a first memory makes targeted access and targeted reading of the cryptological keys difficult.
• the effort for managing cryptological keys by the manufacturer of the devices is completely eliminated with additional security gain if the function modules comprise a random number generator (RNG) which generates the cryptological keys as it were autonomously.
• RNG random number generator
• a real-time clock can advantageously be integrated into the integrated circuit, the correct function of which is also highly relevant for security against manipulation.
• a safety sensor can advantageously be integrated in the circuit as a function module, by means of which at least one operating parameter of the integrated circuit can be monitored.
• Suitable operating parameters for monitoring are, for example, the clock frequency of the real-time clock, the system or CPU clock, or an operating temperature, or an operating voltage of the integrated circuit, or the state of a protective layer on the integrated circuit, or a combination of the aforementioned operating parameters.
• the monitoring of the state of a protective layer on the integrated circuit is particularly effective since the protective layer must be destroyed in order to mechanically access the structure of the semiconductor chip.
• the protective layer is formed as an active protective layer and is applied directly to the die of the semiconductor chip.
• the active protective layer consists of at least one elongated electrical line which runs along the surface of the die, in particular in sections in mutually parallel paths.
• the monitoring can be, for example, a monitoring of the ohmic resistance of the electrical line, wherein a change in the resistance value, which suggests a destruction of the electrical line, advantageously deletes the data to be protected.
• the microcontroller is preferably brought into a secure state, for example a reset. In this way, the "integrated circuit" system according to the invention becomes comparatively intrinsically safe.
• the monitoring of the operating parameter is expediently designed in such a way that at least one limit value is specified for the operating parameter to be monitored, which: measures operating parameters and compares them with the limit value, and deletes the content of the first memory when the limit value is exceeded or fallen below becomes.
• the limit value is expediently to be selected such that the specifications of normal operation do not lead to an interruption in the function of the arrangement, for example in the automotive sector at a temperature of -40 ° C. the data is not yet deleted.
• the manageability and safety of the integrated circuit according to the invention is additionally increased if it is arranged in a housing and has connection contacts led out of the housing. Accordingly, for the purpose of mechanical manipulation, the housing must first be opened.
• a higher integration of the circuit according to the invention can be achieved "if individual function modules have an essentially flat extension and are arranged adjacent to one another in the direction of the surface normals.
• the central processing unit can be stacked with different memories or other function modules.
• Attacks that infer conclusions about the functional state from the behavior of the supply current of the integrated circuit can advantageously be warded off if the functional modules include an integrated voltage regulator that regulates the operating voltage and in this way comparatively noises these operating parameters to the outside.
• the integrated circuit according to the invention has particular advantages in an arrangement with a second memory which is connected to the integrated circuit according to the invention by means of a data bus, in which second memory data or program code are stored in encrypted form and which has memory cells, each of which has a memory address and each memory cell can be addressed directly by reading or writing.
• a data bus in which second memory data or program code are stored in encrypted form and which has memory cells, each of which has a memory address and each memory cell can be addressed directly by reading or writing.
• a Battery is connected, so that the voltage supply is maintained in the absence of any other power supply. In this respect, costs can also be saved if the second memory is inexpensively volatile and is buffered by means of the battery.
• a third memory can be expedient, which is connected to the integrated circuit by means of a data bus and is non-volatile, in particular as a flash. or ROM is formed, the data or program code preferably being stored in encrypted form in the third memory.
• Buffering of the safety sensors by means of a battery is particularly advantageous.
• an auxiliary energy source for example a capacitor, integrated in the housing can be provided, which provides the energy in the event of a registered manipulation attempt to erase the memories, in particular the first memory.
• FIG. 1 is a schematic representation of an inventive arrangement.
• FIG. 1 shows an integrated circuit 1 with various function modules 2, which is connected to external components 3.
• the integrated circuit has further function modules 2, namely a cache memory 5, an encryption unit 6, a first memory 7, a real-time clock 8, a random number generator 80 and a safety sensor system 9.
• function modules 2 namely a cache memory 5, an encryption unit 6, a first memory 7, a real-time clock 8, a random number generator 80 and a safety sensor system 9.
• a voltage regulator 10 and an auxiliary power source 12 integrated components of the integrated circuit 1 designed as a semiconductor chip 13.
• the central processing unit 4 processes data or executes programs which it reads out of the cache memory 5 by means of a first data bus 15.
• the cache memory 5 is connected to the encryption unit 6 by means of a second data bus 16.
• the encryption unit 6 reads the encrypted data or code from the second or third memory 40, 41 using the address data bus 32, decrypts it using the cryptographic key 18 stored in the first memory 7 and writes it to the cache or to others internal registers of the central processing unit 4.
• the cryptological keys 18 have previously been generated by the random number generator 80.
• the random number generator 80 uses, for example, the start values from the statistical fluctuations (noise) of internal, physical measured variables, such as chip temperature, supply voltage, clock frequency, to generate the cryptographic keys 18 which are stored in the first memory 7; ,
• the safety sensor system 9 In addition to the operating temperature T, the operating voltage M, the clock frequency f, the safety sensor system 9 also monitors the ohmic resistance R of a protective layer 20, which consists of there are essentially mutually parallel tracks of an electrical line 21 which are applied directly to the die of the semiconductor chip 13.
• the measured resistance R is permanently compared with a limit value, and if the limit value is exceeded, the central processing unit 4 causes the first memory 7 to be erased, the integrated circuit 1 subsequently being transferred to a secure state, for example a reset.
• the integrated circuit 1 is surrounded by a housing 30 which has connection contacts 3-1 which are at least partially connected to an address data bus 32.
• the integrated circuit 1 exchanges data with a second memory 40 and a third memory 41 by means of the address data bus 32.
• the second memory 40 is designed as volatile RAM and is protected against voltage failure by means of a battery 43, as is the integrated circuit 1.
• the third memory 41 is designed as a non-volatile flash or ROM.
• the data stored in the second memory 40 and third memory 41 are encrypted using the cryptological key 18 and are encrypted or decrypted each time they are accessed using the: encryption unit 6.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Mathematical Physics (AREA)
• Computer Security & Cryptography (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Storage Device Security (AREA)
• Semiconductor Integrated Circuits (AREA)
• Microcomputers (AREA)

Applications Claiming Priority (2)

Publications (1)

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Citations (10)

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• 2004
  • 2004-03-24 DE DE102004014435A patent/DE102004014435A1/de not_active Withdrawn
• 2005
  • 2005-03-10 BR BRPI0509073-3A patent/BRPI0509073A/pt not_active IP Right Cessation
  • 2005-03-10 WO PCT/EP2005/051072 patent/WO2005098567A1/de active Application Filing
  • 2005-03-10 EP EP05716983A patent/EP1728137A1/de not_active Ceased
  • 2005-03-10 RU RU2006137366/08A patent/RU2412479C2/ru active
  • 2005-03-10 US US10/599,230 patent/US8577031B2/en active Active
  • 2005-03-10 CN CNA2005800090492A patent/CN1934517A/zh active Pending
  • 2005-03-10 JP JP2007504396A patent/JP2007535736A/ja not_active Withdrawn

Patent Citations (10)

Non-Patent Citations (1)

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