EP1680814A2 - Procede et dispositif de connexion de puces - Google Patents
Procede et dispositif de connexion de pucesInfo
- Publication number
- EP1680814A2 EP1680814A2 EP04805792A EP04805792A EP1680814A2 EP 1680814 A2 EP1680814 A2 EP 1680814A2 EP 04805792 A EP04805792 A EP 04805792A EP 04805792 A EP04805792 A EP 04805792A EP 1680814 A2 EP1680814 A2 EP 1680814A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- face
- circuit
- connection
- transfer element
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/15—Charge-coupled device [CCD] image sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
- H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
- H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- the technical field to which the invention relates is that of microelectronics or optoelectronics and more specifically the manufacture of microelectronic or optoelectronic components and their external connection means (inputs / outputs).
- the invention can be applied to all kinds of devices requiring the dense interconnection of several electronic chips on an interconnection support of reduced surface area.
- One application is that of the juxtaposition or the joining of several components for example for large imagers or large screens.
- the invention allows for example the juxtaposition of components with a minimum loss of pixels limited to one side.
- Another application relates to the juxtaposition of ink injection chips for printers or other electronic components.
- the feeds must therefore transit from the upper face 8 of each component to the support 4. As illustrated in FIGS. 1B and 1C, this transit is generally carried out by welding wires 6 which are welded on the one hand to pads 10 thermocompression located at the front of the component, on the other hand on the interconnection support 4.
- the lateral spaces required for this operation are very large and in particular cause a significant number of detection pixels to be lost or emission in the juxtaposition zones.
- the document US 2002/2006098 describes a method of interconnection through a silicon chip.
- this technique is extremely complex and its implementation must be done on complete wafers (200mm, 30Omm) of silicon circuit.
- this technique is unsuitable for carrying out on a unit chip, cut from a wafer or substrate. Nor can such a technique be applied, for example, to foundry batches shared by several users.
- the invention relates to an electronic device comprising: - an active element or a circuit, comprising a first and a second face, the first face being provided with means of electrical connection, - an element, or a circuit, or transfer means, comprising a first face and a second face and being assembled by its first face to the second face of the active element, as well as electrical connection means on its second face, - a connection, preferably wired, between the electrical connection means of the active element or of the circuit and of the transfer element.
- Connection means being provided on the transfer element, a connection, for example wired, can be made between the first face of the active element and the second face of the transfer element.
- Wired is understood to mean both a connection by electric wire and by electrical tape. There is therefore no direct connection to be made between the active element and an assembly circuit or a semiconductor wafer.
- the transfer element can, for its part, be fixed on such a wafer or on such an assembly circuit.
- the transfer element has a width, in a direction perpendicular to a side of the active element on which or in the vicinity of which electrical connection means are provided, less than that of the active element itself. Preferably the latter is the only one to be transferred to, or fixed to, the transfer element. This lower width makes it possible to bring a wire connection from the first face of the active element to the second face of the element or transfer circuit but below the active element.
- This transfer element can be of any material, for example silicon or ceramic.
- the circuit may include an electronic circuit, for example a semiconductor, such as a CMOS or CCD circuit, or an interconnection network, or a bipolar circuit.
- Means for detecting or emitting radiation, and / or, optionally, mechanical or electromechanical means, can be integrated or hybrid on the circuit or the electronic circuit.
- MEMS electronic-mechanical micro-systems
- micro-mirrors for example one or more micro-mirrors and / or one or more bolometers and / or one or more force sensors.
- These electronic means can be integrated into the circuit and / or be hybrid on the first face of the circuit.
- the invention also relates to an electronic system comprising a plurality of such devices. Each of the transfer elements of these devices is connected or fixed to a common substrate by means of balls or pins or connection pads.
- the invention also relates to a method for producing a device, for example electronic, comprising: - the assembly of a circuit or of an active circuit, comprising a first and a second face, the first face being provided with means of electrical connection, with a transfer element, comprising a first and a second facess and means of electrical connection on its second face, the assembly being carried out by its first face to the second face of the active element, the element of transfer being intended to be assembled on another circuit or on a semiconductor wafer on the side of this same second face, - the making of a connection, preferably wired, between the means of electrical connection of the element or of the circuit active and carry forward item.
- This method can also include the creation of a connection protection layer.
- the assembly of the circuit and the transfer element may comprise the formation, on one and / or the other of the two faces of the circuit and of the transfer element intended to be assembled, with a layer of adhesive. or an adhesive film or an adhesive strip or welding means.
- FIG. 1A to 1C represent devices of the prior art
- FIG. 2A to 2D represent steps of a method according to the invention
- - Figure 3 is an embodiment of a device according to the invention
- - Figures 4A and 4B show assembled systems of devices according to the invention.
- FIGS. 2A to 2D A first embodiment of the invention is described in connection with FIGS. 2A to 2D.
- the component 20 to be interconnected by the rear face is provided with means 22 for electrical connection, for example one or more thermocompression pads, on one of its sides.
- the thickness of the component is E2.
- This component 20 generally has a quadrilateral shape, as illustrated in FIG. 1A, of width L1 in a direction perpendicular to the side provided with connection means 22.
- An intermediate or transfer element 24, of thickness E1 is produced separately.
- This item 24 can be for example a single or multi-layer ceramic, or a printed circuit.
- This intermediate or transfer element generally has a shape similar to that of component 20. In a direction perpendicular to the side of the component
- connection means 22 on which the connection means 22 are located, it preferably has a width L2 ⁇ L1. It also includes on one of its surfaces connection means, for example one or more pads 26. These pads can be connected to interconnection tracks which redistribute each pad 26 towards balls (BGA type connection) yes pins 40,
- connection means distributed over the surface of the element 24.
- the intermediate or transfer element 24 is able to be assembled on another support such as a circuit or a semiconductor wafer, on the side of this same surface on which the connection means are located.
- the component 20 and the intermediate element 24 are placed side by side, the connection means 22, 26 facing each other.
- a spacer 30 of width 1 greater than E1 + E2 can optionally be used to maintain a spacing of width 1 between the component 20 and the element 24 during the making of the connection.
- the electrical connection wires 32 are then drawn between the connection means of the component 20 and those of the intermediate element 24.
- Preparing the rear face 34 of one or the other or of the two components for subsequent bonding or welding for example by depositing a layer of adhesive, or welding, or a dry film, or a double sticky tape face, ....
- the reference 36 designates for example a layer of adhesive.
- the intermediate element 24 is turned 180 ° by folding it under the component 20 (after advantageous removal of the spacer 30) and the connection between component 20 and intermediate element 24 is terminated by the crosslinking of the adhesive. deposited or reflow of the weld or another method of attachment.
- the two initial elements are therefore linked, the new component created comprising electrical inputs / outputs 40, 42 on the rear face 43, for example spatially distributed in 2D on the free face of the element 24.
- the wired connections 32 are therefore connected , on the one hand at the upper surface of the component 20, on the other hand at the surface 43 of the element 24. On the latter, the ends of these connections are therefore located in a zone A situated under the component 20 or delimited by this component 20.
- Each wire 32 can therefore pass close to the side or edge 21 of the component 20.
- There is therefore a lateral extension of the wire connection much less than it is in the prior art as 'illustrated for example in Figure 1C.
- a shaping of the connecting wires (for example by pressing ...) may possibly be performed.
- a protection 44 for the lateral passage of the wires can then be implemented, for example by encapsulation, by gluing or by deposition (of parylene for example).
- An exemplary embodiment is illustrated in FIG. 3: it relates to the production of components for photon detection, several of these components being intended to be juxtaposed to form a detection matrix.
- Each elementary component comprises for example 100 * 100 square pixels of 200 ⁇ m each side (therefore of area 20O ⁇ m X 200 ⁇ m each).
- a pixelated detection circuit 52 is hybrid on a 50 CMOS reading circuit mounted on an intermediate element 54 provided with connection means. Firstly, a “composite” circuit 50 CMOS circuit / intermediate element 54 is produced.
- the CMOS circuit 50 is cut 20 ⁇ m from the edge of the active circuits on three sides and 80 ⁇ m from the first active pixel on the fourth side, that on which connection pads 53 are located, for example thermocompression pads.
- This circuit has, for example, a size of 20.04 mm by 20.1 mm.
- An intermediate element 54 of ceramic type (Al 2 0 3 , or AIN, etc.) is provided with assembly means 58 for printed circuit. These means are for example pins and make the element 54 connectable and disconnectable. Connection pads 62 will make it possible to fix a connection wire 56 to connect them electrically to the pads 53.
- the ceramic 54 is preferably smaller than the circuit 50, for example it has a size of 1.8 mm ⁇ 1.8 mm.
- the steps described above are carried out in conjunction with FIGS. 2A to 2D using thicknesses E1 and E2 of 500 ⁇ m, a shim 30 of 1.1 mm wide, a connection wire 56 of 25 ⁇ m in diameter and a deposit 44 of parylene for final coating of the wire 56.
- the composite circuit will have the following characteristics: - on three sides: possibility of juxtaposing another circuit at a distance of approximately 20 ⁇ m, - on the side of the circuit 50 where the wires 56 are located: possibility juxtaposition at a distance of approximately 130 ⁇ m: 80 ⁇ m (width of the connection pad 53) + 25 ⁇ m (thickness of the wire 56) + 15 ⁇ m (guard width) + 10 ⁇ m (thickness of the parylene).
- the active circuit 50 is for example provided with connection balls 60, distributed with a pitch of 200 ⁇ m, on which a circuit 52 for detecting photons has been hybridized so that it only loses 0.5 pixels out of the four sides.
- the detector circuit 52 passes over the wires 56.
- a wire connection is made with a very limited lateral extension, the assembly means 58 being brought back or located in zone A located under the component 50. It is then possible to assemble by inserting the pins 58 into a support circuit.
- FIGS. 4A and 4B represent a tiling obtained.
- FIG. 4A several elementary components 64, 66, 68 of the type described above in connection with FIG. 3 are to be assembled on a circuit 70 or a silicon substrate.
- FIG. 4B represents a top view of components, for example detectors 72, each being assembled with a corresponding intermediate element (shown in dashed lines), itself assembled or fixed on a circuit or substrate 80 common to the set of detectors.
- the invention makes it possible to limit the loss, in the juxtaposition limit zones, to a row of pixels (ie a dead zone of approximately 200 ⁇ m in width).
- the tolerance conditions for positioning on the printed circuit are not taken into account in this numerical example.
- an intermediate element can be transferred to the rear face of a chip and the inputs / outputs of the chip are brought to the rear of the chip / intermediate element assembly. The connection of this assembly is thus facilitated and makes it possible to gain density of integration.
- Other elements can be associated with each chip, for example hybrids on its front face.
- the invention applies to the production of large detectors, in particular infrared detectors, juxtaposable bolometric detectors, X-ray scanners or large gamma ray detectors. Large size emissive screens can also be produced.
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0350774A FR2861895B1 (fr) | 2003-11-03 | 2003-11-03 | Procede et dispositif de connexion de puces |
| PCT/FR2004/050549 WO2005045934A2 (fr) | 2003-11-03 | 2004-10-28 | Procede et dispositif de connexion de puces |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1680814A2 true EP1680814A2 (fr) | 2006-07-19 |
Family
ID=34430070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP04805792A Withdrawn EP1680814A2 (fr) | 2003-11-03 | 2004-10-28 | Procede et dispositif de connexion de puces |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7569940B2 (fr) |
| EP (1) | EP1680814A2 (fr) |
| FR (1) | FR2861895B1 (fr) |
| WO (1) | WO2005045934A2 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3355081B1 (fr) * | 2017-01-27 | 2019-06-19 | Detection Technology Oy | Structure de tuile en composé semi-conducteur à conversion directe |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US577391A (en) * | 1897-02-16 | Nursery-bottle support | ||
| JPS6030171A (ja) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | 混成集積回路装置 |
| US4743868A (en) * | 1985-04-03 | 1988-05-10 | Nippondenso Co., Ltd. | High frequency filter for electric instruments |
| US5396104A (en) * | 1989-03-28 | 1995-03-07 | Nippon Steel Corporation | Resin coated bonding wire, method of manufacturing the same, and semiconductor device |
| DE69024313T2 (de) * | 1989-10-20 | 1996-06-13 | Matsushita Electric Ind Co Ltd | Oberflächenmontierbare Netzwerkvorrichtung |
| JP2772739B2 (ja) * | 1991-06-20 | 1998-07-09 | いわき電子株式会社 | リードレスパッケージの外部電極構造及びその製造方法 |
| US5375041A (en) * | 1992-12-02 | 1994-12-20 | Intel Corporation | Ra-tab array bump tab tape based I.C. package |
| US5601459A (en) * | 1994-09-29 | 1997-02-11 | North American Specialties Corporation | Solder bearing lead and method of fabrication |
| JP3487524B2 (ja) * | 1994-12-20 | 2004-01-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
| US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
| US5635718A (en) * | 1996-01-16 | 1997-06-03 | Minnesota Mining And Manufacturing Company | Multi-module radiation detecting device and fabrication method |
| JP3462026B2 (ja) * | 1997-01-10 | 2003-11-05 | 岩手東芝エレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP3011233B2 (ja) * | 1997-05-02 | 2000-02-21 | 日本電気株式会社 | 半導体パッケージ及びその半導体実装構造 |
| JPH1126678A (ja) * | 1997-06-30 | 1999-01-29 | Oki Electric Ind Co Ltd | 電子部品のリード構造 |
| KR100514558B1 (ko) * | 1998-09-09 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조방법, 회로기판 및 전자기기 |
| DE19923467B4 (de) * | 1999-05-21 | 2004-11-11 | Infineon Technologies Ag | Halbleitermodul mit mehreren Halbleiterchips und leitender Verbindung mittels flexibler Bänder zwischen den Halbleiterchips |
| JP4102969B2 (ja) * | 1999-08-19 | 2008-06-18 | セイコーエプソン株式会社 | 半導体装置 |
| US6441476B1 (en) * | 2000-10-18 | 2002-08-27 | Seiko Epson Corporation | Flexible tape carrier with external terminals formed on interposers |
| US6444921B1 (en) * | 2000-02-03 | 2002-09-03 | Fujitsu Limited | Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
| US6444576B1 (en) * | 2000-06-16 | 2002-09-03 | Chartered Semiconductor Manufacturing, Ltd. | Three dimensional IC package module |
| JP2002026198A (ja) * | 2000-07-04 | 2002-01-25 | Nec Corp | 半導体装置及びその製造方法 |
| US6940729B2 (en) * | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
| KR100442880B1 (ko) * | 2002-07-24 | 2004-08-02 | 삼성전자주식회사 | 적층형 반도체 모듈 및 그 제조방법 |
| US6924551B2 (en) * | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
-
2003
- 2003-11-03 FR FR0350774A patent/FR2861895B1/fr not_active Expired - Fee Related
-
2004
- 2004-10-28 US US10/577,142 patent/US7569940B2/en not_active Expired - Fee Related
- 2004-10-28 EP EP04805792A patent/EP1680814A2/fr not_active Withdrawn
- 2004-10-28 WO PCT/FR2004/050549 patent/WO2005045934A2/fr not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO2005045934A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005045934A3 (fr) | 2006-03-02 |
| US20070111567A1 (en) | 2007-05-17 |
| WO2005045934A2 (fr) | 2005-05-19 |
| FR2861895B1 (fr) | 2006-02-24 |
| FR2861895A1 (fr) | 2005-05-06 |
| US7569940B2 (en) | 2009-08-04 |
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