EP1615200A2 - Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung - Google Patents

Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung Download PDF

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Publication number
EP1615200A2
EP1615200A2 EP05105568A EP05105568A EP1615200A2 EP 1615200 A2 EP1615200 A2 EP 1615200A2 EP 05105568 A EP05105568 A EP 05105568A EP 05105568 A EP05105568 A EP 05105568A EP 1615200 A2 EP1615200 A2 EP 1615200A2
Authority
EP
European Patent Office
Prior art keywords
addressing
data
frequency
line
loading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05105568A
Other languages
English (en)
French (fr)
Other versions
EP1615200A3 (de
Inventor
Sébastien Weitbruch
Cédric Thébault
Rainer Schweer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
THOMSON LICENSING
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP04291751A external-priority patent/EP1615196A1/de
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Priority to EP05105568A priority Critical patent/EP1615200A3/de
Publication of EP1615200A2 publication Critical patent/EP1615200A2/de
Publication of EP1615200A3 publication Critical patent/EP1615200A3/de
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays

Definitions

  • the present invention relates to a method for driving a display device having a plurality of cells or pixels by loading addressing data into a data driver at a loading frequency and applying an addressing signal to at least one of said plurality of cells or pixels for an addressing time period corresponding to an addressing frequency. Furthermore, the present invention relates to a corresponding device for driving a display device.
  • the Plasma technology makes it possible to achieve flat colour panels of large size and with very limited depth without any viewing angle constraints.
  • the size of the displays may be much larger than the classical CRT picture tubes.
  • a front filter may be applied in front of the panel.
  • One goal of this filter is to suppress the EMI (Electro-Magnetic Interference) using the so-called faraday principle: the filter is a transparent layer covered by a thin grid of metal.
  • the basic assembly of a screen with a filter is illustrated in Figure 2.
  • the panel 1 together with the drivers 2 and the power electronic 3 is arranged in a housing 4 which stops the EMI at the backside of the display device.
  • the front filter 5 in front of the panel 1 stops the EMI emitted from the front side of the panel.
  • this filter 5 has only a reduced transparency with an actual value between 50% and 60% for consumer applications (for professional applications the norm is not so strict and the transparency is better: 65% to 75%).
  • This filtering is really mandatory since if the front filter is removed from a plasma panel, even an IR remote control is not able to work properly. In other words, if the brightness shall be increased as well as the addressing speed also the radiation will be increased, that will require a stronger filter with even less transparency.
  • each line electrode (compare Figure 3) of the PDP will be selected one after the other by respective drivers Line Driver 1, Line Driver 2 etc.
  • binary data information (cell ON or OFF) will be given on all the data electrodes Y (column electrodes) at one time.
  • the column electrodes Y are linked to so-called data drivers Data Driver 1 to Data Driver 27 which act as registers (serial input and parallel output) working at a given data clock (e.g. 40MHz in the present example).
  • the line and data drivers are controlled and driven by PDP controller.
  • the line electrodes X are arranged on a front plate of a PDP and the column electrodes Y on the back plate.
  • 2556 cells have to be written through data drivers.
  • the 36 data outputs that are in excess, will not be connected but will be filled up with zeros (OFF) from the plasma control IC.
  • Figure 5 shows an example of the overall addressing speed for a primed sub-field.
  • the addressing time is lower than 1 ⁇ s per line.
  • the addressing time per line increases rapidly.
  • the curve of the addressing speed can have different behaviours. All the curves presented here are only examples related to a specific technology. In any case, a characterization of the panel speed should be made specifically for each technology and each new process.
  • the object of the present invention is to provide a method and a device for driving a display panel wherein the emitted EMI fulfils the requirement of the respective norms.
  • this object is solved by a method for driving a display device having a plurality of cells or pixels by loading addressing data into data driving means at a loading frequency and applying an addressing signal to at least one of said plurality of cells or pixels for an addressing time period corresponding to an addressing frequency on the basis of said addressing data, wherein said loading frequency of the addressing data is continuously adaptable to said addressing frequency.
  • a device for driving a display device having a plurality of cells or pixels including data driving means for applying an addressing signal to at least one of said plurality of cells or pixels for an addressing time period corresponding to an addressing frequency and controlling means for loading addressing data into said data driving means at a loading frequency, wherein said controlling means is designed to continuously adapt said loading frequency to said addressing frequency.
  • the major advantage of the present invention is that the loading clock of the data drivers may be matched exactly to the addressing duration. Such different clocking broadens the spectrum of the EMI radiation so that the norm limitations can be fulfilled.
  • loading speed and loading frequency are used indifferently for designating loading frequency.
  • addressing speed and addressing frequency are used for designating addressing frequency.
  • the loading frequency may depend on the presence of a priming signal. Since the addressing frequency varies with the presence of the priming signal, also the loading frequency will do so. Thus, the application of a priming signal has to be regarded for controlling the loading frequency.
  • the loading frequency may vary with the line number of the screen of the display device (e.g. vertical panel behaviour). Specifically, since the addressing frequency continuously varies with the line number, also the loading frequency changes continuously so that the EMI spectrum is broadened.
  • the addressing frequency may be changed in dependence on a line number by using a first look up table (LUT).
  • LUT look up table
  • the loading frequency may be changed in dependence on the line number by using a second LUT.
  • LUTs enable a simple handling of signal dependencies.
  • the main idea of the present invention is to adapt the loading speed precisely to the addressing period.
  • a preferred embodiment shall be presented by the way of the example of Figure 5, wherein the sub-fields are primed.
  • the first column represents a line to be addressed
  • the second column the required speed addressing time per line
  • the last one the current data clock to be used at the data driver for the corresponding line.
  • the data clock for the case of a primed sub-field is printed over the line number.
  • the average frequency is 41,21 MHz in this example.
  • the maximal clock is 51,50MHz whereas the minimum one is 21,82MHz.
  • Figure 10 represents a possible implementation of an apparatus for carrying out the method of the present invention.
  • This type of apparatus is already described in PCT application WO 00/46782. It comprises a video degamma circuit 10. RGB data coded with 8 bits are input to this degamma circuit 10. 10 bit-RGB-data output from the video degamma circuit 10 is analyzed on an average power measure block 11 which gives the computed average power value (APL) to a PWE (peak white enhancement) control block 12.
  • the control block 12 consults its internal power level mode table located in a LUT 121 and directly generates the selected mode control signals for the other processing blocks. It selects the sustain table to be used and the sub-field encoding (CODING) table to be used in the sub-field coding block 13 which generates 16 bit output data from the 10 bit input data from the video degamma circuit 10.
  • CODING sub-field encoding
  • the control block 12 also controls the writing of RGB pixel data in a frame memory 14 (WR), the reading of RGB sub-field data from the second frame memory (RD), and the serial to parallel conversion circuit 15 (SP).
  • the converted data are output to a PDP 16.
  • Two frame memories receiving the 16 bit data from the sub-field coding block 13 are required. Data is written pixel-wise, but read sub-field-wise into the conversion circuit 15 (SF-R, SF-G, SF-B). In order to read the complete first sub-field a whole frame must already be present in the memory. In a practical implementation two whole frame memories 14 are present, and while one frame memory is being written, the other is being read, avoiding in this way reading the wrong data. In a cost optimized architecture, the two frame memories 14 are probably located on the same SDRAM memory IC, and access to the two frames is time multiplexed.
  • Figure 11 shows the driver part of Figure 10 in detail. Essentially, the structure is the same as that of Figure 3.
  • the data drivers Data Driver 1, Data Driver 2, ... Data Driver 27 drive the column electrodes Y of the back plate of the PDP and the line drivers Line Driver 1, Line Driver 2 drive the horizontal line electrodes X of the front plate of the PDP.
  • the control block 12 generates the SCAN and SUSTAIN pulses required to drive the PDP driver circuits.
  • the length of the addressing signal (addressing speed) will be taken from a first LUT 122, preferably stored in the control block 12, and in fact for each line of the panel.
  • the information concerning the data driver clock for the data drivers is taken from a second LUT 123 also preferably stored in the control block 12 and used to send the data from serial/parallel conversion 15 and also to control the data driver loading.
  • the data drivers are loaded with a variable clock frequency between 21,82 and 51,50 MHz.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
EP05105568A 2004-07-09 2005-06-22 Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung Ceased EP1615200A3 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05105568A EP1615200A3 (de) 2004-07-09 2005-06-22 Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04291751A EP1615196A1 (de) 2004-07-09 2004-07-09 Verfahren und Vorrichtung zum Steuern eines Anzeigegerätes mit zeilenweiser dynamischer Adressierung
EP05105568A EP1615200A3 (de) 2004-07-09 2005-06-22 Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung

Publications (2)

Publication Number Publication Date
EP1615200A2 true EP1615200A2 (de) 2006-01-11
EP1615200A3 EP1615200A3 (de) 2007-12-19

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EP05105568A Ceased EP1615200A3 (de) 2004-07-09 2005-06-22 Verfahren und Einrichtung zum Steuern eines Plasmaanzeigegerät mit zeilenweise dynamischer Adressierung

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175194B1 (en) * 1999-02-19 2001-01-16 Pioneer Corporation Method for driving a plasma display panel
EP1139324A2 (de) * 2000-03-31 2001-10-04 Fujitsu Limited Anzeigegerät mit verringertem Geräusch und Ansteuerverfahren dafür
US20020044118A1 (en) * 2000-08-29 2002-04-18 Fujitsu Limited Liquid crystal display apparatus and reduction of electromagnetic interference
EP1271463A2 (de) * 2001-06-22 2003-01-02 Pioneer Corporation Verfahren zur Ansteuerung einer Plasmaanzeige

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175194B1 (en) * 1999-02-19 2001-01-16 Pioneer Corporation Method for driving a plasma display panel
EP1139324A2 (de) * 2000-03-31 2001-10-04 Fujitsu Limited Anzeigegerät mit verringertem Geräusch und Ansteuerverfahren dafür
US20020044118A1 (en) * 2000-08-29 2002-04-18 Fujitsu Limited Liquid crystal display apparatus and reduction of electromagnetic interference
EP1271463A2 (de) * 2001-06-22 2003-01-02 Pioneer Corporation Verfahren zur Ansteuerung einer Plasmaanzeige

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