Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/26—Sensing or reading circuits; Data output circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0491—Virtual ground arrays
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/24—Bit-line control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
  • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
  • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

Definitions

• the present invention generally relates to an array of memory cells More specifically, the present invention relates to virtual ground architecture memory arrays
• a memory array includes a number of lines arranged as rows and columns The rows of the array are commonly referred to as word lines and the columns as bit lines, although it is understood that such terminology is relative
• the word lines and bit lines overlap at what can be referred to as nodes Situated at or near each node is a memory cell, which is generally some type of transistor
• a bit line can serve as either a source or drain line for the transistor (memory cell), depending on which memory cell is being program verified or read
• a "read” can refer to either a read operation or a program verification operation
• Flash memory devices use a memory cell transistor with a floating gate structure Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, on a thin insulating film between a substrate and a floating gate Programming of a memory cells occurs by applying a sufficient voltage difference to the transistor to cause excess electrons to accumulate on the floating gate The accumulation of the additional electrons
• a core voltage is applied to the word line corresponding to that cell, and the bit line corresponding to that cell is connected to a load (e g , a cascode or cascode amplifier)
• precharging works by charging (applying an electrical load) to the node next to the node that corresponds to the memory cell being read Specifically, the node next to (and on the same word line) as the dra node of the selected memory cell is precharged If the drain node and the precharge node are at about the same voltage, then the precharge has the effect of reducing the leakage current A problem with precharging is that it is difficult to predict the voltage that needs to be applied to the precharge node.
• a relatively new memory architecture referred to as a mirror bit architecture
• two bits can be stored per memory cell, as opposed to the single bit that is conventionally stored in a memory cell.
• the threshold voltage range that was typically used to distinguish between a "0" and a " 1" has been subdivided into smaller ranges that are assigned multi-bit logical values. For example, a voltage range of 0.00 to 1.00 volts may be used to store a single bit by assigning "1" to 0 volts and "0" to 1 volts.
• the range of 0.00 to 1.00 may be divided into four ranges: 0-0.25, 0.25-0.50, 0.50-.075, and 0.75-1.00. These four ranges would be associated with the logical values "11", “10", “01", and "00".
• multi-bit memory cells provide an increase in information storage capacity, they also increase the accuracy required of the measurements that are used to distinguish between the logical values associated with the state of the memory cell.
• the pattern of bits (e.g., 00, 01, 10 or 11) stored in a multi-bit memory cell can also influence the amount of leakage current. Thus, estimating the proper amount of precharge voltage can be difficult and may be even more difficult for mirror bit architectures.
• an electrical load is applied to a first node (or bit line) in a memory array, the first node corresponding to a memory cell.
• the second node is separated from the first node by at least one intervening node in the same word line.
• a group of memory cells is arranged in a rectangular array having rows (X- dimension) and columns (Y-dimension).
• the sources and drains of the memory cells are coupled to form a linear chain.
• a common word line is coupled to each gate in the row.
• a separate column line is coupled to each node between adjacent memory cells of the chain.
• a four column Y-decoder is used to select column lines for sense operations.
• a voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.
• Figure 1A shows a schematic of a multi-bit memory cell according to one embodiment of the present invention.
• Figure IB shows a threshold voltage distribution associated with the logic states of the multi-bit memory cell of Figure 1A.
• Figure 2A shows a drain-source series of memory cells with column lines in accordance with an embodiment of the present invention.
• Figure 2B shows an equivalent circuit representation of the parasitic capacitances and resistances associated with the sense operation of a memory cell in a drain-source series.
• Figure 3A shows a four column selection for a sense operation in accordance with an embodiment of the present invention.
• Figure 3B shows a four column selection for a read operation in accordance with an embodiment of the present invention.
• Figure 3C shows a four column selection for a verify operation in accordance with an embodiment of the present invention.
• Figure 4 shows a memory cell array sector layout with reference and redundancy blocks operation in accordance with an embodiment of the present invention.
• Figure 5 A shows a source selector for one column of a four column Y-decoder in accordance with an embodiment of the present invention.
• Figure 5B shows a metal bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention.
• Figure 5C shows a diffusion bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention.
• Figure 6 is a flowchart for a four column sense operation in accordance with an embodiment of the present invention.
• Figure 7 is a representation of a portion of a memory array according to one embodiment of the present invention.
• Figure 8 A is a representation of an exemplary memory cell according to one embodiment of the present invention.
• Figure 8B is a representation of an exemplary mirror bit memory cell according to one embodiment of the present invention.
• Figure 9A illustrates one embodiment of a precharge scheme according to the present invention.
• Figure 9B illustrates another embodiment of a precharge scheme according to the present invention.
• Figure 10 is a flowchart of a method of reading a memory cell according to one embodiment of the present invention.
• Figure 1A shows a schematic of a multi-bit memory cell 100 having a gate 105, source 115, and a drain 110.
• the memory cell stores a left bit 125 (X L ) and a right bit 120 (X R ).
• the source 115 is coupled to ground and a voltage source is applied to the drain 110, while a voltage is applied to the gate 105.
• Figure IB shows schematic threshold voltage distributions 150, 155, 160, and 165 associated with the logic states " 11", “10", “01”, and “11", respectively, of the multi-bit memory cell 100 of Figure 1A.
• the X-axis (V-) represents the threshold voltage and the Y-axis (N) represents the number of memory cells having a particular threshold voltage.
• the increased number of partitions applied to the operating voltage range increase the requirement for sensing accuracy in order to distinguish between logic states of the cell.
• Figure 2A shows a drain-source series 210 having 16 memory cells (0-15) and 17 column lines (CL00- CL16).
• the gates of the memory cells in the series are connected to a common word line 205.
• the drain of each memory cell is connected to the source of one of its adjacent memory cells, and source of each memory cell is connected to the drain of the other of its adjacent memory cells.
• the drain-source series is a portion of a row of memory cells in an array that typically has dummy memory cells (not shown) that are used to provide proper loading at the start and end of a row, but are not accessed for storage
• Column lines CL00-CL16 are each coupled to a drain-source node between adjacent memory cells
• Figure 2B shows an equivalent circuit representation of the parasitic capacitances and resistances associated with the sense operation of a memory cell in the drain-source series 210 of Figure 2A
• memory cell 1 has its source coupled to ground and a voltage V D applied to its drain
• the adjacent memory cells in the drain-source series present an RC network that is dependent upon the state of the adjacent memory cells and the physical structure of the memory cells and their interconnects Shunt capacitances 240 and series resistances 245 are shown
• Shunt capacitances 240 and series resistances 245 are shown
• the memory cell being sensed also has a resistance 235
• ⁇ 2 In order to determine the state of cell 1 current ⁇ 2 must be sensed This is typically done by sensing the current ii provided by the voltage source V D
• the parasitic resistances and capacitances result in error currents ⁇ and ⁇ 5
• the error currents may be transient currents associated with the charging of capacitances, or they may be steady state currents associated with resistances
• Figure 3A shows a four column selection for a sense operation on memory cell 1 in accordance with an embodiment of the present invention
• the two column lines adjacent to memory cell 1 are selected (CLSi, CLS 2 ) as well as two additional columns (CLS 3 , CLS 4 )
• CLSi and CLS 2 are used to provide the basic sensing current for memory cell 1
• CLS 3 and CLS 4 are used in conjunction with a voltage source to reduce the error current ⁇ 4 of Figure 2B
• Figure 3B shows a four column selection and voltage source coupling for a read operation in accordance with an embodiment of the present invention
• CLS* of Figure 3 A is coupled to ground and CLS 2 is coupled to a voltage source V !
• CLS 3 is coupled to a voltage source V 2 and CLS 4 is allowed to float
• Voltage source V* is preferably in the range of 1 2 to 1 4 volts
• Voltage source V 2 has the same value as voltage source Vi and is also preferably in the range of 1 2 to 1 4 volts
• voltage source V has the same value as voltage source Vi and is also preferably in the range of 1 2 to 1 4 volts
• V ! has an associated sense amplifier that enables measurement of the current from source V*
• voltage source V ! and voltage source V 2 are one and the same, with the current sensor being associated with the connection path to selected column line CLS 2
• the current sensor being associated with the connection path to selected column line CLS 2
• a single voltage source having two branches is used, with a current sensor being associated with one branch Since V 2 is applied to the column line adjacent to the column line to which V !
• V 2 is able to mask the parasitic elements associated with the remainder of the drain-source series of memory cells
• V* allows for rapid charging of parasitic capacitances, and thus reduces the time required to perform a read operation
• the fourth selected column line CLS is allowed to float
• a further improvement in speed may be obtained by coupling CLS to V 2 in addition to CLS 3
• Figure 3C shows a four column selection for a verify operation in accordance with an embodiment of the present invention
• CLS] of Figure 3 A is coupled to ground and CLS 2 is coupled to a voltage source V*
• CLS is coupled to a voltage source V 2 and CLS 3 is allowed to float
• Voltage source V* is preferably in the range of 1.2 to 1.4 volts.
• Voltage source V 2 has the same value as voltage source V* and is also preferably in the range of 1.2 to 1.4 volts.
• V* and V 2 are not applied to adjacent column lines. This is due to the greater emphasis on accuracy (as opposed to speed) for a verify operation. In practice there may be a small difference between the values of V ! and V 2 that will produce a small steady state error current. For a read operation, such a current may be ignored since the transient error currents are the primary concern.
• V 2 By applying V 2 to CLS and allowing CLS 3 to float, a greater effective resistance is obtained between V* and V 2 , thereby reducing any error current that by be produced by a difference between V* and V 2 .
• Figure 4 shows an example of a memory cell array sector layout 400.
• a sector 405 comprises I O blocks I/O0-I/O15 that form the core memory array, reference blocks 415 and 420, and a redundancy block 425. As shown, the redundancy block may be physically separate from the remainder of the sector.
• Each I/O block 410 comprises 4 sub-I/Os 430, each with a width of 16 cells. Each sub-I/0 (wO, wl, w2, w3) has an associated word number (00, 01, 10, 11). Thus, for a word length of 16 cells, each I/O block is four words (or 64 cells) wide.
• the reference blocks 415 and 420, and the Redundancy block 425 are each 16 cells wide.
• the basic unit of width for the sector 405 is 16 cells, and a common decoder structure with an addressable width of 16 cells may be used to address each block.
• the total number of decoders required is 67, with 64 decoders for the 16 I/O blocks I/O0-I O15, 2 decoders for the reference blocks 415 and 420, and one decoder for the redundancy block 425.
• the sector 405 has an overall width of 1072 cells, and may have a height of about half of the width, e.g., 512 cells high.
• Figure 5 A shows a source selector for one column of a four column Y-decoder in accordance with an embodiment of the present invention.
• a transistor switched ground 501 is controlled by an input BSG(n). When BSG(n) is asserted, the output YBL(n) of the selector is coupled to ground.
• a first voltage source 502 is controlled by an input BSD(n). When BSD(n) is asserted, the output YBL(n) is coupled to the first voltage source.
• a second voltage source 502 is controlled by an input BSP(n). When BSP(n) is asserted, the output
• YBL(n) is coupled to the second voltage source.
• BSG(n), BSD(n), and BSP(n) are all low, the output YBL(n) is allowed to float.
• Figure 5B shows a metal bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention.
• YBL(0),YBL(1),YBL(2), and YBL(3) are coupled to the output of a source selector YBL(n) as shown in Figure 5A, and branch into two switched metal bit line legs that are controlled by selector CS(7:0).
• Eight metal bit lines MBL(0)-MBL(7) are controlled by the selector CS(7:0).
• Figure 5C shows a diffusion bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention. This portion is coupled to one half of the outputs of Figure 5B, with a similar portion being coupled to the other half.
• Each of the metal bit lines MBL(0)-MBL(3) is terminated by two switched diffusion bit lines and is coupled to a drain-source node on the drain source series 505.
• Each of inputs SEL(0)-SEL(7) controls diffusion bit lines (column lines) 520-527.
• the combination of the components shown in Figures 5 A, 5B, and 5C provide a four-column Y-decoder that may be used to select four columns out of a sub I/O that is 16 memory cells wide.
• Figure 6 shows a flowchart for a four column sense operation performed on a drain-source series of memory cells in accordance with an embodiment of the present invention
• a first column line associated with a memory cell is selected and coupled to ground This column line is generally the source of the memory cell
• a second column line is selected and coupled to a first voltage source
• the second column line is generally coupled to the drain of the memory cell
• a third column line is selected and coupled to a second voltage source, and may or may not be adjacent to the second column line
• a fourth column line is selected and allowed to float
• the fourth column line may or may not be adjacent to the second column line
• the third column line be adjacent to the second column line
• a verify operation it is preferred that the fourth column line be adjacent to the second column line
• the current from the first voltage source is sensed
• Figure 7 is a representation of a portion of a memory array 700 according to one embodiment of the present invention
• a single word line 740 and a number of bit lines 730, 731 and 732 are illustrated
• memory array 700 will in actuality extend further to the left and right and also horizontally and vertically (left, right, horizontal and vertical being relative directions)
• memory array 700 utilizes a virtual ground architecture
• a bit line can serve as either a source or drain, depending on the memory cell being read (or program verified)
• Couplable to word line 740 is a power supply (voltage source 760), while couplable to each bit line 730-732 is a load (exemplified by cascode 750)
• the bit lines 730-732 are substantially parallel to each other, and word line 740 is substantially orthogonal to the bit lines
• the word line 740 and the bit lines 730-732 overlap at a number of nodes 710, 711 and 712, respectively
• a memory cell 720, 721 and 722 Corresponding to each of these nodes is a memory cell 720, 721 and 722 That is, in this embodiment, memory cell 720 corresponds to node 710, memory cell 721 corresponds to node 711, and memory cell 722 corresponds to node 712 Also illustrated is a memory cell 723, corresponding to another node (not shown)
• the memory cells 720-723 may be a single bit memory cell such as memory cell 800 of Figure 8A, or a mirror bit memory cell such as memory cell 850 of Figure 8B
• FIG 8A is a representation of an exemplary memory cell 800 according to one embodiment of the present invention
• memory cell 800 is a floating gate memory cell that includes a substrate 810 in which source and drain regions are formed
• memory cell 800 also includes a first oxide layer 820a, a storage element 830 (e g , a floating gate), a second oxide layer 820b, and a control gate 840
• storage element 830 is used for storing a single bit Memory cells such as memory cell 800 are known in the art
• FIG. 8B is a representation of an exemplary mirror bit memory cell 850 according to one embodiment of the present invention
• memory cell 850 includes a substrate 860, a first oxide layer 870a, a storage element 880 (e g a floating gate), a second oxide layer 870b, and a control gate 890.
• memory cell 850 is based on a symmetric transistor with similar (selectable) source and drain.
• mirror bit memory cell 850 is configured to allow a bit to be stored on either or both sides of storage element 880. Specifically, once electrons are stored on one side of storage element 880, they remain on that side and do not migrate to the other side of the storage element. Thus, in the present embodiment, two bits can be stored per memory cell.
• Figure 9A illustrates one embodiment of a precharge scheme according to the present invention.
• a bit line e.g., bit line 732 that is at least one bit line removed from the drain bit line (e.g., bit line 730) is precharged. That is, according to the present embodiment of the present invention, there is at least one intervening bit line (e.g., bit line 731) between the drain bit line and the precharge bit line.
• bit line 731 intervening bit line
• bit line 729 serves as the source bit line and bit line 730 serves as the drain bit line.
• An electrical load e.g., a cascode
• bit line 732 which is separated from bit line 730 (node 710) by at least one intervening bit line (or node), is precharged.
• the precharge voltage is in the range of approximately 1.2 to 1.4 volts; however, other precharge voltages may be used. For example, precharge voltages of 1.5 volts are contemplated. In general, the precharge voltage is matched as closely as practical to the electrical load on the drain node (e.g., node 710). Other factors that can influence the amount of the precharge voltage include the sensing scheme to be implemented and the effect of the sensing scheme on the design of the cascode and other peripheral circuits.
• a bit line further removed from bit line 730 can be precharged.
• a bit line separated from bit line 730 by more than one (e.g., by two or more) bit lines or nodes can be precharged as an alternative to precharging bit line 732. It is recognized that there is a limitation to how far the precharge bit line may be from the drain bit line. There are at least two factors to consider when selecting the distance between the drain bit line and the precharge bit line. One factor to consider is that, as the precharge bit line is moved further from the drain bit line, the effect of the precharge bit line on the selected node will be reduced. Thus, precharging a bit line too distant from the selected mode may not have a significant enough effect on the leakage current.
• the other factor to consider is the architecture of the memory array.
• memory cells are read (decoded) in groups of four. This can place a limitation on the distance between the drain bit line and the precharge bit line. Based on these factors, distances of up to five bit lines (nodes) between the precharge bit line and the drain bit line are contemplated. However, it is appreciated that application of the features of the present invention, in all of its embodiments, is not limited to a distance of five bit lines (nodes) between drain and precharge bit lines.
• Figure 9B illustrates another embodiment of a precharge scheme according to the present invention.
• multiple bit lines e.g., bit lines 731 and 732
• nodes e.g., nodes 711 and 712
• at least one of the precharge bit lines is separated from the drain bit line by an intervening bit line (node)
• bit lines on each side of the selected node may be precharged.
• the same precharge voltage is applied to each bit line
• different precharge voltages may be applied to one or more of the precharge bit lines
• Figure 10 is a flowchart 1000 of a method of reading (or program verifying) a memory cell according to one embodiment of the present invention
• steps in flowchart 1000 may be performed in an order different than presented and that the steps in flowchart 1000 are not necessarily performed in the sequence illustrated
• steps 1010 and 1020 of flowchart 1000 are performed substantially at the same time, although they may be performed at different times
• step 1010 an electrical load is applied to a first node or bit line (e g , the drain bit line) corresponding to a selected memory cell to be read (or program verified) This load may be applied using a cascode
• a precharge is applied to at least one other (a second) node or bit line on the same word line as the first node or bit line
• the second node or bit line is separated from the first node or bit line by at least one intervening node on the same word line, or at least one bit line in the memory array
• more than one bit line (node) may be precharged using a variety of precharge schemes, and the precharge voltage may be the same or different for each of the precharge bit lines (nodes) By precharging a bit line or node that is separated from the selected memory cell by at least one intervening bit line or node, the amount of leakage current is reduced
• embodiments of the present invention provide a method and device thereof that can reduce and potentially minimize the amount of leakage current between memory

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