WO2004019341A1

WO2004019341A1 - Column-decoding and precharging in a flash memory device

Info

Publication number: WO2004019341A1
Application number: PCT/US2003/018450
Authority: WO
Inventors: Tien-Chung Yang; Ming-Huei Shieh; Kazuhiro Kurihara; Pau-Ling Chen; Keith Wong; Michael S. Chung
Original assignee: Fasl Llc
Priority date: 2002-08-22
Filing date: 2003-06-10
Publication date: 2004-03-04
Also published as: EP1588378A1; JP2005537597A; AU2003245450A8; KR100973788B1; KR20060076758A; TWI326878B; AU2003245450A1; TW200404297A

Abstract

Methods of reading a memory cell, and memory arrays that use these methods, are described. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. For precharging, an electrical load is applied to a first node in a memory array. A second node, separated from the first node by at least one intervening node in the same word line in the memory array, is precharged.

Description

COLUMN-DECODING AND PRECHARGING IN A FLASH MEMORY DEVICE.

TECHNICAL FIELD

The present invention generally relates to an array of memory cells More specifically, the present invention relates to virtual ground architecture memory arrays

BACKGROUND ART

The architecture of a typical memory array is known in the art Generally, a memory array includes a number of lines arranged as rows and columns The rows of the array are commonly referred to as word lines and the columns as bit lines, although it is understood that such terminology is relative The word lines and bit lines overlap at what can be referred to as nodes Situated at or near each node is a memory cell, which is generally some type of transistor In a virtual ground architecture, a bit line can serve as either a source or drain line for the transistor (memory cell), depending on which memory cell is being program verified or read For simplicity of discussion, a "read" can refer to either a read operation or a program verification operation Flash memory devices use a memory cell transistor with a floating gate structure Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, on a thin insulating film between a substrate and a floating gate Programming of a memory cells occurs by applying a sufficient voltage difference to the transistor to cause excess electrons to accumulate on the floating gate The accumulation of the additional electrons on the floating gate raises the charge on the gate and the transistor's threshold voltage The transistor's threshold voltage is raised sufficiently above that of the applied voltage during read cycles so that the transistor does not turn on during the read cycles Therefore, a programmed memory cell will not carry current, representing the logical value "0 " The erasure of a sector of data is caused by a process in which a voltage difference is applied to the transistor in each memory cell of the sector to cause the excess electrons on the floating gate in each transistor to evacuate the insulating film Accordingly, the transistor's threshold voltage is lowered below that of the voltage potential applied to the transistor to read data In the erased state, current will flow through the transistor When the read voltage potential is applied, the current will flow through the transistor of the memory cell, representing a logical value " 1 " stored in the memory cell

When reading a selected memory cell, a core voltage is applied to the word line corresponding to that cell, and the bit line corresponding to that cell is connected to a load (e g , a cascode or cascode amplifier)

Because of the architecture of the memory array, all of the memory cells on the word line are subject to the core voltage This can induce a leakage current along the word line, in effect causing an unwanted interaction between the memory cells on the word line The leakage current, if of sufficient magnitude, can slow down the read and also cause errors in reading the selected memory cell To minimize the interaction among memory cells on a word line and to speed up the read, a technique commonly referred to as precharging is used Precharging works by charging (applying an electrical load) to the node next to the node that corresponds to the memory cell being read Specifically, the node next to (and on the same word line) as the dra node of the selected memory cell is precharged If the drain node and the precharge node are at about the same voltage, then the precharge has the effect of reducing the leakage current A problem with precharging is that it is difficult to predict the voltage that needs to be applied to the precharge node. It is important to apply an appropriate precharge voltage because, if the precharge voltage is set too high or too low, the memory cell may not be properly read. However, there are many factors that can influence the amount of leakage current and hence the amount of voltage that should be applied to the precharge node. These factors include variations in temperature and in the supply voltage.

In addition, a relatively new memory architecture, referred to as a mirror bit architecture, is coming into use. In a contemporary mirror bit architecture, two bits can be stored per memory cell, as opposed to the single bit that is conventionally stored in a memory cell. With the advent of multi-bit memory cells, the threshold voltage range that was typically used to distinguish between a "0" and a " 1" has been subdivided into smaller ranges that are assigned multi-bit logical values. For example, a voltage range of 0.00 to 1.00 volts may be used to store a single bit by assigning "1" to 0 volts and "0" to 1 volts. Alternatively, the range of 0.00 to 1.00 may be divided into four ranges: 0-0.25, 0.25-0.50, 0.50-.075, and 0.75-1.00. These four ranges would be associated with the logical values "11", "10", "01", and "00". Although multi-bit memory cells provide an increase in information storage capacity, they also increase the accuracy required of the measurements that are used to distinguish between the logical values associated with the state of the memory cell. In addition, the pattern of bits (e.g., 00, 01, 10 or 11) stored in a multi-bit memory cell can also influence the amount of leakage current. Thus, estimating the proper amount of precharge voltage can be difficult and may be even more difficult for mirror bit architectures.

DISCLOSURE OF THE INVENTION

Methods of reading a memory cell, and memory arrays that use these methods, are described in various embodiments. In one embodiment, an electrical load is applied to a first node (or bit line) in a memory array, the first node corresponding to a memory cell. A second node (or bit line) in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.

In another embodiment, a group of memory cells is arranged in a rectangular array having rows (X- dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

BRIEF DESCRIPTION OF DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:

Figure 1A shows a schematic of a multi-bit memory cell according to one embodiment of the present invention. Figure IB shows a threshold voltage distribution associated with the logic states of the multi-bit memory cell of Figure 1A.

Figure 2A shows a drain-source series of memory cells with column lines in accordance with an embodiment of the present invention. . Figure 2B shows an equivalent circuit representation of the parasitic capacitances and resistances associated with the sense operation of a memory cell in a drain-source series.

Figure 3A shows a four column selection for a sense operation in accordance with an embodiment of the present invention.

Figure 3B shows a four column selection for a read operation in accordance with an embodiment of the present invention.

Figure 3C shows a four column selection for a verify operation in accordance with an embodiment of the present invention.

Figure 4 shows a memory cell array sector layout with reference and redundancy blocks operation in accordance with an embodiment of the present invention. Figure 5 A shows a source selector for one column of a four column Y-decoder in accordance with an embodiment of the present invention.

Figure 5B shows a metal bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention.

Figure 5C shows a diffusion bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention.

Figure 6 is a flowchart for a four column sense operation in accordance with an embodiment of the present invention.

Figure 7 is a representation of a portion of a memory array according to one embodiment of the present invention. Figure 8 A is a representation of an exemplary memory cell according to one embodiment of the present invention.

Figure 8B is a representation of an exemplary mirror bit memory cell according to one embodiment of the present invention.

Figure 9A illustrates one embodiment of a precharge scheme according to the present invention. Figure 9B illustrates another embodiment of a precharge scheme according to the present invention.

Figure 10 is a flowchart of a method of reading a memory cell according to one embodiment of the present invention.

The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.

MODES FOR CARRYING OUT THE INVENTION

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

Some portions of the detailed descriptions which follow are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as "selecting," "sensing," "applying," "precharging" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

SYSTEM AND METHOD FOR Y-DECODING

Figure 1A shows a schematic of a multi-bit memory cell 100 having a gate 105, source 115, and a drain 110. The memory cell stores a left bit 125 (X_L) and a right bit 120 (X_R). In sensing the state of the bits in the memory cell, the source 115 is coupled to ground and a voltage source is applied to the drain 110, while a voltage is applied to the gate 105.

Figure IB shows schematic threshold voltage distributions 150, 155, 160, and 165 associated with the logic states " 11", "10", "01", and "11", respectively, of the multi-bit memory cell 100 of Figure 1A. The X-axis (V-) represents the threshold voltage and the Y-axis (N) represents the number of memory cells having a particular threshold voltage. In a multi-bit memory cell, the increased number of partitions applied to the operating voltage range increase the requirement for sensing accuracy in order to distinguish between logic states of the cell.

Figure 2A shows a drain-source series 210 having 16 memory cells (0-15) and 17 column lines (CL00- CL16). The gates of the memory cells in the series are connected to a common word line 205. The drain of each memory cell is connected to the source of one of its adjacent memory cells, and source of each memory cell is connected to the drain of the other of its adjacent memory cells. The drain-source series is a portion of a row of memory cells in an array that typically has dummy memory cells (not shown) that are used to provide proper loading at the start and end of a row, but are not accessed for storage Column lines CL00-CL16 are each coupled to a drain-source node between adjacent memory cells

Figure 2B shows an equivalent circuit representation of the parasitic capacitances and resistances associated with the sense operation of a memory cell in the drain-source series 210 of Figure 2A In this example, memory cell 1 has its source coupled to ground and a voltage V_D applied to its drain The adjacent memory cells in the drain-source series present an RC network that is dependent upon the state of the adjacent memory cells and the physical structure of the memory cells and their interconnects Shunt capacitances 240 and series resistances 245 are shown In practice, there will be finite values for shunt resistance and series capacitance as well The memory cell being sensed also has a resistance 235 In order to determine the state of cell 1 current ι₂ must be sensed This is typically done by sensing the current ii provided by the voltage source V_D As can be seen from Figure 2B, the parasitic resistances and capacitances result in error currents ι and ι₅ The error currents may be transient currents associated with the charging of capacitances, or they may be steady state currents associated with resistances In general, ι is of greater concern than ι₅ since the grounded source S has a very small path resistance in comparison to the current path for ι₅

Figure 3A shows a four column selection for a sense operation on memory cell 1 in accordance with an embodiment of the present invention For either a read or verify operation on memory cell 1, the two column lines adjacent to memory cell 1 are selected (CLSi, CLS₂) as well as two additional columns (CLS₃, CLS₄) CLSi and CLS₂ are used to provide the basic sensing current for memory cell 1, and CLS₃ and CLS₄ are used in conjunction with a voltage source to reduce the error current ι₄ of Figure 2B

Figure 3B shows a four column selection and voltage source coupling for a read operation in accordance with an embodiment of the present invention For a read operation, CLS* of Figure 3 A is coupled to ground and CLS₂ is coupled to a voltage source V_! CLS₃ is coupled to a voltage source V₂ and CLS₄ is allowed to float Voltage source V* is preferably in the range of 1 2 to 1 4 volts Voltage source V₂ has the same value as voltage source Vi and is also preferably in the range of 1 2 to 1 4 volts Typically, voltage source

V_! has an associated sense amplifier that enables measurement of the current from source V*

In one embodiment of the present invention, voltage source V_! and voltage source V₂ are one and the same, with the current sensor being associated with the connection path to selected column line CLS₂ Thus, a single voltage source having two branches is used, with a current sensor being associated with one branch Since V₂ is applied to the column line adjacent to the column line to which V_! is applied, with only one intervening memory cell (2), V₂ is able to mask the parasitic elements associated with the remainder of the drain-source series of memory cells The application of V₂ in addition to V* allows for rapid charging of parasitic capacitances, and thus reduces the time required to perform a read operation Generally, during a read operation, the fourth selected column line CLS is allowed to float However, a further improvement in speed may be obtained by coupling CLS to V₂ in addition to CLS₃

Figure 3C shows a four column selection for a verify operation in accordance with an embodiment of the present invention For a verify operation, CLS] of Figure 3 A is coupled to ground and CLS₂ is coupled to a voltage source V* CLS is coupled to a voltage source V₂ and CLS₃ is allowed to float Voltage source V* is preferably in the range of 1.2 to 1.4 volts. Voltage source V₂ has the same value as voltage source V* and is also preferably in the range of 1.2 to 1.4 volts.

In contrast to the read operation previously described, for a verify operation, V* and V₂ are not applied to adjacent column lines. This is due to the greater emphasis on accuracy (as opposed to speed) for a verify operation. In practice there may be a small difference between the values of V_! and V₂ that will produce a small steady state error current. For a read operation, such a current may be ignored since the transient error currents are the primary concern. By applying V₂ to CLS and allowing CLS₃ to float, a greater effective resistance is obtained between V* and V₂, thereby reducing any error current that by be produced by a difference between V* and V₂. Figure 4 shows an example of a memory cell array sector layout 400. A sector 405 comprises I O blocks I/O0-I/O15 that form the core memory array, reference blocks 415 and 420, and a redundancy block 425. As shown, the redundancy block may be physically separate from the remainder of the sector. Each I/O block 410 comprises 4 sub-I/Os 430, each with a width of 16 cells. Each sub-I/0 (wO, wl, w2, w3) has an associated word number (00, 01, 10, 11). Thus, for a word length of 16 cells, each I/O block is four words (or 64 cells) wide. The reference blocks 415 and 420, and the Redundancy block 425 are each 16 cells wide.

Thus, the basic unit of width for the sector 405 is 16 cells, and a common decoder structure with an addressable width of 16 cells may be used to address each block. The total number of decoders required is 67, with 64 decoders for the 16 I/O blocks I/O0-I O15, 2 decoders for the reference blocks 415 and 420, and one decoder for the redundancy block 425. The sector 405 has an overall width of 1072 cells, and may have a height of about half of the width, e.g., 512 cells high.

Figure 5 A shows a source selector for one column of a four column Y-decoder in accordance with an embodiment of the present invention. A transistor switched ground 501 is controlled by an input BSG(n). When BSG(n) is asserted, the output YBL(n) of the selector is coupled to ground. A first voltage source 502 is controlled by an input BSD(n). When BSD(n) is asserted, the output YBL(n) is coupled to the first voltage source. A second voltage source 502 is controlled by an input BSP(n). When BSP(n) is asserted, the output

YBL(n) is coupled to the second voltage source. When BSG(n), BSD(n), and BSP(n) are all low, the output YBL(n) is allowed to float.

Figure 5B shows a metal bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention. YBL(0),YBL(1),YBL(2), and YBL(3) are coupled to the output of a source selector YBL(n) as shown in Figure 5A, and branch into two switched metal bit line legs that are controlled by selector CS(7:0). Eight metal bit lines MBL(0)-MBL(7) are controlled by the selector CS(7:0). Figure 5C shows a diffusion bit line selection portion of a four column Y-decoder in accordance with an embodiment of the present invention. This portion is coupled to one half of the outputs of Figure 5B, with a similar portion being coupled to the other half. Each of the metal bit lines MBL(0)-MBL(3) is terminated by two switched diffusion bit lines and is coupled to a drain-source node on the drain source series 505. Each of inputs SEL(0)-SEL(7) controls diffusion bit lines (column lines) 520-527. The combination of the components shown in Figures 5 A, 5B, and 5C provide a four-column Y-decoder that may be used to select four columns out of a sub I/O that is 16 memory cells wide. Figure 6 shows a flowchart for a four column sense operation performed on a drain-source series of memory cells in accordance with an embodiment of the present invention In step 605, a first column line associated with a memory cell is selected and coupled to ground This column line is generally the source of the memory cell In step 610, a second column line is selected and coupled to a first voltage source The second column line is generally coupled to the drain of the memory cell In step 615, a third column line is selected and coupled to a second voltage source, and may or may not be adjacent to the second column line In step 620, a fourth column line is selected and allowed to float The fourth column line may or may not be adjacent to the second column line For a read operation it is preferred that the third column line be adjacent to the second column line, and for a verify operation it is preferred that the fourth column line be adjacent to the second column line In step 625, the current from the first voltage source is sensed

A PRECHARGING SCHEME FOR READING A MEMORY CELL

Figure 7 is a representation of a portion of a memory array 700 according to one embodiment of the present invention In Figure 7, for simplicity of discussion and illustration, a single word line 740 and a number of bit lines 730, 731 and 732 are illustrated However, it is understood that a memory array may actually utilize a different number of word lines and bit lines That is, memory array 700 will in actuality extend further to the left and right and also horizontally and vertically (left, right, horizontal and vertical being relative directions) It is also understood that only certain elements of a memory array are illustrated, that is, a memory array may actually include elements other than those shown For example, in one embodiment, memory array 700 utilizes a virtual ground architecture In a virtual ground architecture, a bit line can serve as either a source or drain, depending on the memory cell being read (or program verified)

Couplable to word line 740 is a power supply (voltage source 760), while couplable to each bit line 730-732 is a load (exemplified by cascode 750) The bit lines 730-732 are substantially parallel to each other, and word line 740 is substantially orthogonal to the bit lines The word line 740 and the bit lines 730-732 overlap at a number of nodes 710, 711 and 712, respectively Corresponding to each of these nodes is a memory cell 720, 721 and 722 That is, in this embodiment, memory cell 720 corresponds to node 710, memory cell 721 corresponds to node 711, and memory cell 722 corresponds to node 712 Also illustrated is a memory cell 723, corresponding to another node (not shown) The memory cells 720-723 may be a single bit memory cell such as memory cell 800 of Figure 8A, or a mirror bit memory cell such as memory cell 850 of Figure 8B

Figure 8A is a representation of an exemplary memory cell 800 according to one embodiment of the present invention In this embodiment, memory cell 800 is a floating gate memory cell that includes a substrate 810 in which source and drain regions are formed Typically, memory cell 800 also includes a first oxide layer 820a, a storage element 830 (e g , a floating gate), a second oxide layer 820b, and a control gate 840 In this embodiment, storage element 830 is used for storing a single bit Memory cells such as memory cell 800 are known in the art

Figure 8B is a representation of an exemplary mirror bit memory cell 850 according to one embodiment of the present invention In this embodiment, memory cell 850 includes a substrate 860, a first oxide layer 870a, a storage element 880 (e g a floating gate), a second oxide layer 870b, and a control gate 890. Unlike memory cell 800 of Figure 8A, which is based on an asymmetric transistor with a distinct source and a distinct drain, memory cell 850 is based on a symmetric transistor with similar (selectable) source and drain. Also, mirror bit memory cell 850 is configured to allow a bit to be stored on either or both sides of storage element 880. Specifically, once electrons are stored on one side of storage element 880, they remain on that side and do not migrate to the other side of the storage element. Thus, in the present embodiment, two bits can be stored per memory cell.

Figure 9A illustrates one embodiment of a precharge scheme according to the present invention. In this embodiment, a bit line (e.g., bit line 732) that is at least one bit line removed from the drain bit line (e.g., bit line 730) is precharged. That is, according to the present embodiment of the present invention, there is at least one intervening bit line (e.g., bit line 731) between the drain bit line and the precharge bit line. It is appreciated that, although the precharge bit line is illustrated as being in one direction relative to the drain bit line, the precharge bit line may be in either direction along word line 740.

The precharge scheme of Figure 9A is implemented as follows for a read or for program verification of a selected memory cell (e.g., memory cell 720). (For simplicity of discussion herein, a read can refer to either a read operation or a program verification operation.) For a read of memory cell 720, bit line 729 serves as the source bit line and bit line 730 serves as the drain bit line. An electrical load (e.g., a cascode) is applied to node 710 (bit line 730) corresponding to memory cell 720. To reduce leakage current, bit line 732, which is separated from bit line 730 (node 710) by at least one intervening bit line (or node), is precharged. In one embodiment, the precharge voltage is in the range of approximately 1.2 to 1.4 volts; however, other precharge voltages may be used. For example, precharge voltages of 1.5 volts are contemplated. In general, the precharge voltage is matched as closely as practical to the electrical load on the drain node (e.g., node 710). Other factors that can influence the amount of the precharge voltage include the sensing scheme to be implemented and the effect of the sensing scheme on the design of the cascode and other peripheral circuits.

In other embodiments, a bit line further removed from bit line 730 can be precharged. In other words, a bit line separated from bit line 730 by more than one (e.g., by two or more) bit lines or nodes can be precharged as an alternative to precharging bit line 732. It is recognized that there is a limitation to how far the precharge bit line may be from the drain bit line. There are at least two factors to consider when selecting the distance between the drain bit line and the precharge bit line. One factor to consider is that, as the precharge bit line is moved further from the drain bit line, the effect of the precharge bit line on the selected node will be reduced. Thus, precharging a bit line too distant from the selected mode may not have a significant enough effect on the leakage current. The other factor to consider is the architecture of the memory array. For example, in a mirror bit architecture, memory cells are read (decoded) in groups of four. This can place a limitation on the distance between the drain bit line and the precharge bit line. Based on these factors, distances of up to five bit lines (nodes) between the precharge bit line and the drain bit line are contemplated. However, it is appreciated that application of the features of the present invention, in all of its embodiments, is not limited to a distance of five bit lines (nodes) between drain and precharge bit lines.

Figure 9B illustrates another embodiment of a precharge scheme according to the present invention. In this embodiment, multiple bit lines (e.g., bit lines 731 and 732) or nodes (e.g., nodes 711 and 712) are precharged. Note that, in a broad sense, at least one of the precharge bit lines is separated from the drain bit line by an intervening bit line (node)

In alternative embodiments, other precharge schemes may be used For example, more than two bit lines may be precharged Also, non-consecutive bit lines may be precharged Furthermore, when multiple bit lines are precharged, each of the precharge bit lines may be separated from the selected node by one or more intervening nodes or bit lines In addition, with multiple precharge bit lines, bit lines on each side of the selected node may be precharged Again, in a broad sense, at least one of the precharge bit lines is separated from the selected node by an intervening node (or bit line)

In one embodiment in which multiple bit lines are precharged, the same precharge voltage is applied to each bit line In another such embodiment, different precharge voltages may be applied to one or more of the precharge bit lines

Figure 10 is a flowchart 1000 of a method of reading (or program verifying) a memory cell according to one embodiment of the present invention Although specific steps are disclosed in flowchart 1000, such steps are exemplary That is, the present invention is well suited to performing various other steps or variations of the steps recited in flowchart 1000 It is appreciated that the steps in flowchart 1000 may be performed in an order different than presented and that the steps in flowchart 1000 are not necessarily performed in the sequence illustrated In general, steps 1010 and 1020 of flowchart 1000 are performed substantially at the same time, although they may be performed at different times

In step 1010, an electrical load is applied to a first node or bit line (e g , the drain bit line) corresponding to a selected memory cell to be read (or program verified) This load may be applied using a cascode In step 1020, a precharge is applied to at least one other (a second) node or bit line on the same word line as the first node or bit line The second node or bit line is separated from the first node or bit line by at least one intervening node on the same word line, or at least one bit line in the memory array As described above, more than one bit line (node) may be precharged using a variety of precharge schemes, and the precharge voltage may be the same or different for each of the precharge bit lines (nodes) By precharging a bit line or node that is separated from the selected memory cell by at least one intervening bit line or node, the amount of leakage current is reduced Thus, embodiments of the present invention provide a method and device thereof that can reduce and potentially minimize the amount of leakage current between memory cells Also, using a precharge scheme as described according to the various embodiments of the present invention, it becomes less important to match the precharge voltage with the voltage on the drain line in order to reduce leakage current In other words, the selection of the precharge voltage can be made with greater latitude An additional benefit is that the susceptibility of the selected memory cell to variations in precharge voltage is reduced

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents

Claims

CLAIMSWhat is claimed is:

1. A method for performing a sensing operation on the state of a non-volatile memory cell belonging to a plurality of nonvolatile memory cells configured as a drain-source series, said method comprising: selecting a first column line and coupling said first column line to ground (605); selecting a second column line adjacent to said first column line and coupling said second column line to a first voltage source (610); selecting a third column line and coupling said third column line to a second voltage source (615); selecting a fourth column line and allowing said fourth column line to float (620); and, sensing a current supplied by said first voltage source (625).

2. The method of Claim 1, wherein the selected first column line (CLSi) is adjacent to the selected second column line (CLS ), the selected third column line (CLS₃) is adjacent to the second selected column line (CLS₂) and also adjacent to the selected fourth column line (CLS₄).

3. The method of Claim 1, wherein the selected first column line (CLS is adjacent to the selected second column line (CLS₂), the selected fourth column line (CLS₄) is adjacent to the second selected column line (CLS₂) and also adjacent to the selected third column line (CLS₃).

4. The method of Claim 1, wherein said sensing operation is a read operation.

5. The method of Claim 1, wherein said sensing operation is a verify operation.

6. A method of reading a memory cell, said method comprising: applying an electrical load to a first node (710) in a memory array (700), said first node corresponding to said memory cell (1010); and precharging a second node (712) in said memory array, said second node on a same word line (740) as said first node, wherein said second node is separated from said first node by at least one intervening node in said same word line (1020).

7. The method of Claim 6 wherein said second node is in the range of two to five nodes from said first node.

8. The method of Claim 6 wherein said precharging comprises: applying a voltage in the range of 1.2 to 1.5 volts to said second node.

9. The method of Claim 6 wherein said memory cell utilizes a mirror bit architecture wherein two bits of data are stored in said memory cell.

10. The method of Claim 6 further comprising: precharging a third node (711) in said memory array, wherein more than one node on said word line is precharged.