KR100973788B1 - Column-decoding and precharging in a flash memory device - Google Patents

Abstract

A method of reading a memory cell and a memory array using this method is described. The memory cell groups are arranged in a rectangular array with rows (X-dimension) and columns (Y-dimension). Within the row, the source and drain of the memory cell are connected to form a linear chain. A common wordline is connected to each gate of the row. Separate column lines are connected to each node between adjacent memory cells in the chain. Four column Y-decoders are used to select the column lines for the sensing operation. Voltage is applied to two of the four column lines during the sensing operation. For precharging, an electrical load is applied to the first node of the memory array. In the same wordline of the memory array, the second node, which is away from the first node, is precharged by at least one intermediate node.

Memory Cells, Precharging, Word Lines, Leakage Current

Description

Column-decoding and precharging in flash memory devices {COLUMN-DECODING AND PRECHARGING IN A FLASH MEMORY DEVICE}

The present invention generally relates to an array of memory cells. In particular, the present invention relates to a virtual ground architecture memory array.

The architecture of a typical memory array is known in the art. In general, a memory array includes a number of lines arranged as rows and columns. Although these terms are understood to be relative, the rows of an array are usually referred to as wordlines and the columns are referred to as bitlines.

Word lines and bit lines overlap at points (also referred to as nodes). Memory cells are placed at or near each node and are a type of transistor collectively. In the virtual ground architecture, the bit line serves as the source line or drain line of the memory cell, depending on which transistor (memory cell) is program verified (or read). For simplicity of description, "read" is referred to as a read operation or a program verify operation.

Flash memory devices use memory cell transistors having floating gate structures. Data in the flash memory device is programmed and erased by accumulation or depletion of charge, respectively, on the thin insulating film between the substrate and the floating gate. Programming of the memory cell occurs by applying a sufficient potential difference to the transistor to accumulate excess electrons on the floating gate. Accumulation of additional electrons on the floating gate increases the charge on the gate and the threshold voltage of the transistor. The threshold voltage of the transistor is increased sufficiently above the threshold voltage of the voltage applied during the read cycle, so that the transistor is not turned on during the read cycle. Thus, no current flows through the programmed memory cell, indicating a logic value of "0". The erasing of the data sector is performed by a process in which a potential difference is applied to the transistors of each memory cell in the sector so that excess electrons on the floating gate of each transistor are discharged to the insulating film. Thus, the threshold voltage of the transistor is lowered below the potential applied to the transistor to read data. In the erased state, current will flow through the transistor. When a read potential is applied, the current will flow through the transistor of the memory cell, representing a logic value "1" stored in the memory cell.

When reading the selected memory cell, a core voltage is applied to the word line corresponding to the cell, and the bit line corresponding to the cell is connected to a load (e.g., a cascade or cascode amplifier). Because of the memory array architecture, all memory cells on the wordline are affected by the core voltage. This induces leakage current along the wordline, resulting in undesirable interactions between memory cells on the wordline. Leakage current slows down the read rate (if its magnitude is significant) and can also cause errors in selected memory cells.

In order to minimize the interaction between memory cells on the wordline and increase the read speed, a technique commonly referred to as precharging is used. Precharging is performed by charging (applying an electrical load) to a node corresponding to the memory cell to be read and a neighboring node. In particular, neighboring nodes (and on the same wordline) of the drain node of the selected memory cell are precharged. If the drain node and the precharge node are at approximately the same voltage, precharging has the effect of reducing leakage current. The problem with precharging is that it is difficult to predict the voltage that needs to be applied to the precharging node. If the precharging voltage is too large or too small, it is important to apply a suitable precharging voltage because the memory cell cannot be read properly. However, there are many factors that affect the amount of leakage current and thus the amount of voltage that must be applied to the precharge node. These factors include variations in temperature and supply voltage.

In addition, a relatively new memory architecture, referred to as the mirror bit architecture, is being used. In current mirror bit architectures, two bits may be stored per memory cell, which is different from typically one bit stored in a memory cell. With the advent of multi-bit memory cells, the threshold voltage range typically used to distinguish between "0" and "1" has been subdivided into small ranges assigned to multi-bit logic values. For example, a voltage range of 0.00 to 1.00 V can be used to store one bit by assigning "1" to "0" V and "0" to "1" V. Alternatively, the range 0.00 to 1.00 can be divided into four ranges (0 to 0.25, 0.25 to 0.50, 0.50 to 0.75, and 0.75 to 1.00). These four ranges will be associated with logical values "11", "10", "01", and "00".

Although multi-bit memory cells provide an increase in information storage capacity, this also increases the accuracy requirement for the measurements used to distinguish between logic values related to the state of the memory cell. Furthermore, bit patterns (e.g., 00,01,10 or 11) stored in multi-bit memory cells also increase the amount of leakage current. Thus, it is difficult to estimate an appropriate amount of precharging voltage, especially in the case of mirror bit architectures.

Methods of reading memory cells, and memory arrays using these methods, are described in various embodiments. In one embodiment, an electrical load is applied to the first node (or bitline) of the memory array, which first node corresponds to the memory cell. The second node (or bitline) of the memory array, which is on the same wordline as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same wordline.

In another embodiment, groups of memory cells are arranged in a rectangular array with rows (X-dimensions) and columns (Y-dimensions). In a row, the source and drain of the memory cell are connected to form a linear chain. A common wordline is connected to each gate of the row. Separate column lines are connected to each node between adjacent memory cells in the chain. Four column Y-decoders are used to select the column lines for the sense operation. A voltage source is applied to two of the four column lines during the sensing operation. The current on one of the column lines can be sensed to provide a measurement for reading or verifying.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and form a part of this specification, and which illustrate embodiments of the invention in conjunction with the description, help to understand the principles of the invention.

1A is a schematic diagram of a multi-bit memory cell in accordance with an embodiment of the present invention.

FIG. 1B shows the threshold voltage distribution associated with the logic state of the multi-bit memory cell of FIG. 1A.

FIG. 2A illustrates a drain-source series of memory cells with column lines in accordance with one embodiment of the present invention.

2B is an equivalent circuit diagram of parasitic capacitance and resistance associated with the sensing operation of a memory cell in a drain-source column.

3A illustrates four column selection for a sensing operation in accordance with one embodiment of the present invention.

3B illustrates four column selection for a read operation in accordance with one embodiment of the present invention.

3C illustrates four column selection for a verify operation in accordance with one embodiment of the present invention.

4 illustrates a memory cell array sector layout with reference and redundancy block operations in accordance with one embodiment of the present invention.

5A shows a source selector for one column of a four column Y-decoder according to one embodiment of the invention.

5B shows a metal bit line selection portion for one column of a four column Y-decoder according to one embodiment of the invention.

5C shows a diffusion bit line selection portion for one column of a four column Y-decoder according to one embodiment of the invention.

6 is a flowchart for four column sensing operations according to an embodiment of the present invention.

7 illustrates a portion of a memory array in accordance with one embodiment of the present invention.

8A illustrates an exemplary memory array in accordance with one embodiment of the present invention.

8B illustrates an exemplary mirror bit memory cell in accordance with one embodiment of the present invention.

9A illustrates one embodiment of a precharging configuration in accordance with the present invention.

9B shows another embodiment of a precharging configuration according to the present invention.

10 is a flowchart of reading a memory cell according to an embodiment of the present invention.

The drawings referred to herein are to be understood as not being drawn to scale, except in special cases.

In the following detailed description of the invention, numerous specific examples are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will recognize that the present invention may be practiced without these specific examples or their equivalents. In other instances, well-known methods, procedures, elements, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

Portions of the following detailed description are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that may be performed on computer memory. This description and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. As used herein, procedures, computer-implemented steps, logic blocks, processes, and the like are generally considered to be self-consistent sequences of steps or instructions that produce a desired result. These steps require physical manipulation of the physical quantity. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared and otherwise manipulated by a computer. References to these signals as bits, values, elements, symbols, letters, terms, numbers, etc. have been demonstrated many times as primarily convenient for general use.

However, all these or similar terms should be related to the appropriate physical quantities, and it should be borne in mind that these are merely convenient notations applied to their quantities. Unless specifically stated otherwise in the following discussion, throughout the present invention, discussions using terms such as "selection", "sensing", "authorization", "precharging", etc., refer to registers of computer systems and the like. Computer systems or similar electronic computing devices that manipulate and convert data represented as physical (electrical) quantities in memory into computer system memory or registers or other data similarly represented as physical quantities within such information storage, transmission or display devices. It should be recognized that the operation and process of the above is mentioned.

System and method for Y-decoding

1A is a schematic diagram of a multi-bit memory cell 100 having a gate 105, a source 115, and a drain 110. The memory cell stores left bit 125 (X _L ) and right bit 120 (X _R ). In sensing the bit state of a memory cell, a source 115 is connected to ground and a voltage source is applied to drain 110, while a voltage is applied to gate 105.

FIG. 1B is a schematic diagram of threshold voltage distributions 150, 155, 160 and 165 associated with logic states “11”, “10”, “01” and “11” respectively of the multi-bit memory cell 100 of FIG. 1A. The X-axis V _t represents the threshold voltage, and the Y-axis N represents the number of memory cells having a specific threshold voltage. In multi-bit memory cells, the increased number of divisions applied to the operating voltage range increases the requirement for detection accuracy to distinguish between logic states of the cell.

2A shows a drain-source column 210 having sixteen memory cells 0-15 and seventeen column lines CL00-CL16. The gate of each memory cell is connected to a common word line 205. The drain of each memory cell is connected to the source of one of the adjacent memory cells, and the source of each memory cell is connected to the drain of another cell of the adjacent memory cell. Drain-source columns are typically used to provide adequate load at the beginning and end of a row, but become a row portion of a memory cell in an array with dummy memory cells (not shown) that are not accessed for storage. Each of the column lines CL00 to CL16 is connected to a drain-source node between adjacent memory cells.

FIG. 2B shows an equivalent circuit representation of parasitic capacitance and resistance associated with the sensing operation of a memory cell in the drain-source column 210 of FIG. 2A. In this example, the source of memory cell 1 is connected to ground and the voltage V _D is connected to the drain. Adjacent memory cells in the drain-source column represent RC networks that depend on the state of the adjacent memory cells and the physical structure of the memory cells and their interconnections. Shunt capacitance 240 and series resistor 245 are shown. In practice, there will be finite values for both shunt resistance and series capacitance. The sensed memory cell also has a resistor 235.

In order to determine the current state of the cell 1, the current i ₂ must be sensed. This is typically done by sensing the current i ₁ provided by the power supply V _D. As shown in FIG. 2B, parasitic resistance and capacitance cause error currents i ₄ and i ₅ . The error current can be a transient current associated with the charge of the capacitance or a steady state current associated with the resistance. In general, i is _4, because the source and ground (S) have a very small path resistance as compared with the current path to the i _5, is more important than i _5.

3A shows four column selections for a sensing operation on memory cell 1 according to one embodiment of the invention. For the read or verify operation on the memory cell 1, two additional column lines CLS ₃ , CLS ₄ are selected, as well as two column lines CLS ₁ , CLS ₂ adjacent to the memory cell 1. CLS ₁ and CLS ₂ are used to provide a base sense current to the memory cell 1, and CLS ₃ and CLS ₄ are used in conjunction with the voltage source in reducing the error current i ₄ of FIG. 2B.

3B illustrates four column selections and power supplies coupled for a read operation in accordance with one embodiment of the present invention. For the read operation, CLS ₁ of FIG. 3A is connected to ground and CLS ₂ is connected to power supply V ₁ . CLS ₃ is connected to the power supply (V ₂ ) and CLS ₄ is floating. The power supply V ₁ is preferably in the range of 1.2 to 1.4 V. The power supply V ₂ has the same value as the power supply V ₁ , and is preferably in the range of 1.2 to 1.4 V. Typically, the power source (V ₁₎ has a sense amplifier associated to enable the measurement of the current from the power source (V _1).

In one embodiment of the invention, the power supply V ₁ and the power supply V ₂ are one and the same, and the current sensor relates to the connection path to the selected column line CLS ₂ . Thus, a single power supply with two branches is used, and a current sensor is associated with one branch.

Since V ₂ is applied to the column line adjacent to the column line to which V ₁ is applied, when having only one interfering memory cell 2, V ₂ can block parasitic elements associated with the rest of the drain-source column of the memory cell. have. By applying V ₂ in addition to V ₁ , fast charging of parasitic capacitances is possible, thereby reducing the time required to perform the read operation. In general, during a read operation, the fourth selected column line (CLS ₄ ) will float. However, further improvement in speed can be obtained by connecting CLS ₄ to V ₂ in addition to CLS ₃ .

3C illustrates four column selection for a verify operation in accordance with one embodiment of the present invention. For the verify operation, CLS ₁ of FIG. 3A is connected to ground and CLS ₂ is connected to power supply V ₁ . CLS ₄ is connected to the power supply (V ₂ ) and CLS ₃ is floating. The power supply V ₁ is preferably in the range of 1.2 to 1.4V. The power supply V ₂ has the same value as the power supply V ₁ and is preferably in the range of 1.2 to 1.4V.

In contrast to the read operation described above, for the verify operation, V ₁ and V ₂ are not applied to adjacent column lines. This is because the verification operation places more weight on accuracy than speed. In practice, the difference between the V ₁ and V ₂ values is small, resulting in a small steady state error current. In the read operation, this current can be ignored since transient error current is of primary concern. By applying V ₂ to CLS ₄ and allowing CLS ₃ to float, a large effective resistance is obtained between V ₁ and V ₂ , thereby reducing the error current generated by the difference between V ₁ and V ₂ .

4 shows an example of a memory cell array sector layout 400. Sector 405 includes I / O blocks (I / O0 through I / O15), reference blocks 415 and 420, and redundancy blocks 425 forming a core memory array. As shown, the redundancy block is physically separate from the rest of the sector. Each I / O block 410 includes four sub I / Os 430, each of which is 16 cells wide. Each sub I / O (w0, w1, w2, w3) has an associated word number (00, 01, 10, 11). Thus, for a word length of 16 cells, each I / O block is 4 words (ie 64 cells) wide. Reference blocks 415 and 420, and redundancy block 425 are each 16 cells wide. Thus, the default width unit for sector 405 is 16 cells, so a common decoder structure with addressable 16 cell widths can be used to address each block. The total number of decoders required is 67, where 64 decoders are for 16 I / O blocks (I / O0 to I / O15), two decoders are for reference blocks 415 and 420, one The decoder is for redundancy block 425. Sector 405 has a total width of 1072 cells, and may have about half the height of about 512 cells, for example.

5A shows a source selector for one column of a four column Y-decoder according to one embodiment of the invention. Transistor switching ground 503 is controlled by input BSG (n). When the BSG (n) is asserted, the output YBL (n) of the selector is connected to ground. The first power source 501 is controlled by the input BSD (n). When BSD (n) is asserted, output YBL (n) is connected to the first power source. The second power source 502 is controlled by the input BSP (n). When the BSP (n) is asserted, the output YBL (n) is connected to the second power source. When BSG (n), BSD (n), and BSP (n) are all low, the output YBL (n) will float.

5B shows a metal bitline selection of a four column Y-decoder according to one embodiment of the invention. YBL (0), YBL (1), YBL (2), and YBL (3) are connected to the output of source selector YBL (n) as shown in FIG. 5A and controlled by selector CS (7: 0). Branches into two switched metal bitline legs. Eight metal bit lines MBL (0) to MBL (7) are controlled by selector CS (7: 0).

5C shows a diffuse bit line selection of a four column Y-decoder in accordance with one embodiment of the present invention. This part is connected to half of the output of FIG. 5B with a similar part connected to the other half. Each of the metal bit lines MBL (0) to MBL (3) is terminated by two switching diffusion bit lines and is connected to a drain-source node on drain-source column 505. Each of the inputs SEL (0) to SEL (7) controls diffusion bit lines (column lines) 520 to 527. The combination of devices shown in FIGS. 5A, 5B, and 5C can be used to select four columns from sub I / Os that are 16 memory cells wide.

FIG. 6 illustrates a flowchart of four column sensing operations performed in a drain-source column of a memory cell according to an embodiment of the present invention. In step 605, a first column line associated with the memory cell is selected and connected to ground. This column line is collectively connected to the source of the memory cell. In step 610, a second column line is selected and connected to the first voltage source. The second column line is collectively connected to the drain of the memory cell. In step 615, a third column line is selected and connected to the second voltage source, which may or may not be adjacent to the second column line. In step 620, the fourth column line is selected and plotted. The fourth column line may or may not be adjacent to the second column line. For the read operation, it is preferable to make the third column line adjacent to the second column line. For the verify operation, the fourth column line is preferably adjacent to the second column line. In step 625, current from the first voltage source is sensed.

Precharging scheme for reading memory cells

7 illustrates a portion of a memory array 700 in accordance with one embodiment of the present invention. In FIG. 7, only a single word line 740 and a plurality of bit lines 730, 731, and 732 are shown for simplicity of explanation and illustration. However, it will be appreciated that the memory array may actually use different numbers of word lines and bit lines. That is, the memory array 700 may actually extend left and right and horizontally and vertically (where left, right, horizontal, and vertical are relative directions). It is also to be understood that only some elements of the memory array are shown, that is, the memory array may include other elements than those shown. For example, in one embodiment, memory array 700 utilizes a virtual ground architecture. In a virtual ground architecture, the bit line can serve as a source or a drain as the memory is read (or program verified).

A power source (voltage source 760) can be coupled to the word line 740, and a load can also be coupled to each bit line 730-732 (illustrated as cascode 750). The bit lines 730-732 are substantially parallel to each other, and the word line 740 is substantially orthogonal to the bit lines. The word line 740 and the bit lines 730-732 overlap at the plurality of nodes 710, 711, 712, respectively. Memory cells 720, 721, and 722 correspond to each of these nodes. That is, in this embodiment, memory cell 720 corresponds to node 710, memory cell 721 corresponds to node 711, and memory cell 722 corresponds to node 712. Also shown is a memory cell 723 corresponding to another node (not shown). Memory cells 720-723 may be such single bit memory cells, such as memory cell 800 of FIG. 8A, or may be such mirror bit memory cells, such as memory cell 850 of FIG. 8B.

8A illustrates an exemplary memory cell 800 in accordance with one embodiment of the present invention. In this embodiment, the memory cell 800 is a floating gate memory cell including a substrate 810 on which source and drain regions are formed. Typically, memory cell 800 also includes a first oxide layer 820a, a storage element 830 (eg, floating gate), a second oxide layer 820b, and a control gate 840. In an embodiment, the reservoir 830 is used to store a single bit. Memory cells such as memory cell 800 are known in the art.
8B illustrates an exemplary mirror bit memory cell 850 in accordance with one embodiment of the present invention. In this embodiment, the memory cell 850 includes a substrate 860, a first oxide layer 870a, a storage element 880 (eg, a floating gate), a second oxide layer 870b, and a control gate 890. It includes. Unlike the memory cell 800 of FIG. 8A, which is based on asymmetric transistors having separate sources and separate drains, the memory cells 850 are based on symmetrical transistors having similar (selectable) sources and drains. In addition, the mirror bit memory cell 850 is configured such that bits are stored on one or both sides of the storage element 880. In particular, if electrons are stored on one side of the storage element 880, these electrons stay on this side and do not migrate to the other side of the storage element 880. Therefore, in this embodiment, two bits can be stored for each memory cell.

9A illustrates one embodiment of a precharging scheme according to the present invention. In this embodiment, the bit line (eg, bit line 732), which is at least one bit line away from the drain bit line (eg, bit line 730), is precharged. That is, according to an embodiment of the present invention, at least one interference bit line (eg, bit line 731) exists between the drain bit line and the precharging bit line. Although the precharging bit line is shown to lie in only one direction with respect to the drain bit line, it will be appreciated that the precharging bit line may lie in any direction along the word line 740.

The precharging scheme of FIG. 9A is implemented as follows for reading and program verification of a selected memory cell (eg, memory cell 720). For simplicity, the read will be referred to as a read operation or a program verify operation. For readout of memory cell 720, bit line 729 serves as a source bit line, and bit line 730 serves as a drain bit line. An electrical load (eg, cascode) is applied to node 710 (bit line 730) corresponding to memory cell 720. To reduce leakage current, the bit line 732 separated from the bit line 730 (node 710) is precharged by at least one interfering bit line (or node). In one embodiment, this precharging voltage ranges from approximately 1.2V to 1.4V, although other precharging voltages may be used. For example, a 1.5 V precharge voltage may be used. In general, this precharging voltage substantially matches the electrical load at the drain node (eg, node 710). Other factors that may affect the amount of precharging voltage include the way in which the sensing scheme is implemented and the sensing scheme in the design of the cascode and other peripheral circuits.

In other embodiments, the bit line further away from the bit line 730 may be precharged. In other words, a bit line separated from the bit line 730 by one or more (eg, two or more) bit lines or nodes may be precharged on behalf of the precharging bit line 732. It is recognized that there is a limit to how far the precharging bit line can be from the drain bit line. When choosing the distance between the drain bit line and the precharging bit line, there are at least two factors to consider. One factor to consider is that the influence of the precharging bit line on the selected node will be reduced when the precharging bit line is further moved from the drain bit line. Thus, precharging a bitline too far from the selected node will not have sufficient effect on its leakage current. Another factor to consider is the architecture of the memory array. For example, in mirror bit architecture, memory cells are read (decoded) into four groups. This places a limit on the distance between the drain bit line and the precharging bit line. Based on these factors, the distance of up to five bit lines (nodes) between the precharging bit line and the drain bit line is taken into account. However, it will be appreciated that in all embodiments, the application of these features of the present invention is not limited to the distance of 5 bit lines (nodes) between the drain bit line and the precharging bit line.

Figure 9b shows another embodiment of the precharging scheme according to the present invention. In this embodiment, a plurality of bit lines (eg, bitlines 731 and 732) or nodes (eg, nodes 711 and 712) are precharged. Note that in broad terms, at least one of the precharging bits is separated from the drain bit line by an interference bit line (node).

In alternative embodiments, other precharging schemes may be used. For example, three or more bit lines may be precharged. In addition, non-consecutive bitlines may be precharged. Moreover, when a plurality of bit lines are precharged, each of the precharging bit lines may be separated from the selected node by one or more interfering nodes or bit lines. In addition, in addition to the plurality of precharging bit lines, the bit lines on each side of the selected node may be precharged. Again, in broad terms, at least one of the precharging bit lines is separated from the selected node by an interfering node (or bit line).

      In one embodiment where a plurality of bit lines are precharged, the same precharging voltage is applied to each bit line. In another such embodiment, different precharging voltages may be applied to one or more of the precharging bit lines.

10 is a flowchart 1000 of a method of reading (or verifying a program) a memory cell according to an embodiment of the present invention. Although certain steps are described in flowchart 1000, these steps are merely exemplary. That is, the present invention is also suitable for carrying out various other steps and variations thereof from the steps described in the flowchart 1000. It will be appreciated that the steps of flowchart 1000 may be performed in a different order than described in this embodiment, and it need not be performed only in the described sequence. In general, steps 1010 and 1020 of flowchart 1000 are performed substantially concurrently, but they may be performed at different times.

In step 1010, the electrical load is applied to a first node or bit line (eg, drain bit line) corresponding to the selected memory cell to be read (or program verified). This load may be applied using a cascode. In step 1020, precharging is applied to at least one other (second) node or bit line on the same word line as the first node or bit line. The second node or bit line is separated from the first node or bit line by at least one interfering node of the same word line or by at least one bit line of a memory array. As described above, two or more bit lines (nodes) may be precharged using various bit line schemes, and the precharging voltage for each of the precharging bit lines (nodes) may be the same or different.

By precharging the bit line or node separated from the selected memory cell by the at least one interfering bit line or node, the amount of leakage current can be reduced. Accordingly, embodiments of the present invention provide a method and apparatus that can reduce and potentially minimize the amount of leakage current between memory cells. In addition, by using the precharging scheme as described in accordance with various embodiments of the present invention, it is not considered important to match the precharging voltage with the voltage on the drain bit line to reduce leakage current. In other words, the precharging voltage can be selected with a larger range. As a further advantage, the sensitivity of the selected memory cell to changes in the precharge voltage is reduced.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to limit the invention to the precise forms disclosed, and various modifications and variations can be made from the above disclosure. The present embodiments are adopted and presented to best explain the principles of the present invention and its practical application, and those skilled in the art can make various modifications suitable for the specific use contemplated using the present invention and various embodiments. There will be. Therefore, the protection scope of the present invention shall be defined by the appended claims and their equivalents.

Claims (15)

A method of reading a memory cell in a memory array comprising a plurality of parallel bit lines, the method comprising: Applying a predetermined electrical load to the first bit line of the memory array, the first bit line being connected to the memory cell to be read, the memory array being on one side of the first bit line A second bit line adjacent to the first bit line and a third bit line on the other side of the first bit line and adjacent to the first bit line; And Precharging a fourth bitline in the memory array without precharging the second bitline and the third bitline The method of reading a memory cell comprising a. The method of claim 1, And the fourth bit line is spaced apart by two to five bit lines from the first bit line. The method of claim 1, Precharging the fourth bit line, And applying a voltage of 1.2V to 1.5V to said fourth bit line. The method of claim 1, The memory cell, And using a mirror bit architecture, wherein two bits of data are stored in said memory cell. The method of claim 1, Precharging a fifth bit line in the memory array simultaneously with precharging the fourth bit line without precharging the second bit line and the third bit line The method of claim 1, further comprising a memory cell. The method of claim 5, The fifth bit line, And positioned between the first bit line and the fourth bit line. The method of claim 5, The fourth bit line, And between the first bit line and the fifth bit line. As a memory array, A first bit line, a second bit line on one side of the first bit line and adjacent to the first bit line, a third bit line on the other side of the first bit line and adjacent to the first bit line, the first bit line A plurality of parallel bit lines comprising a fourth bit line on one side of the bit line and a fifth bit line on the same side as the fourth bit line; A word line perpendicular to the bit lines; And A plurality of memory cells connected to the word line, each memory cell connected to two adjacent bit lines, the plurality of memory cells comprising one memory cell to be read and the read one memory cell to the Connected to the first bit line It is made, including A predetermined electrical load is applied to the first bit line, and a first precharge electrical load is applied to the fourth bit line without precharging the second bit line and the third bit line. Memory array. The method of claim 8, And the fourth bit line is spaced apart by two to five bit lines from the first bit line. The method of claim 8, And the first precharge electrical load uses a voltage between 1.2V and 1.5V. The method of claim 8, The memory array, And memory cells using a mirror bit structure in which two bits of data are stored in one memory cell. The method of claim 8, And a second precharge electrical load is applied to the fifth bit line simultaneously with precharging the fourth bit line without precharging the second bit line and the third bit line. The method of claim 12, And the first precharge electrical load and the second precharge electrical load use different voltages. The method of claim 12, The fifth bit line, And between the first bit line and the fourth bit line. The method of claim 12, The fourth bit line, And a memory device positioned between the first bit line and the fifth bit line.

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