JP2005537597A - Column decoding and precharging of flash memory devices - Google Patents

Abstract

A method for reading a memory cell and a memory array using this method are described. The groups of memory cells are arranged in a rectangular array having rows (dimension X) and columns (dimension Y). Within the range of one row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is connected to each gate in the row. A separate column line is connected to each node between adjacent memory cells in the chain. A four column Y-direction decoder is used to select a column line for the sensing operation. A voltage source is supplied to two of the four column lines during this sensing operation. An electrical load is applied to the first node of the memory array for precharging. A second node separated from the first node by at least one intermediate node in the same word line of the memory array is precharged.

Description

  The present invention relates generally to arrays of memory cells. In particular, the present invention relates to a virtual ground architecture memory cell.

  Typical memory array architectures are known in the art. In general, a memory array includes a number of lines arranged as rows and columns. The rows of the array are commonly referred to as word lines and the columns are referred to as bit lines, but it is understood that such terms are relative.

  The word line and the bit line overlap at a place called a node. In general, a memory cell which is a kind of transistor is located at or near each node. In a virtual ground architecture, a bit line can serve as a source or drain line for a transistor (memory cell) depending on whether the memory cell is program verified or read. For simplification of explanation, “read” represents both a read operation and a program verify operation.

  The flash memory device uses a memory cell transistor having a floating gate structure. Data in the flash memory device is programmed by charge accumulation on a thin insulating film between the substrate and the floating gate or erased by loss. Memory cell programming occurs by applying a sufficient voltage difference to the transistor to accumulate excess electrons on the floating gate. Accumulation of excess electrons on the floating gate raises the charge on the gate and the threshold voltage of the transistor. The transistor does not turn on during the read cycle because the threshold voltage of the transistor is pulled sufficiently higher than the threshold voltage of the voltage applied during the read cycle. Therefore, the programmed memory cell does not transmit current and exhibits a logical value “0”. Erasing a sector of data occurs by a process in which a voltage difference is applied to the transistors in each memory cell of the sector to move excess electrons on the floating gate in each transistor from the insulating film. In response, the threshold voltage of the transistor is lowered below the threshold voltage of the potential applied to the transistor to read data. When a read potential is applied, the current flows through the transistor of the memory cell and indicates the logical value “1” stored in the memory cell.

  When reading a selected memory cell, a core voltage is applied to the word line corresponding to that cell, and the bit line corresponding to that cell is connected to a load (eg, a cascode or cascode amplifier). Because of this memory array architecture, all of the memory cells on the word line are affected by the core voltage. This induces a leakage current along the word line, causing an undesirable interaction between memory cells on the word line substantially. If the leakage current is sufficiently large, the reading speed is reduced, and an error is caused in reading the selected memory cell.

  In order to minimize the interaction between memory cells on the word line and increase the speed of reading, a technique commonly referred to as precharging is used. Precharging works by charging the node next to the node corresponding to the memory cell being read (applying an electrical load). In particular, the node next to the drain node (on the same word line) of the selected memory cell is precharged. If the drain node and the precharge node have substantially the same voltage, the precharge has an effect of reducing the leakage current.

  A problem associated with precharging is the difficulty in predicting the voltage to be applied to the precharge node. The reason why it is important to apply an appropriate precharge voltage is that if the precharge voltage is too high or too low, the memory cell will not be read properly. However, a number of factors can affect the amount of leakage current and thus the amount of voltage to be applied to the precharge node. These factors include changes in temperature and power supply voltage.

  In addition, a relatively new memory architecture called the mirror bit architecture is beginning to be used. In the latest mirror bit architecture, a single bit is conventionally stored in a memory cell, whereas two bits per memory cell can be stored. With the advent of multi-bit memory, the threshold voltage range that was typically used to distinguish between “0” and “1” was subdivided into a narrower range assigned to multi-bit logic values. For example, a voltage range of 0.00 to 1.00 volts is used to store a single bit by assigning "1" to 0 volts and "0" to 1 volt. On the other hand, the range from 0.00 to 1.00 is four ranges from 0 to 0.25, 0.25 to 0.50, 0.50 to 0.75, and 0.75 to 1.00. Subdivided into These four ranges are associated with logical values “11”, “10”, “01”, and “00”.

  Multi-bit memory cells increase the information storage capacity, but at the same time increase the required accuracy of measurements used to distinguish the logical values associated with the state of the memory cells. In addition, the bit pattern (eg, 00, 01, 10 or 11) stored in the multi-bit memory cell also affects the amount of leakage current. Therefore, it is difficult to estimate an appropriate amount of precharge voltage, which will be even more difficult in the case of a mirror bit architecture.

  Methods for reading memory cells and memory arrays using these methods are described in various embodiments. In one embodiment, an electrical load is applied to the first node (or bit line) of the memory array, the first node corresponding to the memory cell. The second node (or bit line) of the memory array is a second node on the same word line as the first node and is precharged. The second node is separated from the first node by at least one intermediate node in the same word line.

  In another embodiment, the group of memory cells is arranged in a rectangular array having rows (dimension X) and columns (dimension Y). Within the range of one row, the source and drain of the memory cell are connected to form a linear chain. A common word line is connected to each gate in the row. A separate column line is connected to each node between adjacent memory cells in this chain. A four column Y-direction decoder is used to select a column line for the sensing operation. A voltage source is supplied to two of the four column lines during the sensing operation. The current on one column line is sensed to make a measurement for reading or verification.

  The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the detailed description, serve to explain the principles of the invention.

  It should be understood that the drawings referred to in this specification are not to scale unless otherwise noted.

  In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be appreciated by persons skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure features of the present invention.

  Some portions of the detailed descriptions that follow are presented in terms of procedures, steps, logic blocks, processes, and other symbolic representations of operations on data bits executable on computer memory. These descriptions and representations are the means used by data processing technology professionals to most effectively convey the content of their work to others skilled in the art. Procedures, computer-executed steps, logic blocks, processes, etc. are generally considered herein as a consistent sequence of steps or instructions that produce the desired result. These steps are those requiring physical manipulation of physical quantities. In general, these quantities take the form of electromagnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated within a computer, but it is not essential to do so. It has proven convenient at times, principally for reasons of common practice, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

  However, it should be noted that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels attached to these quantities. Unless otherwise noted, throughout the present invention, as will be apparent from the following description, descriptions using terms such as “selection”, “detection”, “application”, “precharging”, etc. Or a description of the operation and process of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in a register or other information storage, transmission or display device. Is recognized.

System and Method for Y Direction Decoding FIG. 1A is a schematic diagram of a multi-bit memory cell 100 having a gate 105, a source 115, and a drain 110. FIG. The memory cell stores a left bit 125 (X _L ) and a right bit 120 (X _R ). In detecting the bit state of the memory cell, the source 115 is grounded, the voltage source is applied to the drain 110, while the voltage is applied to the gate 105.

FIG. 1B is a schematic diagram of threshold voltage distributions 150, 155, 160, and 165 associated with logic states “11”, “10”, “01”, and “11”, respectively, of multi-bit memory cell 100 of FIG. 1A. is there. The X axis (V _T ) represents the threshold voltage, and the Y axis (N) represents the number of memory cells having a specific threshold voltage. In a multi-bit memory cell, as the number of partitions applied to the operating voltage range increases, the required detection accuracy increases to distinguish the logic state of the cell.

  FIG. 2A shows a drain-source series circuit 210 having 16 memory cells (0-15) and 17 column lines (CL00-CL16). The gates of the memory cells in the series circuit are connected to the common word line 205. The drain of each memory cell is connected to the source of one memory cell of its adjacent memory cell, and the source of each memory cell is connected to the drain of the other memory cell of its adjacent memory cell. A drain-source series circuit is used to provide an appropriate load at the beginning and end of the row, and for the rows of memory cells in the array that typically have dummy memory cells (not shown) that are not utilized for storage. It is a part. Column lines CL00 to CL16 are respectively connected to drain-source nodes between adjacent memory cells.

2B is an equivalent circuit diagram of parasitic capacitance and resistance related to the sensing operation of the memory cell in the drain-source series circuit 210 of FIG. 2A. In this example, the memory cell 1 has its source grounded and the voltage V _D applied to its drain. Adjacent memory cells in the drain-source series circuit provide an RC network that depends on the state of adjacent memory cells and the physical structure of the memory cells and their interconnections. A parallel capacitor 240 and a series resistor 245 are shown. In practice, there are finite values of parallel resistance and series capacitance as well. The sensed memory cell also has a resistor 235.

To determine the state of the cell 1, it is necessary to detect the current i _2. This is typically done by sensing the current i _i supplied by the voltage source V _D. As can be seen from FIG. 2B, the parasitic resistance and capacitance cause error currents i ₄ and i ₅ . The error current is a transient current associated with the charging of the capacity, or the error current is a steady current associated with the resistance. In general, i ₄ is more important than i ₅ and the grounded source S has a much smaller path resistance than the current path of i ₅ .

FIG. 3A is a diagram illustrating selection of four columns for a sensing operation related to the memory cell 1 according to an embodiment of the present invention. Two column lines (CLS ₁ , CLS ₂ ) adjacent to memory cell 1 and two auxiliary columns (CLS ₃ , CLS ₄ ) are selected for either a read or verify operation on memory cell 1. The CLS ₁ and CLS ₂ are used to supply the basic sensing current of memory cell 1, and CLS ₃ and CLS ₄ are used with a voltage source to reduce the error current i ₄ in FIG. 2B.

FIG. 3B is a diagram illustrating four column selection and voltage source coupling for a read operation according to an embodiment of the present invention. For the read operation, CLS ₁ in FIG. 3A is grounded, and CLS ₂ is connected to the voltage source V ₁ . CLS ₃ is connected to voltage source V ₂ and CLS ₄ is left floating. The voltage source V ₁ is preferably in the range of 1.2 to 1.4 volts. The voltage source V ₂ has the same value as the voltage source V ₁ and likewise preferably falls within the range of 1.2 to 1.4 volts. Typically, voltage source V ₁ is associated with a sense amplifier that allows measurement of current from voltage source V ₁ .

In one embodiment of the invention, voltage source V ₁ and voltage source V ₂ are identical and a current sensor is associated with the selected column line CLS ₂ . Thus, a single voltage source having two shunts is used and a current sensor is associated with one shunt.

V ₂ is applied to the column line adjacent to the column line to which V ₁ is applied, and since there is only one memory cell (2) in the middle, V ₂ is the rest of the drain-source series circuit of the memory cell. It is possible to mask the parasitic elements associated with the part. The application of V ₂ in addition to V ₁ allows for rapid charging of the parasitic capacitance, thus reducing the time required to perform the read operation.

In general, during the read operation, the fourth selected column line CLS ₄ is left floating. However, further speed improvements are achieved by connecting CLS ₄ to V ₂ in addition to CLS ₃ .

FIG. 3C is a diagram illustrating selection of four columns for a verification operation according to an embodiment of the present invention. For the verification operation, CLS ₁ in FIG. 3A is grounded, and CLS ₂ is connected to voltage source V ₁ . CLS ₄ is connected to voltage source V ₂ and CLS ₃ is left floating. The voltage source V ₁ is preferably in the range of 1.2 to 1.4 volts. Voltage source V ₂ has the same voltage as voltage source V ₁ and preferably falls within the range of 1.2 to 1.4 volts.

In contrast to the above read operation, in the verification operation, V ₁ and V ₂ are not applied to adjacent column lines. This is because accuracy is more important in the verification operation (rather than speed). In practice, there is a small difference between the values of V ₁ and V ₂ , producing a small steady-state error current. In the case of a read operation, such a current is ignored since transient error current is the main concern. By applying V ₂ to CLS ₄ and leaving CLS ₃ floating, a greater effective resistance can be obtained between V ₁ and V _2, and thus between V ₁ and V ₂ . The error current generated by the difference is reduced.

  FIG. 4 is a diagram illustrating an example of the sector layout 400 of the memory cell array. The sector 405 includes input / output blocks I / O 0 to I / O 15 that form a core memory array, reference blocks 415 and 420, and a redundant block 425. As shown, the redundant block is physically separated from the rest of the sector. Each input / output block 410 includes four sub input / outputs 430, each having a width of 16 cells. Each sub-input / output (w0, w1, w2, w3) has an associated word number (00, 01, 10, 11). Thus, if the word length is 16 cells, each input / output block is 4 words (ie, 64 cells) wide. The reference blocks 415 and 420 and the redundant block 425 are each 16 cells wide. Thus, the basic unit of the width of sector 405 is 16 cells, and a common decoder structure having an addressable width of 16 cells is used to address each block. The total number of decoders required is 67, 64 decoders for 16 input / output blocks I / O0 through I / O15, two decoders for reference blocks 415 and 420, and redundant block 425. And one decoder for. The selector 405 has an overall width of 1072 cells and has a height that is approximately half that width, for example, 512 cells.

  FIG. 5A is a diagram illustrating a source selector for one column of a four column Y-direction decoder according to one embodiment of the present invention. Transistor switched ground 501 is controlled by input BSG (n). When BSG (n) is asserted, the selector output YBL (n) is grounded. The first voltage source 502 is controlled by the input BSD (n). When BSD (n) is asserted, the output YBL (n) is connected to the first voltage source. The second voltage source 502 is controlled by the input BSP (n). When BSP (n) is asserted, the output YBL (n) is connected to the second voltage source. When BSG (n), BSD (n), and BSP (n) are all low, the output YBL (n) is left floating.

  FIG. 5B is a diagram illustrating a metal bit line selection unit of a 4-column Y-direction decoder according to an embodiment of the present invention. YBL (0), YBL (1), YBL (2) and YBL (3) are connected to the output of the source selector YBL (n) as shown in FIG. 5A and are connected between two switchable metal bit lines. Divided into The eight metal bit lines MBL (0) to MBL (7) are controlled by the selector CS (7: 0).

  FIG. 5C is a diagram illustrating a diffusion bit line selection unit of a 4-column Y-direction decoder according to an embodiment of the present invention. This part is connected to one half of the output of FIG. 5B and a similar part is connected to the other half. Each of the metal bit lines MBL (0) to MBL (3) is terminated by two switchable diffusion bit lines and connected to a drain-source node on the drain-source series circuit 505. Each of the inputs SEL (0) to SEL (7) controls the diffusion bit lines (column lines) 520 to 527. The combination of components shown in FIGS. 5A, 5B, and 5C implements a 4-column Y-direction decoder that is used to select 4 columns from the sub-input / output that is 16 memory cells wide.

  FIG. 6 is a flowchart of the four-row detection operation that is performed on the drain-source series circuit of the memory cell according to one embodiment of the present invention. In step 605, the first column line associated with the memory cell is selected and grounded. This column line is generally the source of the memory cell. In step 610, the second column line is selected and connected to the first voltage source. The second column line is generally connected to the drain of the memory cell. In step 615, a third column line is selected and connected to a second voltage source, and the third column line may or may not be adjacent to the second column line. In step 620, the fourth column line is selected and left floating. The fourth column line may or may not be adjacent to the second column line. For the read operation, preferably the third column line is adjacent to the second column line, and for the verification operation, preferably the fourth column line is adjacent to the second column line. In step 625, the current from the first voltage source is sensed.

Precharging Method for Reading Memory Cells FIG. 7 is a diagram illustrating a portion of a memory array 700 according to one embodiment of the present invention. In FIG. 7, a single word line 740 and a number of bit lines 730, 731 and 732 are shown for ease of explanation and illustration. However, of course, the memory array may actually use a different number of word lines and bit lines. That is, the memory array 700 actually extends further to the left and right, and also extends in the horizontal and vertical directions (left, right, horizontal and vertical are relative orientations). Further, it will be appreciated that only certain elements of the memory array are shown, i.e., the memory array actually includes elements not shown. For example, in one embodiment, memory array 700 utilizes a virtual ground architecture. For a virtual ground architecture, the bit line can serve as either a source or a drain depending on the memory cell being read (or program verified).

  A power supply (voltage source 760) can be connected to the word line 740, while a load (exemplified by the cascode 750) can be connected to each of the bit lines 730 to 732. Bit lines 730-732 are substantially parallel to each other, and word line 740 is substantially orthogonal to the bit lines. The word line 740 and the bit lines 730 to 732 overlap a number of nodes 710, 711, and 712, respectively. Corresponding to each of these nodes are memory cells 720, 721, and 722. That is, in this embodiment, the memory cell 720 corresponds to the node 710, the memory cell 721 corresponds to the node 711, and the memory cell 722 corresponds to the node 712. Further, a memory cell 723 is illustrated and corresponds to another node (not shown). The memory cells 720 to 723 may be single bit memory cells such as the memory cell 800 of FIG. 8A or mirror bit memory cells such as the memory cell 850 of FIG. 8B.

  FIG. 8A is a diagram illustrating an exemplary memory cell 800 according to one embodiment of the invention. In this embodiment, the memory cell 800 is a floating gate memory cell including a substrate 810 on which a source region and a drain region are formed. Typically, the memory cell 800 also includes a first oxide film 820a, a storage element 830 (eg, a floating gate), a second oxide film 820b, and a control gate 840. In this embodiment, storage element 830 is used to store a single bit. Memory cells such as memory cell 800 are known in the art.

  FIG. 8B is a diagram illustrating an exemplary mirror bit memory cell 850 according to one embodiment of the present invention. In this embodiment, the memory cell 850 includes a substrate 860, a first oxide film 870a, a memory element 880 (eg, a floating gate), a second oxide film 870b, and a control gate 890. Unlike memory cell 800 of FIG. 8A, which is based on an asymmetric transistor with a separate source and a separate drain, memory cell 850 is based on a symmetric transistor with a similar (selectable) source and drain. Yes. Similarly, mirror bit memory cell 850 is configured such that bits can be stored on either or both sides of storage element 880. In particular, once electrons are stored on one side of the storage element 880, the electrons remain on that side and do not move to the other side of the storage element. Therefore, in this embodiment, 2 bits can be stored per memory cell.

  FIG. 9A is a diagram for explaining an embodiment of the precharge method according to the present invention. In this embodiment, a bit line (eg, bit line 732) that is at least one bit line away from the drain bit line (eg, bit line 730) is precharged. That is, according to this embodiment of the present invention, there is at least one intervening bit line (for example, bit line 731) between the drain bit line and the precharge bit line. Although the precharge bit line is illustrated as being in one direction relative to the drain bit line, the precharge bit line may be in either direction along the word line 740.

  The precharge method of FIG. 9A is implemented as described below for reading or program verification of a selected memory cell (eg, memory cell 720). (To simplify the description herein, the term read is used for both read and program verify operations.) For reading memory cell 720, bit line 728 serves as a source bit line. The bit line 730 serves as a drain bit line. An electrical load (eg, cascode) separated from bit line 730 (node 710) by at least one intervening bit line (or node) is precharged. In one embodiment, the precharge voltage is in the range of about 1.2 to 1.4 volts, although other precharge voltages may be used. For example, a precharge voltage of 1.5 volts can be considered. In general, the precharge voltage is matched to the electrical load on the drain node (eg, node 710) as closely as possible. Other factors that can affect the amount of precharge voltage include the sensing method implemented and the effect that the sensing method has on the design of the cascode and other peripheral circuits.

  In other embodiments, bit lines further away from bit line 730 may be precharged. In other words, bit lines separated by more than one (eg, two or more) bit lines or nodes from bit line 730 are precharged instead of precharging bit line 732. Of course, the distance that the precharge bit line is separated from the drain bit line is limited. At least two factors need to be considered when selecting the distance between the drain bit line and the precharge bit line. One factor to consider is that as the precharge bit line moves away from the drain bit line, the effect of the precharge bit line on the selected node is reduced. Therefore, precharging a bit line very far from the selected node does not have a significant and sufficient effect on the leakage current. Another factor to consider is the memory array architecture. For example, in a mirror bit architecture, memory cells are read (decoded) in groups of four. This can limit the distance between the drain bit line and the precharge bit line. Based on these factors, a distance of up to five bit lines (nodes) can be considered between the precharge bit line and the drain bit line. However, it can be seen that the features of the present invention are applied in all of the embodiments without being limited to the case where the distance between the drain bit line and the precharge bit line is a 5-bit line (node). .

  FIG. 9B is a diagram for explaining another embodiment of the precharge method according to the present invention. In this embodiment, multi-bit lines (eg, bit lines 731 and 732) or nodes (eg, nodes 711 and 712) are precharged. In a broad sense, it should be noted that at least one of the precharge bit lines is separated from the drain bit line by an intermediate bit line (node).

  In other embodiments, other precharge methods are used. For example, three or more bit lines are precharged. In addition, discontinuous bit lines may be precharged. Further, when multiple bit lines are precharged, each of the precharge bit lines is separated from the selected node by one or more intermediate nodes or bit lines. In addition, a number of precharge bit lines are used to precharge the bit lines on both sides of the selected node. Again, in a broad sense, at least one precharge bit line is separated from the node selected by the intermediate node (or bit line).

  In one embodiment where multiple bit lines are precharged, the same precharge voltage is applied to each bit line. In another such embodiment, different precharge voltages are applied to one or more precharge bit lines.

  FIG. 10 is a flowchart 1000 of a method for reading (or verifying a program) a memory cell according to one embodiment of the present invention. Although specific steps are described in flowchart 1000, such steps are exemplary. That is, the present invention is suitable for performing various other steps or variations of the steps described in flowchart 1000. It will be appreciated that the steps of flowchart 1000 may be performed in an order different from the presented order, and that the steps of flowchart 1000 may not necessarily be performed in the order shown. In general, steps 1010 and 1020 of flowchart 1000 are performed substantially simultaneously, but they may be performed at different times.

  In step 1010, an electrical load is applied to the first node or bit line (eg, drain bit line) corresponding to the selected memory cell to be read (or program verified). This load may be applied using a cascode. In step 1020, a precharge is applied to at least one other (second) node or bit line on the same word line as the first node or bit line. The second node or bit line is separated from the first node or bit line by at least one intermediate node on the same word line or by at least one bit line in the memory array. As described above, two or more bit lines (nodes) are precharged using various precharge methods, and the precharge voltage may be the same or different for each precharge bit line (node). .

  By precharging a bit line or node separated from a memory cell selected by at least one intermediate bit line or node, the amount of leakage current is reduced. Accordingly, embodiments of the present invention provide a method and apparatus that may reduce and minimize leakage current between memory cells. Also, using a precharge method as described by the various embodiments of the present invention reduces the importance of matching the precharge voltage to the voltage on the drain line to reduce leakage current. . That is, the precharge voltage can be selected with a greater degree of freedom. A further effect is that the selected memory cell is less affected by changes in the precharge voltage.

  The foregoing descriptions of specific embodiments of the present invention have been disclosed for purposes of illustration and description. These descriptions are not intended to be exhaustive or to limit the invention to the same form as disclosed, and naturally many variations and modifications are contemplated in view of the above teachings. It is done. The embodiments have been selected and described in order to best explain the principles of the invention and its practical application, whereby various modifications may be made by those skilled in the art to suit the invention and the particular application contemplated. The various embodiments are best utilized. It is intended that the scope of the invention be defined by the claims recited in the claims and their equivalents.

1 is a schematic diagram of a multi-bit memory cell according to an embodiment of the present invention. 1B illustrates a threshold voltage distribution associated with the logic state of the multi-bit memory cell of FIG. 1A. FIG. FIG. 3 is a diagram illustrating a drain / source series circuit of a memory cell together with a column line according to an embodiment of the present invention. FIG. 6 is an equivalent circuit diagram of parasitic capacitance and resistance associated with the sensing operation of the memory cell in the drain / source series circuit. It is a figure explaining 4 column selection for detection operation by one example of the present invention. FIG. 5 is a diagram illustrating selection of four columns for a read operation according to an embodiment of the present invention. It is a figure explaining 4 column selection for verification operation by one Example of the present invention. FIG. 4 is a diagram illustrating a sector layout of a memory cell array using reference and redundant block operations according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a source selector for one column of a four column Y-direction decoder according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a metal bit line selection unit of a 4-column Y-direction decoder according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a diffusion bit line selection unit of a 4-column Y-direction decoder according to an embodiment of the present invention. 4 is a flowchart of a four-row detection operation according to an embodiment of the present invention. FIG. 3 illustrates a portion of a memory array according to one embodiment of the present invention. FIG. 3 illustrates an exemplary memory cell according to one embodiment of the present invention. FIG. 3 illustrates an exemplary mirror bit memory cell according to one embodiment of the present invention. It is a figure explaining one Example of the precharge method by this invention. It is a figure explaining another Example of the precharge method by this invention. 3 is a flowchart of a method of reading a memory cell according to an embodiment of the present invention.

Claims (10)

A method for performing a state detecting operation of a nonvolatile memory cell belonging to a plurality of nonvolatile memory cells configured as a drain-source series circuit,
Selecting a first column line and grounding the first column line (605);
Selecting a second column line adjacent to the first column line and connecting the second column line to a first voltage source (610);
Selecting a third column line and connecting the third column line to a second voltage source (615);
Selecting a fourth column line and placing the fourth column line in a floating state (620);
Sensing (625) the current supplied by the first voltage source;
Having a method. The selected first column line (CLS ₁ ) is adjacent to the selected second column line (CLS ₂ );
The selected third column line (CLS ₃ ) is adjacent to the selected _second column line (CLS ₂ ), and is also adjacent to the selected fourth column line (CLS ₄ );
The method of claim 1. The selected first column line (CLS ₁ ) is adjacent to the selected second column line (CLS ₂ );
The selected fourth column line (CLS ₄ ) is adjacent to the selected _second column line (CLS ₂ ), and is also adjacent to the selected third column line (CLS ₃ );
The method of claim 1.   The method of claim 1, wherein the sensing operation is a read operation.   The method according to claim 1, wherein the detection operation is a verify operation. Applying an electrical load to a first node (710) corresponding to a memory cell in the memory array (700);
A second node (712) in the memory array is pre-determined on the same word line as the first node and separated from the first node by at least one intermediate node in the same word line. Charging (1020);
A method for reading a memory cell comprising:   The method of claim 6, wherein the second node is in the range of 2 to 5 nodes from the first node.   The method of claim 6, wherein the precharging comprises applying to the second node a voltage that falls within a range of 1.2 to 1.5 volts.   The method of claim 6, wherein the memory cell utilizes a mirror bit architecture and two bits of data are stored in the memory cell.   The method of claim 6, further comprising precharging a third node (711) in the memory array, wherein two or more nodes on the word line are precharged.

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