KR20070036046A - Semiconductor device and programming method - Google Patents

Abstract

The semiconductor device of the present invention selects non-adjacent pages when writing multi-bit data into a plurality of pages by using pages of predetermined number of memory cells arranged on the same word line WL as a selection unit. A column decoder (selection write circuit) 7 which writes bits simultaneously to a memory cell of a page is provided.

By widening the interval of memory cells to write at the same time, unnecessary stress caused by writing to the memory cells not writing is avoided.

Program, memory, multi-bit, page

Description

Semiconductor Device and Writing Method {SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD}

The present invention relates to a semiconductor device capable of writing multi-bit data at the same time and a writing method thereof.

BACKGROUND Semiconductor devices, such as nonvolatile semiconductor memory devices, have increased in capacity due to advances in process technology. As the capacity increases, the demand for faster writing and erasing increases.

In flash memory, it is necessary to write all bits before erasing, so increasing the writing speed is also connected to increasing the erasing speed. Therefore, a plurality of data has been simultaneously written in writing units such as one byte (8 bits) and one word (16 bits).

However, in a virtual ground type nonvolatile semiconductor memory device which shares bit lines of adjacent memory cells on the same word line with each other, if the distance between memory cells for writing multiple bits is too close, no memory cell is written. There is a problem that the stress of writing until applied.

In FIG. 1, metal bit lines MBL0 to MBL5 and metal bits connected to the same word line and connected to the memory cells 0 to 4 of the virtual ground type and the drain or source regions of memory cells 0 to 4 that share bit lines with each other. Selection switches Sse10 to Sse15 for connecting each of the lines MBL0 to MBL5 to the ground line and selection switches Dse10 to Dse15 for connecting each of the metal bit lines MBL0 to MBL5 to the data line are shown. 1 is a part of a nonvolatile semiconductor memory device, and only main parts necessary for explanation are shown.

For example, it is assumed that the metal bit line MBL0 is set at low level and the metal bit line MBL1 is set at high level in order to write data into memory cell 0 shown in FIG. Simultaneously with this writing, the metal bit line MBL2 is set to low level and the metal bit line MBL3 is set to high level in order to write data to the memory cell 2. At this time, the memory cell 1 sandwiched between the memory cell 0 and the memory cell 2 connects a gate to the word line WL common to the memory cell 0 and the memory cell 2, and the metal bit line MBL1 is at a high level, thereby the metal bit. Since the line MBL2 is set at the low level, data is also written to the memory cell 1. In other words, it stresses writing to memory cells that do not need to write data.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and a writing method capable of stably performing multi-bit simultaneous writing.

In order to achieve this object, in the present invention, a plurality of word lines, a plurality of bit lines, and a plurality of pages are defined for each word line, each page has a predetermined number of nonvolatile memories, and the word lines and the bit lines. A semiconductor device including a selection write circuit for selecting a page which is not adjacent to a plurality of nonvolatile memory cells connected to the plurality of nonvolatile memory cells, and simultaneously programming the nonvolatile memory cells of the selected page. By widening the interval between the memory cells to write at the same time, unnecessary stress caused by writing to the memory cells not to write is avoided.

In the semiconductor device, the plurality of pages associated with one word line include an even page and an odd page, and the selection write circuit programs the nonvolatile memory cells of any one of the even and odd pages. The nonvolatile memory cell of the other page can be programmed later. By writing data on even pages and data writing on odd pages in sequence, multi-bit simultaneous writing can be realized without changing the configuration of the memory cell array and the decoding of bit line selection.

The selective writing circuit may be a floating state in which the bit lines connected to the nonvolatile memory cells of the page where data is not written. By making the bit line of the memory cell of the page not writing data into the floating state, no cell current flows through the bit line into the memory cell not writing data. Therefore, unnecessary data is not written into the memory cell or stress is not applied to the memory cell.

The semiconductor device has a plurality of blocks with respect to one word line, each block having a predetermined number of pages,

The semiconductor device has a first mode in which one page is programmed simultaneously in each block, and a second mode in which odd or even pages are simultaneously programmed for each block.

The semiconductor device can be configured to include a control circuit for operating the selection write circuit in either the first mode or the second mode in response to a command from the outside. Since data can be written in a plurality of write modes, the speed of the write can be adjusted, and data can be written according to the operator's wishes.

And a high voltage generation circuit for generating a high voltage for programming the nonvolatile memory cell, wherein the selection write circuit is configured to activate a selected bit line using the high voltage generated by the high voltage generation circuit. You can do Since the power supply from the external device does not need to be supplied, data can be written into the memory cell using only the semiconductor device.

Also, a high voltage generation circuit for generating a high voltage for programming the nonvolatile memory cell and the high voltage at which the high voltage generation circuit is generated in the first mode are selected inside the semiconductor device, and external in the second mode. Has a selection circuit for selecting a different high voltage from the write mode, wherein the selected high voltage cannot be realized with the supply voltage of the internal high-voltage generating circuit by changing the source of the high voltage in accordance with the data write mode given to the selection write circuit. Can be realized and the number of bits that can be written at the same time can be increased.

In the above configuration, among the nonvolatile memory cells in which data can be written at the same time, a write level scheduling circuit for generating a dummy programming current corresponding to the number of the nonvolatile memory cells that are not written is included. can do. Since the voltage drop of the power supply at the time of data writing can be kept constant, the writing level of data written to the memory cell can be made constant.

The above level leveling circuit has a plurality of writing level leveling subcircuits, and each level leveling subcircuit can be configured to be provided on each of two adjacent pages which are not programmed at the same time. The voltage drop of the power supply at the time of data writing can be kept constant by flowing a current almost equal to the cell current flowing into the memory cell from the selected bit line to the writing level constant circuit. Therefore, the write level of the data written to the memory cell can be made constant. In addition, since two write-level constant circuits can be shared by two adjacent pages which do not write data at the same time, the number of circuits can be reduced and the device configuration can be reduced.

Each of the write level constant sub-circuits needs to be able to generate a current almost equal to a program current flowing through one nonvolatile memory cell during programming.

The nonvolatile memory cell may be a virtual ground type nonvolatile memory cell in which adjacent nonvolatile memory cells share a bit line. In a virtual ground type memory cell, when data is written to many memory cells at the same time, if the distance between the memory cells to write is too close, the stress of writing is applied to the memory cells not to write. By the semiconductor device of the above structure, multi-bit simultaneous writing can be performed stably.

The present invention includes a non-volatile memory cell including a predetermined number of nonvolatile memory cells, comprising selecting a non-contiguous page with respect to one word line, and simultaneously programming the nonvolatile memory cells of the selected page. Include writing methods. By widening the interval between the memory cells to write at the same time, it is possible not to give unnecessary stress to the memory cells not to write.

In this case, with respect to one word line, the plurality of pages include an even page and an odd page, and in the programming, the selective writing circuit may program a nonvolatile memory cell of any one of the even and odd pages. After that, the nonvolatile memory cell of the other page can be programmed. By writing data on even pages and data writing on odd pages in sequence, multi-bit simultaneous writing can be realized without changing the configuration of the memory cell array and the decoding of bit line selection.

The writing step may include a step of floating a bit line of the nonvolatile memory cell of a page in which data is not written. By making the bit line of the memory cell of the page not writing data into the floating state, the cell current flows through the bit line into the memory cell not writing data. Therefore, there is no problem in that unnecessary data is written into the memory cell or stressed in the memory cell.

The selecting and the programming are related to a first mode, and the method is a nonvolatile memory in a second mode in which one page of a predetermined number of pages included in each block relating to one word line is programmed simultaneously. And programming the cell and selecting either the first mode or the second mode according to an external command. Since data can be written in multiple write modes, it is possible to adjust the writing speed.

Effects of the Invention

The present invention can stably perform multi-bit simultaneous writing.

1 is a view for explaining a method of writing a conventional semiconductor device.

2 is a block diagram showing the configuration of a semiconductor device of the present invention.

3 is a diagram illustrating a configuration of a data input / output (I / 0) circuit.

4 is a diagram illustrating a correspondence relationship between a cell array, a column gate, and a data input / output (I / O) device.

5 is a timing chart at the time of 64-bit simultaneous writing.

Fig. 6 is a timing chart during 16-bit simultaneous writing.

7 illustrates a logic gate for generating a GEL signal.

8 is a diagram showing the configuration of the cell array 5 and the column gates.

9 is a diagram illustrating a configuration of a write level constant circuit.

10 is a diagram illustrating a configuration of a current compensation circuit.

EMBODIMENT OF THE INVENTION Hereinafter, the best state for implementing this invention is demonstrated, referring an accompanying drawing.

2 shows a configuration of a semiconductor device of this embodiment. The semiconductor device shown in FIG. 2 is an embodiment of the nonvolatile semiconductor memory device 1, and includes a control circuit 2, a chip enable / output enable circuit 3, an input / output buffer 4, a cell array 5, Row decoder 6, column decoder (selective writing means) 7, address latch 8, column gate 9, data input / output (I / O) circuit 10, write circuit 11, readout circuit (12), an erase circuit (13), and a power supply unit (20). In addition, the power supply 20 includes a drain high voltage generator 21, a selector 22, a regulator 23, a gate high voltage generator 24, and the like.

The control circuit 2 receives a control signal, an address signal, a data signal such as a write enable (/ WE) or a chip enable (/ CE) from the outside, operates as a state machine based on the signal, and operates as a state machine. Each part of the device 1 is controlled.

The input / output buffer 4 receives data from the outside and supplies this data to the control circuit 2 and the data input / output (I / 0) circuit 10.

The chip enable / output enable circuit 3 receives the chip enable signal / CE and the output enable signal / OE as a control signal from the outside of the device, so that the input / output buffer 4 and the cell array 5 Control operation / non-operation

The readout circuit 12 operates under the control of the control circuit 2, and reads data from the read address of the cell array 5 in order to read the data from the cell array 5, the row decoder 6, and the column decoder (selective writing). Means) 7 and the like.

The write circuit 11 operates under the control of the control circuit 2, and the cell array 5, the row decoder 6, and the column decoder (selective write means) are used to write data to the write address of the cell array 5. (7) and so on. In addition, the erase circuit 13 operates under the control circuit 2, and the cell array 5, the row decoder 6, and the column decoder (selective writing) are used to collectively erase the designated area of the cell array 5 in predetermined units. Means) 7 and the like.

The cell array 5 is a virtual ground type memory array, which includes an array of memory cells, word lines, bit lines, and the like, and stores two bits of data in each memory cell. Between the control gate and the substrate, a film laminated in the order of an oxide film, a nitride film, and an oxide film is formed, and the threshold value is changed by trapping charges on the nitride film to distinguish data "0" and "1". Since the trap layer is an insulating film, charge does not move, and by accumulating charge at both ends of the trap layer, two bits can be written in one cell, and a method of writing two bits in one cell is also called a mirror bit method. In addition, the cell array 5 may be a memory cell using a floating gate made of polycrystalline silicon as a layer for accumulating charge.

In reading data, data from a memory cell designated as an activated word line is read out to the bit line. At the time of writing (hereinafter referred to as a program) or erasing, the word line and the bit line are set to appropriate potentials according to the respective operations, thereby performing charge injection or charge release operations for the memory cells.

The data input / output (I / O) circuit 10 operates under the control of the control circuit 2 to write and read data to and from the cell array 5. The detail of the data input / output (I / O) circuit 10 is demonstrated, referring FIG. As shown in FIG. 3, the data input / output (I / O) circuit 10 includes a ground circuit 31, a write driver 32, a data latch 33, and a sense amplifier (verification circuit) 34.

The ground circuit 31 is a circuit for setting the bit line selected by the column decoder (selective writing means) 7 to the ground level via the column gate 9. The data latch 33 receives the output signal from the column decoder (selective writing means) 7 and latches the data input from the input / output buffer 4. The write driver 32 transfers the data written in the data latch 33 to the bit lines in the cell array 5 via the column gate 9.

The sense amplifier (verification circuit) 34 amplifies the data read in the bit line and amplifies it to a level at which it can be handled as a digital level. At the time of data writing, the write driver 32 is in the writing state and connected to the bit line. At the time of reading, the sense amplifier (verification circuit) 34 is connected to the bit line and the data on the bit line is amplified. In addition, when a page is selected and written, the bit lines of a page adjacent to the page are in a floating state.

In addition, the sense amplifier (verification circuit) 34 judges the read data. The current of the data supplied from the cell array 5 is compared with the reference current according to the designation by the row decoder 6 and the column decoder (selective writing means) 7 to determine whether the data is zero or one. The reference current is a current supplied from a reference cell (not shown). The determination result is supplied to the input / output buffer 4 as read data.

In addition, the verify operation accompanying the program operation and the erase operation is performed for program verifying the current of the data supplied from the cell array 5 according to the designation of the row decoder 6 and the column decoder (selective writing means) 7. And comparison with a reference current for erasure verification. This reference current is also supplied from the reference cell for program verification and erasure verification.

The row decoder 6 selects and drives a plurality of word lines WL based on respective addresses at the time of data writing, erasing and reading, and the word line driver (not shown) is shown in FIG. The predetermined high voltage is supplied from the gate high voltage generator 24 shown in FIG.

The column decoder (selective writing means) 7 controls the column gate 9 based on the address held in the address latch 8. The column gate 9 is selected by the column decoder 7 so that the corresponding sense amplifier (verification circuit) 34 in the data input / output (I / O) circuit 10 is selected.

For example, when reading data from a desired memory cell of the cell array 5, the bit line connected to this memory cell is connected to a corresponding sense amplifier (verification circuit) 34 by a column gate.

In addition, when data is written into a desired memory cell of the cell array 5, a desired memory cell is activated by address data inputted from the outside, and the inputted write data is a column gate from the corresponding data latch 33. It is output to the bit line via (9) and written in the desired memory cell of the cell array 5.

The power supply unit 20 supplies the high voltage generated by the high voltage generator 21 for drain provided in the nonvolatile semiconductor memory device 1 to the data input / output (I / O) circuit 10 and the high voltage for the gate. The high voltage generated by the generator 24 is supplied to the row decoder 6, the column decoder (selective writing means) 7, and the like. The power supplied by the power supply unit 20 is used as a decoding power source required for a write operation or an erase operation. In addition, in the present embodiment, the high voltage generator 21 in the nonvolatile semiconductor memory device 1 generates a high voltage and supplies the high voltage to the data input / output (I / 0) circuit 10. It can be used as a decoding power supply. To write more data at high speed, a power supply with high current supply capability is required. In recent years, due to the lowering of the power supply voltage, there is a limit to the number of bits to be written at the same time as the current supply capability of the high voltage generation circuit 21 inside the nonvolatile semiconductor memory device 1. For this reason, when the number of bits to be written at the same time is large (64-bit simultaneous write mode described later), a high voltage is supplied from the outside, and this high voltage is used as the decoding power supply. The voltage from the outside is input from the acceleration pin (ACC pin) shown in FIG. The selector 22 outputs an externally input voltage to the regulator 23 when the write mode is a 64-bit write mode. In the 16-bit writing mode, the high voltage generated by the internal high voltage generator 21 for draining is output to the regulator 23. In addition, the instruction of the write mode is notified by the write mode instruction signal from the write circuit 11 shown in FIG. The regulator 23 smoothes and constants the high voltage supplied, and outputs it to the power supply line VPROG. In addition, when the current supply capability of the power supply unit 20 is high, it may be operated only by a high voltage supplied from the power supply unit 20 without receiving power supply from the outside.

4, the correspondence between the cell array 5, the data input / output (I / O) circuit 10, and the column gate 9 will be described. One cell array 5 is divided into a plurality of blocks along the bit lines. In this embodiment, the data is divided into 16 blocks. Each block is provided with a data input / output (I / 0) circuit 10 and a column decoder (selective writing means) 7, respectively, so that data for the number of blocks can be input and output in parallel. 4, the data input / output (I / O) circuit 10 is designated as I / O. One block is divided into eight pages. The data input / output (I / O) circuit 10 selects memory cells in units of this page and writes and reads data.

The nonvolatile semiconductor memory device 1 of this embodiment has a 64-bit simultaneous write mode for writing 64-bit simultaneously and a 16-bit write mode for writing 16 bits simultaneously.

In the 64-bit simultaneous writing mode, the cell array 5 is divided into even pages and odd pages, and 64 bits of data are written simultaneously on even or odd pages. Fig. 5 shows a signal output from the column decoder (selective writing means) 7 in the 64-bit simultaneous writing mode. As shown in Fig. 5, the column decoder (selection writing means) 7 selects an even page selection signal PGM_E and an odd page for selecting even pages during a period when the program signal PGM indicating the write permission is at a high level. Outputs the selected odd page selection signal (PGM_O). Since the even page selection signal PGM_E is at a high level, even pages of 0, 2, 4, and 6 are selected by the column gate 9. Similarly, when the odd page selection signal PGM_O is at a high level, odd pages of 1, 3, 5, and 7 are selected by the column gate 9.

In addition, the GSEL signals GSEL0-GSEL7 shown in FIG. 5 are signals for connecting the selected bit line to the ground line. In the period in which the signals of GSEL0, 2, 4, and 6 are at the high level, the signals of GSE L1, 3, 5, and 7 are at the low level. In contrast, in the period where the signals of GSEL1, 3, 5, and 7 are at the high level, the signals of GSEL 0, 2, 4, and 6 are at the low level. For example, the bit line is set to a low level by connecting a selection bit line of even pages into which data is written to the ground line. At this time, since data is not written to the odd pages, the GSEL signal is at a low level, and the bit line is in a floating state. When data is written to even pages, the bit lines of odd pages are set to floating, so that no cell current flows through the bit lines to the memory cells not writing data. That is, memory cells that are not programmed are interposed between memory cells to be programmed. For this reason, unnecessary data is written to the memory cells which do not write, thereby avoiding stress. In addition, since writing to even and odd pages is not performed at the same time, the interval between memory cells to be written at the same time is increased, so that unnecessary stress is not applied to memory cells not to be written. In addition, by writing data into even pages and data writing into odd pages in sequence, multi-bit simultaneous writing can be realized without changing the configuration of the memory cell array and the decoding of bit line selection.

In the 16-bit simultaneous writing mode, each of the 16 blocks shown in Fig. 4 is selected, and data is written to any page in the selected block. 6 shows a timing chart. As shown in Fig. 6, the column decoder (selection writing means) 7 generates the cell signals WSEL0 to WSEL7 for selecting memory cells in a period in which the program signal PGM indicating the write permission is at a high level. Output to the gate 9. The cell signals of WSEL0 to WSEL7 correspond to the pages of each block. That is, when WSEL0 is at the high level, page O is selected, and data is written to the memory cells in this page O. Similarly, when WSEL1 is at the high level, page 1 is selected and data is written to the memory cells in page 1.

In the same manner as in the 64-bit simultaneous write mode, the GSEL signals GSEL0 to GSEL7 are output, and the bit line serving as the source of the written page is connected to ground. Set the bit lines of pages other than the page to which data is written to the floating state.

A logic gate for generating a GSEL signal is shown in FIG. The logic gate is included in the cam decoder 7. The GSEL signals (GSEL 0, 2, 4, 6) for even pages input the even page select signal (PGM_E) and each cell signal WSEL (WSEL0, 2, 4, 6) to the NOR gate 40, and the NOR gate. It is generated by inverting the output of the 40 by the inverter 41. Similarly, the GSEL signals GSEL1, 3, 5, and 7 for odd pages input the odd page selection signal PGM_O and the respective cell signals WSEL (WSEL1, 3, 5, and 7) to the NOR gate 40, and the NOR gate. It is produced by inverting the output of 40 by the inverter 41.

8 shows a detailed configuration of the cell array 5 and the column gate 9. In the vicinity of the intersection of the plurality of word lines WL (only one WL is representatively shown in FIG. 8 for simplicity) and the plurality of metal bit lines MBL, word lines WL, and metal bit lines MBL. A memory cell MC is provided and arranged in a matrix. Two memory cells MC are formed between two metal bit lines MBL. On one page serving as a unit for writing or reading, eight memory cells MC are provided (MC0 to MC7 shown in Fig. 8), and two bits can be written to one memory cell MC. Since two memory cells MS are provided between the two metal bit lines, a sub bit line SBL for connecting the memory cells MC to the two bit lines is provided. The sub bit line SBL is formed of a diffusion layer, is provided in parallel with the metal bit line MBL, and is made of metal through a selection transistor (STr shown in FIG. 8) having a decoded signal from the column decoder 7 as a gate input. It is connected to the bit line MBL.

Further, each metal bit line MBL is drained with a first transistor (GTr shown in FIG. 8) and a metal bit line MBL for switching between connecting or not connecting the metal bit line MBL to the ground signal line ARVSS. A second transistor (DTr shown in Fig. 8) is provided which switches between connecting and not connecting to the signal line DATAB. The decoded signal from the column decoder (selective writing means) 7 switches the opening and closing of the first transistor GTr and the second transistor DTr, and connects it to the metal bit line MBL. The signals generated by the column decoder (selective writing means) 7 are the signals of BSD and BSG shown in FIG. 8. When the BSD signal becomes high, the second transistor DTr is closed and the corresponding bit line and drain signal line DATAB are connected. In addition, when the BSG signal becomes high, the first transistor GTr is closed, and the corresponding bit line and ground signal line ARVSS are connected. The ground line ARVSSn is provided independently for each page.

For example, in the aforementioned 64-bit simultaneous write mode, when the GSEL signals 1, 3, 5, and 7 transition to a high level, the GSEL signals 0, 2, 4, and 6 become low levels. When page 1 shown in FIG. 8 is selected for writing, the ground line of the next page 2 is set to the floating state by the GSEL 2 shown in FIG.

At this time, the write level constant circuit 25 connected to the power supply line VPROG shown in FIG. 2 is demonstrated. The write level constant circuit 25 is composed of a plurality of current compensation circuits 26, as shown in FIG. The current compensating circuit 26 functions as a write level constant sub-circuit, flows a dummy programming current which is a predetermined amount of current from the power supply line VPROG, and adjusts the voltage drop at the time of data writing constantly. In order to make the writing level of the data written into the memory cell constant, it is necessary to keep the drop level of the voltage supplied from the power supply unit 20 constant during the writing. In the nonvolatile semiconductor memory device 1 of this embodiment, only when data of "O" is written, a high voltage is supplied to the data line, the bit line is selected, and a cell current flows through the memory cell. Therefore, in order to keep the voltage drop level constant when writing multi-bit data at the same time, the current compensation circuit 26 is provided as many as the data can be written at the same time. Cell current for the memory cells that do not write the data of " For example, in the case of 16-bit simultaneous writing, if there are three pages in which " 0 " is written, 13-bit writing current is flown out of the writing-level constant circuit 25. Similarly, in the case of 64-bit simultaneous writing, if there are three pages in which " 0 " is written, 61-bit write current is flowed out of the write level constant circuit 25.

However, in the cell array 5 of the 16 I / O, 8 page configuration shown in Fig. 4, 128 current compensating circuits 26 are required, and the number of circuits increases, resulting in a large circuit scale. In this embodiment, the current compensation circuits 26 are provided one by one in two adjacent memory cells which are not written at the same time, so that the circuit scale is not increased.

10 shows a specific configuration of the current compensation circuit 26. As shown in FIG. The current compensating circuit 26 shown in FIG. 10 is a current compensating circuit 26 corresponding to page 0 and page 1, and the resistors R1, R2, R3 and the switch transistors 55, 56 are connected in series to the power supply line VPROG. Connected. The inverter 51 and the NAND gate 52 are connected to the gate of the switch transistor 56. In this way, the inverter 53 and the NAND gate 54 are connected to the gate of the switch transistor 55.

The inverter 51 is input with the page 0 write data P0PGMD signal. The output of the inverter 51 is input to the NAND gate 52. The NAND gate 52 is input with the output signal of the inverter 51 and the signal of GSEL0. The GSEL0 signal is a signal that connects the selected bit line to the ground line in accordance with data when page 0 is selected for writing. The output of the NAND gate 52 becomes the gate input of the switch transistor 56. Similarly, the write data P1PGMD signal of page 1 is input to the inverter 53. The output of the inverter 53 is input to the NAND gate 54. The NAND gate 54 is input with an output from the inverter 53 and a signal of GSEL1. The GSEL1 signal is a signal that connects the bit line selected in accordance with the data to the ground line when page 1 is selected for writing. The output of the NAND gate 54 becomes the gate input of the switch transistor 55.

Except when the data of "0" is written, the switch transistors 55 and 56 are turned on to flow a predetermined amount of current from the power supply line VPROG. This predetermined amount of current is set to be substantially equal to the write current flowing when writing "0" data into the memory cell. For example, when " 0 " is written on page 1, the P1PGMD signal is at a low level. Since the GSEL signal (here, GSEL1) becomes a high level in the page selected for writing, a signal corresponding to the level of the PAPGMD signal is input to the gate of the switch transistor 55 in the NAND gate 54. In addition, when it is not selected to write, the GSEL signal GSEL1 is at a low level, and therefore a high level signal is always output to the switch transistor 55. Thus, the switch transistor 55 is turned on to flow a current from the power supply line VPROG through the resistors R1, R2, and R3.

In addition, the above-described embodiment is a suitable embodiment of the present invention. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, a nonvolatile semiconductor memory device has been described as an example. However, the present invention can be sufficiently applied to a semiconductor device on which the nonvolatile semiconductor memory device is mounted.

Claims (14)

A plurality of word lines, A plurality of bit lines, A plurality of pages are defined for each word line, each page having a predetermined number of nonvolatile memories, a plurality of nonvolatile memory cells connected to the word line and the bit line, And a selection write circuit for selecting pages which are not adjacent to each other and simultaneously programming nonvolatile memory cells of the selected page. The method of claim 1, wherein the plurality of pages relating to one word line include an even page and an odd page, And wherein said selective write circuit programs nonvolatile memory cells of either page of even pages and odd pages, and then programs nonvolatile memory cells of one page. The semiconductor device according to claim 1 or 2, wherein the selective writing circuit puts a bit line connected to the nonvolatile memory cell of a page in which data is not written. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device has a plurality of blocks with respect to one word line, and each block has a predetermined number of pages, The semiconductor device has a first mode in which one page is programmed simultaneously in each block, and a second mode in which odd or even pages are simultaneously programmed for each block. The semiconductor device includes a control circuit for operating the selection write circuit in either the first mode or the second mode in response to a command from the outside. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device has a high voltage generation circuit for generating a high voltage for programming the nonvolatile memory cell. And the selection write circuit activates a selected bit line using the high voltage generated by the high voltage generation circuit. The method of claim 4, wherein A high voltage generator circuit for generating a high voltage for programming the nonvolatile memory cell in the semiconductor device; And a selection circuit for selecting the high voltage at which the high voltage generating circuit is generated in the first mode and selecting another high voltage from the outside in the second mode, wherein the selected high voltage is applied to the selection writing circuit. The dummy programming current according to any one of claims 1 to 6, wherein a dummy programming current corresponding to the number of the nonvolatile memory cells that do not write is generated among the nonvolatile memory cells that can simultaneously write data. Semiconductor Device Including Write Level Scheduling Circuit 8. The semiconductor device according to claim 7, wherein the level constant circuit has a plurality of write level constant sub-circuits, and each level constant sub-circuit is provided one on two adjacent pages which are not programmed at the same time. 10. The semiconductor device according to claim 8, wherein each of the write level constant subcircuits is capable of generating a current substantially equal to a program current flowing through one nonvolatile memory cell during programming. 10. The semiconductor device according to any one of claims 1 to 9, wherein the nonvolatile memory cell is a virtual ground type nonvolatile memory cell in which adjacent nonvolatile memory cells share a bit line. Selecting a page including a predetermined number of nonvolatile memory cells and not adjacent to each other with respect to one word line; And simultaneously programming the nonvolatile memory cells of the selected page. 12. The non-volatile memory as claimed in claim 11, wherein the plurality of pages include an even page and an odd page with respect to one word line. The method of writing a nonvolatile memory in which a cell is programmed and then a nonvolatile memory cell of another page is programmed. 13. The method of claim 11 or 12, wherein the writing step comprises floating a bit line of the nonvolatile memory cell of a page in which data is not written. 14. The method according to any one of claims 11 to 13, wherein the selecting and the programming are related to a first mode, and the method includes a predetermined number of pages included in each block relating to one word line. Programming the nonvolatile memory cell in a second mode in which one page of the plurality of pages is programmed simultaneously; And writing either the first mode or the second mode according to an external command.

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