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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
  • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
  • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
  • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
  • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2

Definitions

• the present invention relates to the fabrication of highly sophisticated integrated circuits including transistor elements with minimum feature sizes of 0.1 ⁇ m and less, and, more particularly, to highly capacitive gate structures including a dielectric with a thickness of an oxide capacitance equivalent thickness of 2 nm and less.
• the silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
• Most modern integrated circuits comprise a huge number of field effect transistors, wherein, for the reasons pointed out above, silicon dioxide is preferably used as a gate insulation layer separating a polysilicon gate electrode from a silicon channel region. In steadily improving device performance' of field effect transistors, a length of this channel region has continuously been decreased to improve switching speed and drive current capability.
• the transistor performance is controlled by a voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length.
• the thickness of the silicon dioxide layer has to be correspondingly decreased to provide for the required capacitance between the gate and the channel region.
• a channel length of 0.13 ⁇ m requires a silicon dioxide thickness in the range of approximately 2-3 nm
• a gate length of 0.08 ⁇ m may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm.
• the relatively high leakage current caused by direct tunneling of charge carriers through an ultra thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that are not acceptable for performance-driven circuits.
• capacitance equivalent thickness a thickness required for achieving a specified capacitive coupling with silicon dioxide.
• capacitance equivalent thickness a thickness required for achieving a specified capacitive coupling with silicon dioxide.
• the present invention is based on the inventors' finding that a high permittivity of the gate dielectric, caused by weakly bound charged clouds of the dielectric material, may effectively be restricted to an angular range substantially perpendicular to the flow direction of the charge carriers in the channel region. Since the capacitive coupling between the gate electrode and the channel region is substantially determined by the electromagnetic interaction of the weakly bound charge clouds with charge carriers, an inversion layer is effectively generated, whereas a lateral coupling of the charge clouds in the dielectric with the charge carriers in the channel region is maintained low.
• a field effect transistor comprises a gate insulation layer formed above an active region and including a high-k dielecfric, wherein a permittivity of the high-k dielectric perpendicular to the gate insulation layer is higher than a permittivity parallel to the gate insulation layer.
• a method of forming a high-k gate insulation layer above a substrate comprises epitaxially growing an anisofropic dielectric material having a first permittivity along a first direction and a second permittivity along a second direction, wherein the second permittivity is higher than the first permittivity. At least one process parameter is controlled to adjust the second direction substantially perpendicular to a surface of the subsfrate.
• a method of forming a high-k dielecfric gate insulation layer comprises providing a subsfrate having formed thereon an active semiconductor region. An anisofropic dielecfric material is then deposited to form a dielecfric layer and the subsfrate is subsequently annealed. At least one process parameter of at least one of depositing and annealing the subsfrate is controlled to adjust a crystalline orientation such that a first permittivity oriented parallel to the dielecfric layer is less than a second permittivity oriented perpendicular to the dielectric layer.
• a method of forming a gate insulation layer having a capacitance equivalent thickness of less than approximately 2 nm comprises selecting a crystalline dielecfric having a different permittivity in at least two different directions. The method further includes determining a process parameter setting for forming the crystalline dielecfric above a subsfrate such that a direction corresponding to the higher permittivity is substantially perpendicular to a surface of the subsfrate. Finally, the crystalline dielecfric is formed in conformity with the parameter setting.
• a field effect transistor comprises a gate insulation layer having a capacitance equivalent thickness of less than 2 nm, wherein the gate insulation layer includes a dielecfric layer.
• a ratio of a permittivity perpendicular to the dielecfric layer to a permittivity parallel to the dielecfric layer is equal to or higher than 1.2.
• Figure la schematically shows a cross-sectional view of a field effect transistor including an anisofropic gate dielecfric;
• Figure lb schematically shows a simplified model of the anisofropic dielecfric
• Figure lc shows a simplified model of a conventional substantially isofropic dielecfric
• Figure 2 depicts an elementary cell of a titanium dioxide crystal
• Figure 3 schematically shows a field effect transistor having a gate dielecfric according to a further illustrative embodiment of the present invention.
• the present invention is, therefore, based on the concept of taking into account, in addition to an increased absolute permittivity, the directionality of the permittivity to thereby significantly affect the interaction of the charge carriers, such as electrons, with the dielecfric material when moving from the source to the drain region.
• a field effect transistor 100 comprises a substrate 101 including an active region 106, typically a silicon-based semiconductor material.
• the transistor 100 is illustrated as an N- channel type.
• the present invention applies to P-channel transistors as well.
• a source region 102 and a drain region 103 are formed in the active region 106.
• a gate electrode 104 for example comprised of polysilicon or any other appropriate conductive material, is formed over the active region 106 and is separated therefrom by a gate insulation layer 105 comprising an anisofropic dielecfric material, such as a crystalline metal-containing oxide or silicate, or ferro-electric materials, or optically anisofropic materials, and the like.
• an anisofropic dielecfric material such as a crystalline metal-containing oxide or silicate, or ferro-electric materials, or optically anisofropic materials, and the like.
• the anisofropic dielecfric of the gate insulation layer 105 may have a first permittivity k para u e ⁇ that is oriented substantially parallel to the gate insulation layer 105, and a second permittivity k orthogona i hi a direction substantially perpendicular to the gate insulation layer 105, wherein k para u e ⁇ is lower than k orthogonab as indicated by reference sign 107.
• a voltage is applied to the gate electrode 104 and to the active region 106.
• the source region 102 and the active region 106 are tied to a common reference potential so that, for the N-channel fransistor 100 shown in Figure la, a positive voltage may lead to the formation of a conductive channel 108 at the interface between the gate insulation layer 105 and the active 5 region 106.
• the gate insulation layer 105 Due to the high permittivity k orthogona i; the gate insulation layer 105 provides a high capacitive coupling of the gate electrode 104 to the channel 108, while the increased physical thickness of the gate insulation layer 105 compared to the capacitance equivalent thickness of 2 nm and less maintains leakage currents from the channel 108 into the gate electrode 105 at an acceptable level. Since the permittivity k para ii e i is significantly lower than the permittivity k o n hogona i perpendicular to the flow direction of the charge carriers, the
• Figure lb shows a simplified model of a portion of the gate insulation layer 105.
• the gate insulation layer 105 including the anisofropic dielecfric, is represented by a two-dimensional grid in which lattices sites are represented by dots 111 that are coupled to the nearest neighbors by springs 110 in the vertical
• the springs 110 and the bars 112 are to represent charge clouds and the corresponding ability to interact with a charged particle. Upon application of a positive
• the corresponding springs 110 will deform, i.e., the charge clouds will be unbalanced, so that an electron is attracted and is tied to the channel region 108.
• the electron will move under the influence of this electric field and will move to the adjacent spring 110a so that the electron remains coupled to the gate insulation layer 105 in the vertical direction. Since the bars 112 do not allow any deformation, at least in this simplified model,
• Figure lc shows this situation for a substantially isofropic gate insulation layer 105a. Since, in this case, the electron may deform the horizontally oriented springs 110, as well as the vertical oriented springs, a certain amount of coupling is present in both directions and results in a reduced mobility of the electrons in the
• the charge carrier mobility in the channel region 108 is significantly less deteriorated, and thus the fransistor performance is increased, compared to a conventional device having an isofropic dielectric. Even if in the conventional device a dielecfric material of comparable
• FIG. 2 shows an example for an anisofropic dielectric material.
• an elementary cell of a titanium dioxide (Ti0 2 ) is shown in the so-called rutile form. In this crystalline form, titanium dioxide is
• a permittivity along the c axis is less than a permittivity along the a axis with a ratio of the a axis permittivity to the c axis permittivity of approximately 2 at room temperature.
• the k value of the permittivity is approximately 60 and may depend on growth parameters and the specific arrangement of the gate insulation layer 105.
• titanium dioxide may be deposited by chemical vapor deposition using precursor gases such as titanium tefrakis isopropoxide (TTIP) and titanium nitrate.
• titanium dioxide is substantially deposited in the rutile form.
• the subsfrate may be annealed within a temperature range of approximately 700-900°C to fransform the titanium dioxide layer into a crystalline layer substantially exhibiting the rutile form.
• a typical prpcess flow with the above-described deposition scheme for forming the field effect fransistor 100 including, for example, a titanium dioxide layer in a crystalline rutile form may comprise the following steps.
• shallow trench isolations (not shown) may be formed to define the active region 106.
• the gate insulation layer 105 is deposited on the substrate 101.
• the gate insulation layer 105 comprises titanium dioxide, and it may be advantageous to deposit a thin barrier layer in order to ensure thermal stability of the titanium dioxide.
• one or two atomic layers of silicon dioxide or silicon nitride, or zirconium silicate and the like, may be deposited on the subsfrate 101.
• titanium dioxide is deposited, for example with chemical vapor deposition as described above, wherein process parameters are adjusted to obtain a crystalline growth with the c axis substantially oriented perpendicular to the surface of the subsfrate 101.
• a corresponding parameter setting depends on the crystal orientation of the subsfrate 101, the type of barrier layer and the deposition conditions and possibly on anneal conditions.
• the crystal orientation upon growing and/or annealing of the titanium dioxide may be established by experiment and/or by theory, for example by means of simulation calculations.
• the titanium dioxide may substantially be deposited at moderate temperatures and may crystallize in subsequent anneal cycles. After deposition of the titanium dioxide, depending on the process recipe, an anneal cycle may be carried out to provide for the required crystallinity. In depositing the titanium dioxide, a thickness is controlled so as to obtain the required capacitance equivalent thickness. As previously pointed out, the effective permittivity k orth ⁇ ga ⁇ a i and k para ⁇ e ⁇ may depend on the deposition specifics and on the type of barrier material used. Typical values are in the range of 20-70. Subsequently, a polysilicon layer may be deposited and patterned by well-established photolithography and etch techniques to form the gate electrode 104. Thereafter, the field effect fransistor 100 may be completed by well-known implantation, spacer and anneal techniques.
• Figure 3 illustrates a schematic cross-sectional view of a further example of a field effect fransistor 300 having a gate dielecfric comprised of an anisofropic high-k material layer 305 and a barrier layer 315 in the form of an extremely thin silicon dioxide layer formed on a silicon subsfrate 301.
• the fransistor 300 further comprises a gate electrode 304 formed on the anisofropic dielectric layer 305 and sidewall spacers 309. Source and drain regions 303 are formed within the subsfrate 301.
• a combined thickness 316 of the layers 305 and 315 is selected to correspond to a capacitance equivalent thickness in the range of approximately 1-1.5 nm.
• an effective thickness of the anisofropic dielecfric layer 305 may be in the range of approximately 3-5 nm, thereby providing a leakage current that substantially corresponds to a silicon dioxide layer of 2 nm and more.
• the fransistor element 300 allows scaling of the gate length well beyond 0.1 ⁇ m while maintaining the leakage current at a level of present cutting-edge devices.
• carrier mobility may be comparable to silicon dioxide-based devices.
• the present invention provides sophisticated transistor elements allowing a gate length of 0.1 ⁇ m and less by providing different permittivities parallel and perpendicular to the gate insulation layer, wherein preferably a ratio of the k orthogona i to the k para ii e i is higher than 1.2 to achieve a significant effect on the charge carrier mobility improvement with respect to capacitance increase and leakage reduction.
• the anisofropy of the dielecfric gate material is selected in accordance with process requirements and the desired target GET.
• the necessity for a barrier layer may dictate a minimum k value to achieve the target CET, wherein the anisofropy has to meet the operational requirements.
• high performance applications may require a high anisofropy to optimize carrier mobility, while leakage currents are still within reasonable limits due to a moderate permittivity, such as the permittivity of titanium dioxide, compared to materials of extremely high values on the order of 100, however, with less pronounced anisofropy.
• the crystallinity of the high-k dielecfric may be adjusted so that the required orientation is obtained.
• the deposition kinetics, the type of barrier layer, if required, the crystalline structure of the subsfrate, and the like may be taken into account, for example, by modeling and/or experiment, to adjust the physical thickness in accordance with the target capacitance equivalent thickness.
• the orientation and/or the crystalline structure may be adjusted by providing one or more sub-layers of one or more different materials. For example, it may be necessary to provide a suitable crystalline structure for depositing the high-k material so as to take on the required orientation. Accordingly, one or more "transition" layers may then be provided to finally provide a deposition basis for obtaining the desired orientation of the "bulk" material having the high k-value.

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