EP1483785A1 - Verfahren und gerät zum integrierten chemisch-mechanischen polieren von kupfer- und barriereschicht - Google Patents

Verfahren und gerät zum integrierten chemisch-mechanischen polieren von kupfer- und barriereschicht

Info

Publication number
EP1483785A1
EP1483785A1 EP03720656A EP03720656A EP1483785A1 EP 1483785 A1 EP1483785 A1 EP 1483785A1 EP 03720656 A EP03720656 A EP 03720656A EP 03720656 A EP03720656 A EP 03720656A EP 1483785 A1 EP1483785 A1 EP 1483785A1
Authority
EP
European Patent Office
Prior art keywords
polishing
pad
layer
solution
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03720656A
Other languages
English (en)
French (fr)
Inventor
Homayoun Talieh
Robin F. Urquhart-Dykes & Lord BROWNE
Bulent Bason
Douglas Young
Yuchun Wang
Tuan Truong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASM Nutool Inc
Original Assignee
ASM Nutool Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/199,471 external-priority patent/US20040014399A1/en
Priority claimed from US10/346,425 external-priority patent/US6857947B2/en
Application filed by ASM Nutool Inc filed Critical ASM Nutool Inc
Publication of EP1483785A1 publication Critical patent/EP1483785A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B21/00Machines or devices using grinding or polishing belts; Accessories therefor
    • B24B21/04Machines or devices using grinding or polishing belts; Accessories therefor for grinding plane surfaces
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/04Lapping machines or devices; Accessories designed for working plane surfaces
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/16Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the load

Definitions

  • the invention relates to the field of chemical mechanical polishing. More particularly, the invention relates to a method and apparatus for integrated polishing of both copper and barriers layers.
  • Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect conductor because of their superior electromigration and low resistivity characteristics.
  • the interconnects are usually formed by filling copper in features or cavities etched into the dielectric interlayers by a metallization process. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential interlayers can be electrically connected using vias or contacts. [0005] In a typical process, first an insulating interlayer is formed on the semiconductor substrate.
  • Patterning and etching processes are performed to form features such as trenches, vias or dual damascene structures in the insulating layer. Then, copper is electroplated to fill all the features. However, the plating process results in a copper layer within the features, as well as on the substrate surface. The excess copper overburden on the surface is then removed before the subsequent processing step.
  • the insulation layer is first coated with a barrier layer, typically, a tantalum or tantalum/tantalum nitride composite layer.
  • the barrier layer coats the vias and the trenches as well as the top surface of the insulation layer to ensure good adhesion and acts as a barrier material to prevent diffusion of the copper into the semiconductor devices and tlirough the insulation layer.
  • a seed (conductive) layer which is often a copper layer, is deposited on the barrier layer.
  • the seed layer forms a conductive material base for copper film growth during the subsequent copper deposition. As the copper film is electroplated, the copper layer quickly fills the vias but coats the wide trench and the surface in a conformal manner.
  • a thick copper layer or overburden is formed on the substrate.
  • a CMP Chemical Mechanical Polishing
  • the barrier layer is then removed by another CMP step.
  • CMP Chemical mechanical polishing
  • CMP is a semiconductor wafer flattening and polishing process that combines chemical removal of layers such as insulators and metals with mechanical buffering of a wafer surface.
  • CMP is also used to flatten/polish wafers after crystal growing and during the wafer fabrication process, and is a process that provides global planarization of the wafer surface.
  • CMP is often used to flatten/polish the profiles that build up in multilevel metal interconnection schemes. Achieving the desired flatness of the wafer surface must take place without contaminating the desired surface. Also, the CMP process must avoid polishing away portions of the functioning circuit parts.
  • One conventional CMP process requires positioning a wafer on a holder rotating about a first axis and lowered onto a polishing pad rotating in to the opposite direction about a second axis.
  • the wafer holder presses the wafer against the polishing pad during the planarization process.
  • a polishing solution such as a polishing agent or slurry is typically applied to the polishing pad during the polishing of the wafer.
  • the content of the polishing solution depends on the nature of the material to be removed during the CMP.
  • the polishing solution may be composed any one or more of abrasives, oxidizers, complexing reagents (etching chemicals), inhibitors and/or surfactants.
  • abrasives oxidizers
  • complexing reagents etching chemicals
  • the oxidizer in the polishing solution oxidizes the surface of the metallic material while the oxidized metallic material is removed chemically and mechanically by abrasion due to the friction with the pad or the abrasive powder or both.
  • Etching chemicals can be used to increase the polishing rate of the metallic material.
  • a wafer holder positions and presses a wafer against a belt shaped polishing pad while the pad is moved continuously in the same linear direction relative to the wafer.
  • the so called belt shaped polishing pad is movable in one continuous path during this polishing process.
  • These conventional polishing processes may further include a conditioning station positioned in the path of the polishing pad for conditioning the pad during polishing. Factors that need to be controlled to achieve the desired flatness and planarity may include polishing time, pressure between the wafer and pad, speed of rotation, slurry particle size, polishing solution feed rate, the chemistry of the polishing solution, and pad material.
  • the invention overcomes the identified limitations with conventional chemical mechanical polishing and provides a technique for polishing multiple layers of a workpiece
  • a plurality of layers of a semiconductor wafer is polished using the same pad This is achieved by supplying different polishing solutions when polishing each layer of a differing composition
  • a copper layer is first polished using a first polishing solution delivered to the pad Afterwards, a barrier layer of the same wafer is polished using a second polishing solution delivered onto the same pad After each layer is polished, both the pad and/or wafer may be cleaned by using a rinse with or without a subsequent blow or spinning process to remove excess solution
  • the copper and barrier layer removal may be performed in an integrated CMP system using multiple polishing pads or multiple portions of a single polishing pad Further, multiple polishing solutions may be combined with multiple polishing pads to optimise polishing efficiency
  • a plurality of layers of a semiconductor wafer is polished using different polishing solutions in different CMP stations
  • a copper layer is first polished using a first polishing solution delivered to a pad in a first CMP station Afterwards, a barrier layer of the same wafer is polished using a second polishing solution in a second CMP station
  • Figure 1A illustrates a cross-section of a semiconductor wafer before depositing a copper layer on it
  • Figure IB illustrates a cross-section of the semiconductor wafer shown in Figure
  • Figure 1C illustrates a cross-section of the semiconductor wafer in Figure IB after polishing the copper layer in accordance with one or more embodiments of the invention
  • Figure ID illustrates a cross-section of layers of the semiconductor wafer in Figure
  • Figure I E is a flowchart of one or more embodiments of the invention which use two different polishing solutions on the same pad
  • Figure IF is a flowchart of one or more embodiments of the invention which use three different polishing solutions on the same pad,
  • Figure 2 illustrates a cross-section of the semiconductor wafer shown in Figure
  • Figure 3 is a flowchart of at least one embodiment of the invention using separate polishing solution lines
  • Figure 4 is a flowchart of at least one embodiment of the invention using separate polishing solution lines
  • Figure 5 is a flowchart of at least one embodiment of the invention using a component line and oxidizer line,
  • Figures 6A-B illustrate a side view and a plan view of a polishing station configured in accordance with one or more embodiments of the invention
  • Figures 7 A-B illustrate a detailed view of wafer polishing using a single pad according to one or more embodiments of the invention
  • Figure 8 depicts a block diagram of an integrated CMP system having multiple
  • Figure 9 is a flowchart of an embodiment of method of polishing copper and barnei layers of a semiconductor wafer using an integrated CMP system having multiple CMP stations, such as the CMP system described with reference to Figure 8 DETAILED DESCRIPTION
  • the invention is directed to a method and apparatus for chemical mechanical polishing of multiple layers of a workpiece such as a semiconductor wafer.
  • the various techniques described herein may involve a single polishing pad or multiple polishing pads. Additionally, the techniques may involve a single polishing solution or multiple polishing solutions. Further, a single portion of a polishing pad or multiple portions of a single polishing pad (each portion having a different composition) may be utilized.
  • the term “polishing pad” is interchangeable with the terms “polishing member” and “polishing belt”.
  • the terms "wafer”, “semiconductor wafer", “workpiece”, and “substrate” are interchangeable.
  • a first type of polishing solution is supplied for polishing a first layer such as a copper layer. Once the endpoint of the copper layer is reached, the supply of the first type of polishing solution is stopped and the wafer and the pad are rinsed. In the context of this application, the endpoint can be described as having been achieved when a given layer is removed from the top of the underlying layer and the underlying layer is exposed.
  • a second type of polishing solution is then supplied for polishing a second layer such as a barrier layer on the same pad.
  • a first type of polishing solution is supplied on the pad to polish the copper layer partially at high speed.
  • a second type of polishing solution is then supplied to remove the rest of the copper layer.
  • a third type of polishing solution is subsequently used to remove the barrier layer.
  • the polishing solution can be either various polishing agents without abrasive particles or slurries with abrasive particles, depending upon the type of pad used for polishing and the desired type of polishing.
  • the polishing pad can contain abrasives embedded in the front side of the pad with polishing agents that do not contain abrasive particles being introduced, or can use a polishing pad that does not contain such embedded abrasives and instead uses a slurry, or can use some other combination of belt, slurry and/or polishing agents.
  • the polishing solution may include a chemical that oxidizes the material that is then mechanically removed from the wafer, as is described further hereinafter, as well as may contain abrasive particles made from colloidal silica or fumed silica.
  • the polishing agent or slurry generally grows a thin layer of silicon dioxide or oxide on the front surface of the wafer, and the buffering action of the pad mechanically removes the oxide. As a result, high profiles on the wafer surface are removed until an extremely flat surface is achieved. [0033] Referring back to the first embodiment, after reaching the endpoint of the copper layer polishing, supply of the first type of polishing solution is discontinued so that polishing of the barrier layer commences with the second type of polishing solution.
  • polishing solution lines are embodied in a polishing solution distribution system.
  • FIG. 1A illustrates a portion of an exemplary substrate 11 that usually includes a silicon wafer.
  • the illustrated portion of substrate 1 1 includes a patterned insulating layer 14 or field comprising a dielectric material. Cavities 16 or features such as trenches and vias are formed in the insulating layer 14 by etching away portions of the insulating layer using well known techniques. The features 16 may expose portions of the substrate surface.
  • a barrier layer 15 such as Ta or TaN or Ta/TaN stacked layer is formed in the cavities 16 and on top surface 17 of the insulating layer or field surface.
  • the barrier layer may have a thickness on the order of 200- 300 A.
  • the barrier layer 15 is lined with a thin copper seed layer to initiate copper growth on the barrier layer.
  • a planar conductive layer 12, such as a copper layer, is formed, using an ECMD (Electrochemical Mechanical Deposition) process, over the copper seed layer.
  • the thickness of the copper layer 12 is about 1000 A.
  • Figures IB exemplifies a beginning substrate having a planar copper layer that is produced using an ECMD process.
  • An example ECMD process is disclosed in US patent No. 6, 176,992 entitled “Method and apparatus for electro-chemical mechanical deposition” issued January 23, 2001 and commonly owned by the assignee of the present application.
  • Use of a substrate with a planar copper layer as a beginning substrate is just for the purpose of exemplification.
  • the inventive process as will be shown in Figure 2, can also use beginning substrates having a thick conformal copper layer that is produced using a conventional electrodeposition process such as ECD (Electro Chemical Deposition) and is within the scope of the present invention.
  • ECD Electro Chemical Deposition
  • Figures 1C and ID exemplify later stages of the polishing process of such beginning samples that are shown in Figures IB and 2.
  • the polishing process of the present invention uses a single polishing belt or pad (abrasive or non-abrasive) throughout the polishing process.
  • the barrier layer 15 and copper layer 12 are polished using the same polishing pad or belt (not shown).
  • the pad first polishes and removes copper layer 12 from the wafer 1 1 until reaching its "endpoint” and then removes the barrier layer 15 up to its "endpoint".
  • the endpoint of the copper layer 12 may be defined as the first instance along the layer 12 when the barrier layer 15 is reached during polishing.
  • the endpoint of the barrier layer 15 may be defined as the first instance at which the top 17 of field 14 is reached during polishing.
  • a predetermined amount of over-polish may be carried out in either or both cases to eliminate any possible residues of materials on the wafer surface.
  • the copper layer 12 is polished by a pad (not shown) by delivering onto the pad a first type of polishing solution (described below).
  • the chemical reactions in the first type of polishing solution in conjunction with the mechanical abrasive action of the pad upon copper layer 12 removes copper layer 12.
  • the removal of copper layer 12 occurs until its endpoint is reached, which is defined as the start of barrier layer 15 beneath it.
  • the resulting wafer 1 1 is shown in Figure lC.
  • the barrier layer 15 and the features 16 remain while the copper layer 12 has been removed up to level of the barrier layer 15.
  • a second type of polishing solution one that is better suited to polishing of the barrier layer than the first type of polishing solution, is supplied for barrier layer 15 polishing (block 140).
  • the second type of polishing solution is disposed on the polishing pad and the polishing of the barrier layer is performed.
  • the polishing of the barrier layer using the second type of polishing solution continues until the endpoint of the barrier layer 15 is reached (checked at block 150).
  • the second type of polishing solution is switched off (block 160). Removal of the polishing solution from the pad may be achieved by a high pressure rinse and/or air blow method similar or identical with that used to clean off the first type of polishing solution.
  • the wafer 1 1 is then rinsed and spun top remove excess solution.
  • the chemical mechanical polishing of the wafer 1 1 is considered complete and the wafer is ready for the next processing step.
  • the next wafer (or group of wafers) can then be loaded (block 170).
  • the process 10 then repeats with the new wafer (or group) in accordance with blocks 100 tlirough 160.
  • a novel feature of the invention is that the same pad is used for both the copper and barrier layers 12 and 15, respectively. Furthermore, a cleaning step is performed in between to avoid complications of non-compatibility between a first polishing solution and a second polishing solution.
  • the types of pads available for such polishing may vary widely. Such pads include fixed abrasive pads and nonabrasive pads, depending on the desired polishing effect and chemical solution used. Either pad may be used for polishing both the copper and barrier layers, but in each case, the composition of the polishing solutions used may or not be the same.
  • the copper layer 12 may be a planar copper film.
  • planarized thin copper film may indicate a film that is planar with a thickness on the order of less than 3000 angstroms.
  • the polishing pad may be a fixed abrasive type pad such as MWR66 pad from 3M Corporation.
  • the polishing solution for polishing copper could be an abrasive free solution such as the CPS-08 solution also from 3M Corporation, although a solution with an abrasive therein can also be used
  • a modified polishing solution available from EKC (Polishing solution 9030) together with a reduced abrasive of 2% or less (down from the typical 5%) may be used, although other polishing solutions, with or without abrasives can be used
  • the modification of the EKC 5 solution includes an increase in the pH of the solution from 4 0 to 5 5 The increased pH may be achieved, for instance, by adding ammonium hydroxide or hydioxylamine If the pad used is to be a regular polymeric pad, such as Thomas West 711, then the same polishing solutions, CPS-08 solution and a modified EKC with 2% abrasive, for copper and tantalum, respectively, can still be used
  • the above piocess can also be performed using more than two polishing solutions, for example using two different polishing solutions for the copper polishing and one polishing solution for the barrier layer polishing
  • This process can also be implemented using the CMP apparatus shown in Figuies 6A-B Figure IF is a flowchart 20 describing a CMP process embodiment using three polishing solutions on the same pad
  • an individual wafer or even, a group of wafers if a parallel polishing system is implemented
  • a first type of copper polishing solution is supplied for fast copper layer polishing (block 710)
  • Chemical mechanical polishing with the first type of copper polishing solution (which rapidly polishes the copper) continues until the endpoint of the copper layer 12 is reached (checked at block 720)
  • the first type of copper polishing solution is turned off and subsequently the cleaning of the wafer and the pad is carried out (block 730)
  • the first polishing step may be timed to remove most of the copper using the first type of copper polishing solution, leaving behind only 500-2000 angstrom thick layer, which is then polished off using the second type of copper polishing solution.
  • the second type of copper polishing solution typically has a lower polishing rate than the first type of copper polishing solution, and it leaves behind a smoother copper surface with less number of defects.
  • a third type of polishing solution for the polishing of the barrier layer 15 is delivered on the pad (block 760) and the polishing of the barrier layer is performed.
  • the polishing of the barrier layer using the third type of polishing solution continues until the endpoint of the barrier layer 15 is reached (checked at block 770).
  • the third type of polishing solution is turned off, and the pad and the wafer are cleaned (block 780). Removal of the remains of the polishing solution from the pad may be achieved by a high pressure rinse with DI water and following air blow method similar or identical with that used to clean off the copper polishing solutions.
  • the wafer 11 may also be rinsed and spun.
  • the chemical mechanical polishing of the wafer 11 is considered complete and the wafer ready for the next processing step.
  • the next wafer (or group of wafers) can then be loaded (block 790).
  • the process 70 then repeats with the new wafer (or group) in accordance with blocks 700 through 790 shown in Figure IF.
  • the same pad is used to remove both the copper 12, and the barrier 15, layers by using multiple polishing solutions.
  • fixed abrasive pads and regular pads or polymeric pads can be used for this purpose. Either pad may be used for polishing both the copper and barrier layers, but in each case, the composition of the polishing solutions used may or not be the same.
  • the polishing pad may be a fixed abrasive type of pad such as MWR66 pad from 3M Corporation.
  • the first type of copper polishing solution may be an abrasive free solution with high removal rate, such as the CPS-1 1 solution also from 3M Corporation.
  • the copper removal rate of the CPS-1 1 solution is approximately 4000 A per minute at about 1 psi of pressure applied to the wafer surface by the pad.
  • After polishing with the CPS- 1 1 there maybe some copper residues left on the barrier layer or certain thickness of copper may be intentionally left on the surface.
  • Such residues may be polished off using the second type of copper polishing solution that should work mainly on the remaining residues but should have minimum etching effect on the copper that is in the features This way dishing may be minimized
  • the second type of copper polishing solution may be an abrasive free solution with low copper removal rate, such as the CPS-12 solution from 3M Corporation
  • the copper removal rate of the CPS-12 solution is approximately 1000 A per minute and removes copper residues from the top of the barrier layer
  • the modified polishing solution available from EKC together with a reduced abrasive of 2% or less may be used as discussed before
  • the modification of the EKC solution includes an inciease in the pH of the to solution from 4 0 to about 5 5
  • the increase of pH may be achieved, for instance, by adding ammonium hydroxide or hydroxylamine
  • the pad used is to be a regular polymeric pad, such as Thomas West 71 1, then the same polishing solutions, CPS-1 1, CPS-12 and a modified EKC with 2% abrasive, for copper and tantalum polishing, respectively, can still be used
  • Figure 2 illustrates another beginning substrate to exemplify the process of the present invention
  • Copper layer 12' is formed, using a conventional conformal deposition process, over the copper seed layer
  • the conductive layer 12' is fo ⁇ ned by depositing copper to a thickness that is about 1 5-2 00 times the depth of the features 16'
  • the copper layer 12' and the barrier layer 15' of the wafer 1 1 ' may be polished away using the above or below described embodiments as in the case of polishing the wafer 1 1 with planar copper layer 12
  • Various stages of the polishing process also progresses as exemplified in Figures 1C and ID above.
  • FIG 3 is a flowchart of at least one embodiment of the invention using separate polishing solution lines.
  • Process 20 is one way of implementing process 10 (of Figure IE) using two separate polishing solution lines.
  • a wafer (or group of wafers) is positioned for polishing (block 200).
  • a first polishing solution line, polishing solution line #1 is turned on in order to supply polishing solution to the polishing pad (block 210), see also Figures 6A-B.
  • the polishing solution supplied by the polishing solution line #1 (for instance, CPS-08) would be used to polish the copper layer 12 down to its endpoint.
  • the polishing solution line #1 would be turned (kept) on until the copper endpoint is reached (checked at block 220).
  • polishing solution line #1 is turned off (block 230).
  • the head holding the wafer may be lifted above the pad and a de-ionized (DI) water rinse is applied to the wafer which then bounces off the wafer surface and falls onto the pad (block 235).
  • DI de-ionized
  • the wafer 1 1 is spun and, if desired, excess solution removed by blowing a fluid such as air (block 235).
  • polishing solution line #2 is turned on
  • polishing solution line #2 The polishing solution supplied by the polishing solution line #2 would be used to polish the barrier layer 15 (such as tantalum) from the wafer The polishing solution line #2 would be turned (kept) on until the bai ⁇ er layer 15 endpoint is reached (checked at block 250) Once the endpoint is reached, polishing solution line #2 is turned off (block 255) In order to clean the pad and wafer 1 1 of the polishing solution from line #2, the head holding the wafer is now lifted above the pad and a DI water rinse is applied to the wafer 1 1 (block 260) Then wafer can be spun to remove excess solution The water from the rinse bounces off the wafer 1 1 and falls onto the pad thereby cleaning it Then the pad is blown to remove excess solution Once the pad and wafer 11 are cleaned, the next wafer (or gioup) is loaded (block 270) and process 20 is repeated from block 200 on for the newly loaded wafer(s)
  • FIG. 4 is a flowchart of at least one embodiment ol the invention using separate polishing solution lines
  • Process 30 is anothei polishing process using the same pad and two separate polishing solution lines
  • a wafer (or group of wafers) such as wafer 1 1 is positioned for polishing (block 300)
  • both polishing solution lines, polishing solution line #1 and polishing solution line #2 are turned on in order to supply polishing solution to the polishing pad (block 3 10), see also Figures 6 A-B
  • the components supplied by the polishing solution lines 1 and 2 would be used to polish the copper layer 12 from the wafer 1 1
  • the polishing solution line #1 supplies an oxidizer (such as hydrogen peroxide)
  • Polishing solution line #2 supplies a complexing reagent and inhibitor but no oxidizer
  • Complexing reagents include chemicals such as organic acids and amines while the inhibitor is typically benzot ⁇ azolc (BTA)
  • BTA benzot ⁇ azolc
  • polishing solution lines #1 and #2 would be turned (kept) on until the copper endpoint is reached (checked at block 320) Once the endpoint is ieached, polishing solution line #1 is turned off (block 330) Since the polishing solutions in polishing solution lines #1 and #2 are somewhat compatible, a DI rinse cleaning and then spinning of the wafer or air blowing on the pad to remove the previous solution and DI rinse are optional but may not be needed Polishing solution line #2 would thus remain on The polishing solution supplied by the polishing solution line #2 would be used to polish the barrier (tantalum) layer 15 from the wafer 1 1 Once the tantalum endpoint is reached, polishing solution line #2 is turned off (block 355) In order to clean the wafer of the polishing solution from line #2, a DI water rinse and subsequent spinning to remove excess solution is applied (block 360) Once the wafer and pad are cleaned, the next wafer (or group) is loaded (block 370) and process 30 is repeated from block 300 on for the newly loaded wafer(s)
  • FIG. 5 is a flowchart of at least one embodiment of the invention using a component line and oxidizer line
  • Process 40 is another polishing process using the same pad and two separate lines, one containing polishing solution and the other, an oxidizer A wafer (or group of wafers) is positioned for polishing (block 400) Then, both lines, the polishing solution line and oxidizer line, are turned on in order to supply polishing solution and oxidizer to the polishing pad (block 410) The components supplied by the polishing solution line and the oxidizer line would be used to polish the coppei layer 12 from the wafei
  • the polishing solution line supplies a complexing reagent and inhibitor
  • the oxidizer line supplies an oxidizer such as hydrogen peroxide
  • the removal (polishing) of copper increases with the increasing oxidizer concentration and reaches a peak The removal of tantalum however, is less dependent on oxidizer concentration and depends more upon mechanical abrasion
  • the polishing solution line and oxidizer line would be turned (kept
  • the oxidizer line is turned off (block 430). Since the solutions in the polishing solution and oxidizer lines are somewhat compatible, a DI rinse and spin of the wafer and air blowing of the pad may not be needed. The polishing solution line would still remain on. The polishing solution supplied by the polishing solution line would then be used to polish the tantalum layer down to its endpoint (the top of the field). Once the tantalum endpoint is reached, polishing solution line is turned off (block 455). Some over-polishing beyond the endpoint may be used to clear possible residue. In order to clean the wafer, a DI water rinse is applied to the wafer while the wafer is spinning (block 460). This also impacts upon and cleans the pad. Once the pad and wafer are cleaned, the next wafer (or group) is loaded (block 470) and process 40 is repeated from block 400 on for the newly loaded wafer(s).
  • FIGS 6A-B illustrate a side view and a plan view of a polishing station configured in accordance with one or more embodiments of the invention.
  • the wafer polishing station 50 includes a number of polishing components and a wafer housing 540 or wafer carrier head.
  • the wafer housing 540 securely positions a wafer 550 so that a front face 560 of the wafer is fully exposed.
  • the polishing station 50 includes a polishing pad 510 for polishing the front face 560, a mechanism (not shown) for driving the polishing pad 510 in a bi-directional linear or reciprocating (forward and reverse) motion, and a support plate 520 for supplying a fluid support to the back side of the pad 510 as the pad 510 polishes the exposed wafer surface 560.
  • Bidirectional linear motion is also known as reverse linear motion.
  • the underside of the polishing pad 510 may be additionally attached to a flexible but firm material (not shown) for supporting the pad 510.
  • the polishing pad 510 is used to polish both copper and barrier (e.g. tantalum) layers of face 560.
  • the use of a single pad for both layers of exposed wafer surface 560 eliminates the need for separate use of multiple pads and also, perhaps, of multiple polishing stations.
  • the polishing pad 510 may be abrasive free such as a polymeric pad or may be a fixed abrasive pad. Since tantalum and copper layers have differing characteristics, if the same pad is to be used for polishing both, different polishing solutions would have to be used.
  • a bi-directional linear polisher as described is preferably used as the polishing station 50, such as described in U.S. Patent No. 6,103,628 and U.S. Patent Application No. 09/684,059, both of which are hereby expressly inco ⁇ orated herein by reference.
  • the polishing pad is preferably a belt that has a portion of the belt in the processing area that moves in a bidirectional direction, which may or may not contain fixed abrasives thereon, and which is preferably levitated in a polishing area above a platen support Further, the belt may be incrementally moved, so that the same belt, but a different portion of the belt (which different portion may or may not overlap with the previously used portion in the processing area) is used at different times, which different times may or may not be distinguished by the type of processing solution being used
  • polishing station is presently preferred, the present invention, howevei, is not limited to using such a polishing station Rathci, the processes described herein can be used with other CMP polishing stations, including those that use a linearly rotating belt, a stationary polishing pad with a moving wafer, a rotating polishing pad that moves against a stationary or rotating wafer, or others Further, pads that are thin with little rigidity, as well as pads that are thicker or more rigid can be used, depending upon the desired effect There may or may not be supporting plates behind the pads [0061]
  • the polishing solutions and rinsing solution used during the polishing are preferably supplied to both sides of the polishing station 50 that uses a bi-directional linear polisher by two or more polishing solution lines, such as line #1 and line #2
  • polishing solution line #1 comprises a left-side supply line 12 and right side supply line 51 1
  • polishing solution line #2 comprises a left-side supply line 514 and right
  • polishing solution line #1 is turned on to supply polishing solution to the right and left sides of the pad 510.
  • right side supply line 51 1 and left side supply line 512 will be actively providing polishing solution to the pad 510.
  • Right side supply line 513 and left side supply line 514 would be off.
  • the pad 510 is driven by mechanism 530 and this motion, coupled with the chemical reactiveness of the polishing solution from polishing solution line #1 upon the surface 560 of wafer 550, serves to polish copper from surface 560.
  • polishing solution delivery can also be coupled with the motion of the pad.
  • polishing solution may be delivered from nozzle 51 1 as the pad moves to the left and delivered from nozzle 512 when the pad is moving to the right In this way, the delivered polishing solution is always moved towards the wafer by the moving pad. Waste of polishing solution is minimized.
  • the polishing solution line #1 will be turned off. This entails cutting off or deactivating supply lines 51 1 and 512.
  • a de-ionized water nozzle injects water to the wafer surface when the wafer is lifted above the pad.
  • polishing solution line #2 will be turned on, and thus right side supply line 513 and left side supply line 514 would be actively providing polishing solution to the right and left sides, respectively, of pad 510.
  • the polishing solution supplied in polishing solution line #2 is designed for the polishing of the barrier (e.g. tantalum) layer. The motion of pad 510 and polishing solution from polishing solution line #2 against the surface 560 serves to polish tantalum from the surface 560 of wafer 550.
  • polishing solution line #2 is turned off (supply lines 513 and 514 are deactivated), the pad is cleaned (using rinser 570) and excess solution is removed using blower 580) and the next wafer is loaded into housing 540 for polishing.
  • Rinser 570 and blower 580 may be implemented in a variety of ways including by use of high-pressure nozzles.
  • polishing solution line #1 would supply a complexing reagent, an inhibitor and an oxidizer.
  • polishing solution line #2 would supply a complexing reagent and inhibitor, but no oxidizer or very low concentration of oxidizer.
  • both polishing solution lines #1 and #2 could be turned on (and hence all four supply lines 51 1, 512, 513 and 514 would be on) during the polishing of copper After copper polishing, polishing solution line #1 could be turned off, leaving active (on) only supply lines 513 and 514 of polishing solution line #2
  • polishing solution line #2 would carry the complexing reagent and inhibitor while polishing solution line #1 would carry just the oxidizer
  • both lines #1 and #2 could be turned on during copper polishing and then polishing solution line #1 could be turned off for tantalum polishing
  • Figures 7A-B illustrate a detailed view of wafer polishing using a pad as described in the above embodiments Referring back to Figui e IB wafer 1 1 that is to be polished has plurality of layers, including a copper layer 12 and a barrier layer 15 Prior to polishing, an exposed front face 645 will expose the copper layer 12 to polishing first After the copper layer 12 has been polished, the resulting wafer 11 will expose the barrier layer 15
  • polishing solution line #1 comprises a left side supply line 612 and right-side supply line 61 1
  • polishing solution line #2 comprises a left side supply line 614 and right-side supply line 613
  • Supply lines 611 and 613 supply the right-side of the polishing pad 640 while supply lines 612 and 614 supply the left side of the polishing pad 640
  • a polishing solution from line #1 containing a chemicals that oxidize and chemically mechanically remove copper layer 12 of surface 645 is supplied between the wafer 1 1 and the polishing pad 640 After copper layer 12 is polished, polishing solution line #1 is turned off The wafer 1 1 is raised above the pad 640 as shown in Figure 7B While the wafer 11 is in the position shown in Figure 7B, a deionized water rinse (containing 0-0 01% corrosion inhibitor) from rinser 670 cleans the polishing solution from the wafer 1 1 and then cleans the polishing solution from the pad 640 by bouncing off of the wafei 1 1 (upon its front surface 645) and onto the pad The water which cleans the pad may remain on the pad which may adversely dilute the next polishing solution The blower 680 blows an onto the pad to minimize the dilution of the next polishing solution [0068] After cleaning, the wafer 1 1 returns to the position shown in Figure 7A Then polishing solution line #2 is turned on supplying polishing
  • removal of the copper layer may be performed before barrier layer removal.
  • bulk copper may be removed down to barrier layer using a fixed abrasive polishing pad.
  • the polishing solution may or may not contain particles.
  • the fixed abrasive polishing pad may be used in combination with a polishing solution with solid particles to remove the remaining copper layer from the surface of the barrier layer while a down force is applied to the workpiece. This downforce may be a relatively low down force.
  • the barrier layer is removed. Removal of the barrier layer may utilize a portion of the polishing pad that is made a soft polymer.
  • the polishing pad may have one portion that has a fixed abrasive and a second portion that is made of a soft polymer.
  • a tantalum selective polishing solution may be delivered to the polishing pad to remove the barrier layer while a low down force is applied to the work piece.
  • removal of the copper and barrier layers may be performed using an integrated CMP system (integrated CMP tool) on separate polishing pads.
  • the different pads are located in separate CMP stations within the same one tool.
  • An exemplary CMP station suitable for use in the integrated CMP system is described above with reference to Fig. 6A and also with reference to "Advanced Chemical Mechanical Polishing System with Smart Endpoint Detection", U.S. Ser. No. 10/346,425 filed January 17, 2003 (NT-278-US), inco ⁇ orated herein by reference.
  • FIG. 8 depicts a block diagram of an integrated CMP system 800 having multiple CMP stations, according to an embodiment of the invention.
  • the integrated CMP system 800 has a first CMP station 810 and a second CMP station 820.
  • the first CMP station 810 in a first polishing sequence, the copper layer is removed using a first polishing pad (not shown) and a first polishing solution.
  • the first polishing pad is a fixed abrasive polishing pad and the first polishing solution contains abrasive and/or lubricating particles.
  • the abrasive particles may act as a lubricant for polishing when combined with the fixed abrasive polishing pad.
  • Abrasive particles are solid particles in a slurry.
  • the wafer is lowered onto the first polishing pad and the first polishing solution is delivered onto the first polishing pad.
  • the first polishing pad is moved over the support plate (see Figure 6A) while a fluid pressure is applied under the first polishing pad.
  • a barrier layer removal process (second polishing sequence) is performed in the second CMP station 820.
  • the second CMP station 820 has a second polishing pad (not shown) and uses a second polishing solution.
  • the second polishing pad may be a polymeric / non-fixed abrasive polishing pad.
  • the second polishing pad may be made of a soft polymeric material such as polyurethane.
  • a selective polishing solution is used as the second polishing solution during the barrier layer removal process.
  • the selective polishing solution is delivered onto a polymeric polishing pad suitable for barrier material removal and the pad is moved for polishing.
  • a fluid pressure may be applied under the second polishing pad. Using these techniques may minimize the stress on the wafer and resulting delamination. These techniques also may minimize dishing and scratches.
  • the use of two CMP stations in the integrated CMP system is exemplary only. Integrated CMP systems with additional CMP stations are also contemplated.
  • FIG. 9 is a flowchart of an embodiment of a method of polishing copper and barrier layers of a semiconductor wafer using an integrated CMP system having multiple CMP stations, such as the CMP system described with reference to Figure 8.
  • a first layer of a semiconductor wafer is polished using a polishing solution on a first portion of polishing pad.
  • the first layer is comprised of copper.
  • a second layer of the semiconductor wafer is polished using a polishing solution on a second portion of polishing pad.
  • the second layer is comprised of tantalum. It shall be understood that more than two layers can be polished, and more than two portions of polishing pad may be used.
  • the polishing solutions used to polish the different layers may be the same polishing solution or different polishing solutions.
  • the different portions of polishing pad may be located on the same polishing pad or on different polishing pads.
  • the respective polishing solution and polishing pad are preferably designed and/or suited for polishing a particular layer of the wafer.
  • the solution and pad may be suited to polish copper, or suited to polish a barrier layer, such as tantalum.
  • wafer surface and “surface of the wafer” include, but are not limited to, the surface of the wafer prior to processing and the surface of any layer formed on the wafer, including oxidized metals, oxides, spun on glass, ceramics, etc.
  • any number and manner of to layers may be polished using the techniques described herein such as a fixed abrasive pad by supplying number of polishing solutions as appropriate for each of those layers. It shall be understood that removing a layer from the surface of a semiconductor wafer is synonymous with polishing a layer on the surface of the semiconductor wafer.
  • the terms “block” and “step” both refer to a processing step.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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EP03720656A 2002-03-13 2003-03-13 Verfahren und gerät zum integrierten chemisch-mechanischen polieren von kupfer- und barriereschicht Withdrawn EP1483785A1 (de)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US346425 1994-11-29
US36500102P 2002-03-13 2002-03-13
US365001P 2002-03-13
US199471 2002-07-19
US10/199,471 US20040014399A1 (en) 2002-07-19 2002-07-19 Selective barrier removal slurry
US41754402P 2002-10-10 2002-10-10
US417544P 2002-10-10
US10/346,425 US6857947B2 (en) 2002-01-17 2003-01-17 Advanced chemical mechanical polishing system with smart endpoint detection
PCT/GB2003/001066 WO2003079428A1 (en) 2002-03-13 2003-03-13 Method and apparatus for integrated chemical mechanical polishing of copper and barrier layers

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TW200308007A (en) 2003-12-16

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