200308007 玖、發明說明 【相關申請案】 本案爲2003年1月17日申請的美國專利申請案序號 10/346,425(NT-278-US)和2002年7月19日申請的美國專利 申請案序號10/199,471(NT-258-US)的部份接續案，其全都 倂於此以爲參考。 本案主張基於2002年10月10日申請的美國專利臨時 申請案第60/417,544號（NT-278-P2)和2002年3月13日申 請的美國專利臨時申請案第60/365,001號（NT-237-P)的優先 權，其全都倂於此以爲參考。 【發明所屬之技術領域】 本發明係關於化學機械拋光的領域。尤其本發明係關 於銅和阻障層兩者之整合拋光的方法和設備。 【先前技術】 傳統的半導韹元件一般包括半導體基板（通常是矽基板) 以及多個依序形成的介電層（例如二氧化矽）和導電材料做的 導電路徑或交互連結。因爲銅和銅合金的優異電子遷移性 和低電阻特性，所以它們最近已受到相當的注意以做爲交 互連結的導體。交互連結通常是以金屬化的過程將銅塡入 蝕刻於介電中介層裡的特徵或空穴而形成。銅金屬化過程 的較佳方法是電鍍。在積體電路中，多層次的交互連結網 路相對於基板表面而側向地延伸。形成於序列中介層裡的 交互連結可以使用導通孔或接點而電連接。 在一典型的過程中，首先在半導體基板上形成絕緣中 200308007 介層。進行圖案化和蝕刻過程，以於絕緣層中形成例如溝 槽、導通孔或雙重金屬鑲嵌（dual damascene)結構等特徵。 然後電鍍銅以塡充所有的特徵。然而，鍍的過程導致特徵 裡有銅層，也導致基板表面上有銅層。然後在後續處理步 驟之前移除表面上負擔過多的銅。 傳統上在圖案化和蝕刻之後，絕緣層會先披覆以阻障 層，其典型爲鉅或钽/氮化鉬複合層。阻障層披覆住導通 孔和溝槽以及絕緣層的頂面以確保有良好的附著，並且做 爲阻障材料以避免銅擴散到半導體元件中和穿過絕緣層。 其次在阻障層上沉積種子（導電）層，其通常爲銅層。種子層 形成了導電材料基底，以供後續銅沉積期間的銅膜成長。 隨著電鍍上銅膜，銅層快速地塡充了導通孔，但以保形的 方式披覆了寬的溝槽和表面。當持續此沉積過程以確保溝 槽也被塡滿時，在基板上就形成了厚的銅層或多餘負擔。 傳統上在鍍銅之後，採用 CMP(chemical mechanical polishing ，化學機械拋光）過程來全面平坦化，並且把銅層的厚度降 低到阻障層表面的高度。爲了電性隔離已塡充銅的特徵， 然後以另一 CMP步驟來移除阻障層。 在半導體產業中，VLSI(Very Large Scale Integration， 極大型積體電路）和 ULSI(Ultra Large Scale Integration，超 大型積體電路）應用之半導體晶圓的化學機械拋光（CMP)具 有重要而廣泛的用途。CMP是半導體晶圓平坦化和拋光的 過程，其結合了例如絕緣體和金屬等層的化學移除以及晶 圓表面的機械衝擊。CMP也用於晶體成長之後和晶圓製程 200308007 期間的晶圓平坦化/拋光，並且是提供晶圓表面全面平坦 化的過程。舉例而言，在積體電路製程期間，CMP常用於 平坦化/拋光於多層次金屬交互連結體系中所累增的輪廓 。必須在不污染所要表面下達成晶圓表面所要的平坦度。 同時，CMP過程必須避免拋光弄掉有作用的線路零件部份 〇 現在要描述半導體晶圓之化學機械拋光的傳統系統。 一種傳統的CMP過程需要把晶圓定位於握持物上，其繞著 第一軸旋轉，並且降到繞著第二軸做反向旋轉的拋光墊上 。在平坦化過程期間，晶圓握持物壓著晶圓抵住拋光墊。 在晶圓拋光期間，典型上會施加例如拋光劑或漿液的拋光 溶液至拋光墊。拋光溶液的內容物乃視CMP期間所要移除 的材料特性而定。舉例來說，如果該材料是金屬性的，則 拋光溶液可以由硏磨劑、氧化劑、錯合試劑（蝕刻化學品）、 抑制劑及/或表面活性劑當中任一者或多者所組成。拋光 溶液中的氧化劑氧化了金屬材料的表面，同時氧化的金屬 材料由於與墊子或硏磨粉末或兩者的摩擦所導致的硏磨而 被化學地和機械地移除。蝕刻化學品可以用來增加金屬材 料的拋光速率。 在另一種傳統的CMP過程中，晶圓握持物將晶圓定位 並且壓著晶圓抵住帶形的拋光墊，同時墊子在相對於晶圓 的相同線性方向上連續地移動。在此拋光過程期間，所謂 的帶形拋光墊可以在一連續的路徑上移動。這些傳統的拋 光過程可以進一步包括調理站，其定位於拋光的路徑中， 200308007 以於拋光期間調理墊子。須要控制以達到所要平坦度和平 面度的因素可能包括拋光時間、晶圓和墊子之間的壓力、 旋轉的速度、漿液的粒子尺寸、拋光溶液的進給速率、拋 光溶液的化學性質以及墊子的材料。 雖然上述的CMP過程爲半導體產業所廣泛使用和接受 ，但是仍然還有挑戰。由於須要接受拋光的銅、阻障物和 其他層所用的材料在性質上有差異，以致傳統的系統通常 包括用於不同層之不同的拋光溶液和不同類型的拋光墊。 這常常意味著銅層必須使用某一墊子來拋光，而阻障層必 須使用完全不同的墊子來移除。同時，墊子材料和拋光溶 液組成的差異可能造成非預期的副作用，例如在非目前拋 光的其他層中造成侵蝕或碟狀。此增加了拋光過程中的時 間、成本、缺陷比率和複雜度。 特定而言，拋光的技藝已經嘗試解決在鉬阻障層上之 銅層的拋光問題。應該注意的是：所有參照Ta阻障物的敘 述也可適用於TaN阻障物和Ta/ TaN堆疊。 先前技藝的CMP工具是複雜而昂貴的機器。需要整合 的拋光方法和設備，以用於同時有效拋光鉬和銅，而降低 成本和複雜度以及縮短拋光半導體晶圓所需的時間。 【發明內容】 本發明克服了所列之傳統化學機械拋光的限制，並且 提供了拋光多層工件的技術。 在本發明的一或多個具體態樣中，使用相同的墊子來 拋光半導體晶圓的多個層。此乃藉由當拋光不同組成的每 200308007 一層時，供應不同的拋光溶液而達成。在一具體態樣中， 使用傳送至墊子的第一拋光溶液而首先拋光銅層。之後， 使用傳送至相同墊子上的第二拋光溶液來拋光相同晶圓的 阻障層。每一層拋光之後，可以使用沖洗劑來淸潔墊子及 /或晶圓，接下來有或沒有吹氣或旋轉過程以移除多餘的 溶液。在另外可選擇的具體態樣中，可以在使用多個拋光 墊或單一拋光墊之多個部份的整合CMP系統中進行銅和阻 障層的移除。此外，多個拋光溶液可以結合多個拋光墊， 以使拋光效率最佳化。 在本發明的其他具體態樣中，於不同的CMP站中使用 不同的拋光溶液來拋光半導體晶圓的多個層。在一具體態 樣中，使用傳送至第一 CMP站之墊子的第一拋光溶液而首 先拋光銅層。之後，在第二CMP站中使用第二拋光溶液來 拋光相同晶圓的阻障層。 【實施方式】 本發明係針對例如半導體晶圓之工件的多層加以化學 機械拋光的方法和設備。在此所描述的多種技術可能牽涉 到單一拋光墊或多個拋光墊。此外，該等技術可能牽涉到 單一拋光溶液或多種拋光溶液。再者，可以利用拋光墊的 單一部份或單一拋光墊的多個部份（每一部份具有不同的組 成）。「拋光墊」（polishing pad)—詞可以與「拋光構件」 (polishing member)和「拋光帶」（polishing belt)等詞互換。 「晶圓」（wafer)、「半導體晶圓」（semiconductor wafer)、 「工件」（workpiece)和「基板（substrate)」等詞是可以互換 200308007 的。 在一具體態樣中，供應第一種拋光溶液以拋光例如銅 層的第一層。一旦抵達銅層的終點，則停止供應第一種拋 光溶液，並且淸洗晶圓和墊子。在此應用的背景下，當給 定層從底下層的頂端移除而暴露出底下層時，則可以描述 成已經達到該終點。然後供應第二種拋光溶液，以在相同 墊子上拋光例如阻障層的第二層。在另一具體態樣中，在 墊子上供應第一種拋光溶液，而以高速部份地拋光銅層。 然後供應第二種拋光溶液，以移除其餘的銅層。接下來再 使用第三種拋光溶液以移除阻障層。 關於所用的拋光溶液，拋光溶液可以是沒有硏磨粒子 的多種拋光劑，或者是具有硏磨粒子的漿液，此視用於拋 光的墊子類型和所要的拋光類型而定。舉例而言，拋光墊 可以包含嵌埋於墊子正面的硏磨劑，而引入不含硏磨粒子 的拋光劑；或者可以使用不含此種嵌埋硏磨劑的拋光墊， 並且轉而使用漿液；或者可以使用帶子、漿液及/或拋光 劑的一些其他組合。拋光溶液可以包括將材料氧化的化學 品，該材料然後從晶圓機械地移除，這在之後會進一步描 述；也可以包含由膠體狀二氧化矽或薰燒之二氧化矽所做 成的硏磨粒子。拋光劑或漿液一般在晶圓的正面上長出一 薄層的二氧化矽或氧化矽，並且墊子的衝擊作用機械地移 除該氧化物。結果移除了晶圓表面上的高輪廓，直到達成 極平的表面爲止。 回去參考第一個具體態樣，到達銅層的拋光終點以後 200308007 ，中斷供應第一種拋光溶液，如此以第二種拋光溶液開始 進行阻障層的拋光。這些和其他的具體態樣全都使用相同 墊子來拋光銅和阻障層兩者。進行這些和其他具體態樣的 設備乃一前一後地耦合並控制必需的拋光溶液線路。就本 發明某一方面而言，拋光溶液線路乃具體化於拋光溶液分 布系統中。 在討論本發明中，多種參考將會針對特定的銅層、阻 障層、拋光溶液、墊子以及其他的成分。此種參考祇是舉 例說明，因爲應該輕易地理解到：任何形式、方式和種類 的層、拋光溶液、墊子以及其他的成分可以依所要用途、 拋光系統及/或晶圓而適當地取代。舉例來說，在說明書 中，沉積的銅層和底下的種子層都常常稱爲銅層，而阻障 層則稱爲鉬層。此種敘述乃視所用的晶圓組成以及當時正 處理的諸層而定，並且不應該考慮爲以任何方式限制本發 明。 同時在描述本發明時，針對「相同墊子」（same pad)的 參考也可以包括一個墊子的不同部份，並且在所有例子中 ，「相同種類的墊子」（same type of pad)是指墊子的各個不 同部份（如果有的話）都有類似組成的墊子。當描述不同圖形 時’相似的參考數字會用來指示相似的構件和相似的結構 〇 圖la圖解說明通常包括矽晶圓之範例性基板n的一 部份。基板11的圖解說明部份包括圖案化的絕緣層14或 區域，其包括介電材料。例如溝槽和導通孔的空穴16或特 12 200308007 徵乃藉由使用熟知的技術，將部份的絕緣層14蝕去而形成 於絕緣層14中。特徵16可以暴露出部份的基板表面。例 如Ta或TaN或Ta/ TaN堆疊層的阻障層15乃形成於空穴 16中以及絕緣層14或區域表面的頂面17上。阻障層15的 厚度可以是在200〜300A的等級。雖然圖la〜Id並未顯示， 但是阻障層15乃襯以一薄銅種子層，以起始銅在阻障層15 上的生長。例如銅層的平面狀導電層12乃使用 ECMD(electrochemical mechanical deposition，電化學機械沉 積）法而形成於銅種子層上。舉例來說，銅層12的厚度大 約爲1000人。 圖lb示範了具有使用ECMD法所製造之平面狀銅層的 開始基板。ECMD法的範例乃揭示於2001年1月23日頒發 的美國專利第6，176,992號，其標題爲「電化學機械沉積的 方法和設備」（Method and Apparatus for Electro-Chemical Mechanical Deposition)，同樣爲本案的受讓人所丨維有。使用 具有平面狀銅層的基板做爲開始基板祇是基於舉例說明的 目的。本發明的方法（圖2將會顯示）也可以使用具有厚的保 形銅層之開始基板，該銅層係使用例如ECD(electro_ chemical deposition，電化學沉積）的傳統電丨几積過彳壬所製七 ，並且也是在本發明的範圍中。 圖lc和Id示範了圖lb和2所顯示的此種開始樣本之 拋光過程的稍後階段。本發明的拋光過程在整個1拋％ @程 中使用單一的拋光帶或墊（硏磨性或非硏磨性）° 根據本發明，阻障層15和銅層12乃使用相同的拋光 13 200308007 墊或帶（未顯示）所拋光。墊子首先拋光並移除晶圓11上的 銅層12，直到達到其「終點」爲止，然後移除阻障層15直 到其「終點」爲止。基於描述本發明之各種具體態樣的目 的，銅層12的終點可以定義成當拋光期間抵達阻障層15 時沿著該層12的第一情況。類似地，阻障層15的終點可 以定義成當拋光期間抵達區域14之頂端17時的第一情況 。應該注意到：在銅和阻障物移除的終點之後，在此任一 或兩個情形下可以執行預定量的過度拋光，以消除晶圓11 表面上任何可能的殘餘物。銅層12乃藉由將第一種拋光溶 液（底下有敘述）傳送到墊子上，而以墊子（未顯示）加以拋光 。第一種拋光溶液中的化學反應配合銅層12上之墊子的機 械硏磨作用，移除了銅層12。銅層12的移除一直發生到達 到其終點爲止，終點乃定義成其下阻障層15的開始。所得 的晶圓11乃顯示於圖lc。雖然銅層12已移除到阻障層15 的高度，阻障層15和特徵16仍保持著。 拋光銅之後，使用例如水的淸潔流體來簡單地淸潔晶 圓11表面和墊子表面。當淸潔時，晶圓11表面和墊子表 面可以是或不是分開的，但如果是分開的，則晶圓11表面 和墊子表面可以個別分開淸潔，而此種淸潔可以在參考之 後的淸潔中進行。淸潔以後，雖然晶圓11表面可以加以旋 轉或不旋轉以移除多餘的溶液，但是墊子上的多餘溶液最 好吹掉，以使其表面準備好接受不同的化學品。此時，第 二種拋光溶液可以配置於相同的墊子上。然後使用第二種 拋光溶液來拋光阻障層15，直到達到區域14的頂面Π爲 14 200308007 止。此拋光作用產生了平面化的晶圓11表面，如圖Id所 示。每一特徵16現在是彼此電性隔離的，並且頂面17是 平坦且平面狀’以供進一步處理。圖le是本發明之一或多 個具體態樣的流程圖。在半導體晶圓之化學機械拋光的過 程10中，個別的晶圓（如果採用平行的拋光系統，則或者 甚至是一群晶圓）必須先加以定位以便在墊子上拋光（方塊 100)。可以藉由載運頭或外罩來達成定位，其將晶圓定位 成極接近於拋光墊（見圖6a)。接下來在過程10中，供應第 一種拋光溶液以供銅層12拋光（方塊110)。在此過程期間 ，第一種化學拋光溶液乃配置於銅層12和拋光墊之間，如 此以化學地和機械地拋光此銅，同時晶圓11乃被壓住抵著 墊子。隨著晶圓11被壓住抵著拋光墊，拋光墊相對於晶圓 11的移動提供了銅表面12上的機械作用。 此機械作用結合拋光溶液的化學反應，拋光了銅表面 。載運頭的旋轉有助於拋光溶液的傳遞，也有助於在整個 銅層12上得到均勻的拋光速率。以第一種拋光溶液（其特 別適合銅的拋光）進行的化學機械拋光一直繼續到抵達銅層 12的終點爲止（在方塊120檢查）。一旦抵達銅層12的終點( 一旦阻障層15已經暴露出來），並且做了可選擇的過度拋 光，則淸除第一種拋光溶液（方塊130)。淸除墊子上的第一 種拋光溶液可以使用去離子（de-ionized，DI)水的高壓淸洗 及/或吹送空氣法（見底下）來達成。同時晶圓11本身可以 藉由去離子水淸洗，然後旋轉晶圓11來移除去離子水，而 得以分別地淸潔；晶圓11典型上仍是溼的，但是上面沒有 15 200308007 多餘的去離子水。 一旦淸除了第一種拋光溶液’則供應第二種拋光溶液( 其比第一種拋光溶液還適合阻障層15的拋光）以供阻障層 15拋光（方塊140)。第二種拋光溶液乃配置於拋光墊上’並 且進行阻障層15的拋光。使用第二種拋光溶液的阻障層15 拋光一直繼續到抵達阻障層15的終點爲止（在方塊150檢查 )。一旦抵達阻障層15的終點（一旦抵達區域14的頂面17) ，則關掉第二種拋光溶液（方塊160)。可以藉由類似或相同 於用來淸除第一種拋光溶液的高壓淸洗及/或吹送空氣法 ，來達成移除墊子上的拋光溶液。然後淸洗和旋轉晶圓11 以移除多餘的溶液。 晶圓11的化學機械拋光視爲完成了，並且晶圓11乃 準備好做下一個處理步驟。然後可以載入下一個晶圓（或一 群晶圓）(方塊170)。然後過程10根據方塊100到160以新 的晶圓（或群）來重複進行。 在一具體態樣中，本發明的新穎特色在於：使用相同 的墊子於銅層12和阻障層15兩者。此外，在之間進行淸 潔步驟，以避免第一拋光溶液和第二拋光溶液之間非相容 的複雜性。可用於此種拋光的墊子種類乃變化很廣。此種 墊子包括固定硏磨劑的墊子和非硏磨性的墊子，此視所要 的拋光效果和所用的化學溶液而定。可以使用上述兩類中 任一種墊子來拋光銅和阻障層兩者，但是在每一情形中， 所用之拋光溶液的組成可能是或不是相同的。 在過程10的範例中，銅層12可以是平面狀銅膜。注 16 200308007 意在此背景下，「平面化薄的」（planarized thin)銅膜可以是 指厚度在小於3000埃的等級而爲平面狀的膜。拋光墊可以 是固定硏磨劑型的墊子，例如得自3M公司的MWR66墊子 。對於此種固定硏磨劑的墊子而言，拋光銅的拋光溶液可 以是無硏磨劑的溶液，例如也得自3M公司的CPS-08溶液 ，雖然也可以使用當中有硏磨劑的溶液。爲了在相同的墊 子上拋光鉬，可以使用得自EKC之修改過的拋光溶液（9030 拋光溶液），同時硏磨劑（從典型的5%)降低到2%或更少， 雖然也可以使用有或沒有硏磨劑的其他拋光溶液。EKC 5 溶液的修改包括了溶液的pH從4.0增加到5.5。舉例而言 ，增加pH可以藉由添加氫氧化銨或羥胺而達成。如果所用 的墊子是一般的聚合墊’例如Thomas West 711，則仍然可 以分別使用相同的拋光溶液（CPS-08溶液和具有2%硏磨劑 之修改過的EKC)於銅和鉅。使用少量的硏磨劑（2%而非5%) 的一個優點是留在墊子上的副產物可以比較容易淸除。從 留在墊子上的漿液來看，非常高含量的硏磨劑可造成處理 的問題。如果無法從墊子上適當地淸除粒子和化學品，則 可能影響接在銅拋光步驟後面的阻障物拋光步驟。此外， 在拋光溶液之活性很大的情形下，沒有硏磨粒子的拋光溶 液也可以與非硏磨性的聚合墊一起使用。 上述過程也可以使用多於兩種拋光溶液來進行，舉例 而言，銅拋光使用兩種不同的拋光溶液，而阻障層拋光使 用一種拋光溶液。此過程也可以使用圖6a、6b所示的CMP 設備來實施。圖If是描述在相同的墊子上使用三種拋光溶 17 200308007 液之CMP過程具體態樣的流程圖70。在半導體晶圓的化學 機械拋光過程70中，個別的晶圓（如果採用平行的拋光系 統’則或者甚至是一群晶圓）必須先加以定位以便在墊子上 拋光（方塊700)，如上所述。接下來在過程70中，供應第 一種銅拋光溶液以供銅層12快速拋光（方塊710)。以第一 種銅拋光溶液（其快速拋光銅）進行的化學機械拋光一直繼續 到抵達銅層12的終點爲止（在方塊720檢查）。關掉第一種 銅拋光溶液，接著進行晶圓11和墊子的淸潔（方塊730)。 淸除墊子上的拋光溶液係使用去離子水的高壓淸洗及/或 吹送空氣法來達成。同時晶圓11本身可以藉由去離子水淸 洗然後旋轉晶圓11來淸潔。使用第一種銅拋光溶液之後， 將第二種銅拋光溶液傳送到墊子上，以移除留在區域14的 頂面17上之阻障層15上的剩餘銅殘餘物（方塊740)。另外 可以選擇的是將第一拋光步驟加以計時，以使用第一種銅 拋光溶液來移除大部份的銅，而僅留下500〜2000埃厚的層 ，其然後使用第二種銅拋光溶液來拋光移除。第二種銅拋 光溶液的拋光速率典型上乃低於第一種銅拋光溶液，並且 留下比較平滑的銅表面，而具有較少量的缺陷。 一旦關掉並淸掉第二種銅拋光溶液（方塊750)，則將用 於阻障層15拋光的第三種拋光溶液傳送到墊子上（方塊 760)，並且進行阻障層15的拋光。使用第三種拋光溶液的 阻障層15拋光一直繼續到抵達阻障層15的終點爲止（在方 塊770檢查）。一旦抵達阻障層15的終點（一旦抵達區域14 的頂面17)，則關掉第三種拋光溶液，並且淸潔墊子和晶圓 18 200308007 11(方塊780)。可以藉由類似或相同於用來淸除銅拋光溶液 的去離子水高壓淸洗及接著吹送空氣法，來達成移除墊子 上剩餘的拋光溶液。晶圓11也可以加以清洗和旋轉。移除 了阻障物後，晶圓11的化學機械拋光視爲完成了，並且晶 圓11乃準備好做下一個處理步驟。然後可以載入下一個晶 圓（或一群晶圓）(方塊790)。然後過程70根據方塊700到 790以新的晶圓（或群）來重複進行，如圖If所示。由所做敘 述可以看出，在此做法中使用相同的墊子和多種拋光溶液 來移除銅層12和阻障層15兩者。就如在之前的做法，基 於此目的可以使用固定硏磨劑的墊子、一般的墊子或聚合 墊。可以使用任一種墊子來拋光銅和阻障層兩者，但是在 每一情形中，所用之拋光溶液的組成可能是或不是相同的 〇 在過程70的範例中，拋光墊可以是固定硏磨劑型的墊 子，例如得自3M公司的MWR66墊子。第一種銅拋光溶液 可以是具有高移除速率之無硏磨劑的溶液，例如也得自3M 公司的CPS-11溶液。在墊子施加大約1 psi壓力至晶圓11 表面的情形下，CPS-11溶液的銅移除速率爲每分鐘大約 4000A。以CPS-11拋光之後，阻障層15上可能留有一些銅 殘餘物，或者表面上可以故意留有一定厚度的銅。此種殘 餘物可以使用第二種銅拋光溶液來拋光移除，而第二種銅 拋光溶液應該主要針對剩餘的殘餘物起作用，並且應該對 特徵16中的銅具有最小的蝕刻效應。如此可以使碟狀情形 降到最低。 19 200308007 第二種銅拋光溶液可以是具有低銅移除速率之無硏磨 劑的溶液，例如得自3M公司的CPS-12溶液。CPS-12溶液 的銅移除速率爲每分鐘大約1000A，並且從阻障層15的頂 端移除銅殘餘物。爲了在相同的墊子上拋光鉅，可以使用 得自EKC之修改過的拋光溶液，同時硏磨劑降低到2%或更 少，如上所討論的。如同之前的情形，EKC溶液的修改包 括了溶液的pH從4.0增加到5.5。舉例而言，增加pH可以 藉由添加氫氧化銨或羥胺而達成。再次地，如果所用的墊 子是一般的聚合墊，例如Thomas West 711，則仍然可以分 別使用相同的拋光溶液（CPS-11、CPS-12和具有2%硏磨劑 之修改過的EKC)於銅和钽。圖2圖解說明另一種開始基板 ，以示範本發明的方法。圖2示範具有保形銅層之開始基 板11’，該銅層可以使用例如ECD(electro-chemical deposition，電化學沉積）的傳統電沉積過程所製造。圖2圖 解說明通常包括矽晶圓之範例性基板11’的一部份。基板 11’的圖解說明部份包括圖案化的絕緣層14’或介電材料。 例如溝槽和導通孔的空穴16’或特徵乃藉由使用熟知的技術 ，將部份的絕緣層14’蝕去而形成於絕緣層14,中。例如Ta 或TaN或Ta / TaN堆疊層的阻障層15’乃形成於空穴16,中 以及絕緣層14’的頂面17’上。阻障層15’的厚度可以是在 100〜300A的等級或更小。雖然並未顯示，但是阻障層15’ 乃襯以一薄銅種子層，以起始銅在阻障層15’上的生長。 銅層12’乃使用傳統的保形沉積過程而形成於銅種子層 上。舉例來說，在典型的半導體元件中，導電層12,係藉由 20 200308007 沉積厚度大約爲特徵16’厚度之1·5〜2.00倍的銅而形成。根 據本發明的原理，如同在拋光具有平面狀銅層12之晶圓11 的情形，晶圓11’的銅層12’和阻障層15’可以使用上述和下 述具體態樣來拋光移除。拋光過程的各階段也是如上面圖 lc和Id所示範的進行。爲了淸楚起見，以下的具體態樣將 配合用於拋光平面狀銅層和底下Ta阻障層之情形的圖 la〜Id來描述。然而，相同的具體態樣可以應用於參考圖2 所敘述的銅層12’和底下的Ta阻障層15’。唯一的差別在於 後者之銅層12’的厚度，其中所述的過程可能比較薄之平面 層12的拋光要花更多時間。考慮圖lb和2中銅層厚度的 差異，將會體會到：圖3所示之使用兩種不同拋光溶液的 處理做法會更適合處理圖lb的銅層12和阻障層15，並且 使用三種拋光溶液化學品的處理做法會更適合移除圖2的 厚銅層12’和阻障層15’。另外可以選擇的是使用兩種拋光 溶液於較厚的銅12’，但是可以增加晶圓11上的壓力，以 增加第一溶液的移除速率，直到移除了一定厚度的銅（例如 三分之二）爲止。然後可以降低壓力，而仍然使用第一溶液 以移除剩餘的銅。然後使用第二溶液來拋光阻障層15’。 圖3是本發明使用分開的拋光溶液線路之至少一個具 體態樣的流程圖。過程2 0是使用兩條分開的抛光彳谷液線路 來實施圖le之過程10的一種方式。一晶圓（或一群晶圓）加 以定位以便拋光（方塊200)。然後打開第一拋光溶液線路（拋 光溶液線路#1)，以便供應拋光溶液至拋光墊（方塊210)，同 時參看圖6a、6b。拋光溶液線路#1所供應的拋光溶液（例如 21 200308007 CPS-08)會用於拋光銅層12到其終點。拋光溶液線路#1會 一直保持打開的’直到抵達銅的終點爲止（在方塊220檢查) 。一旦抵達銅的終點，則關掉拋光溶液線路#1(方塊23〇)。 爲了淸除墊子上來自線路#1的拋光溶液，握持晶圓11的頭 可以舉起於墊子上，並且以去離子（DI)水對晶圓η施以淸 洗’其然後從晶圓11表面反彈落於墊子上（方塊235)。同 時旋轉晶圓11 ’並且如果想要的話，藉由吹送例如空氣的 流體來移除多餘的溶液（方塊235)。 一旦淸潔了墊子和晶圓11，則打開拋光溶液線路#2(方 塊240)。拋光溶液線路#2所供應的拋光溶液會用於拋光晶 圓11上的阻障層15(例如鉬）。拋光溶液線路#2會一直保持 打開的，直到抵達阻障層15的終點爲止（在方塊250檢查） 。一旦抵達終點，則關掉拋光溶液線路#2(方塊255)。爲了 淸除墊子和晶圓11上來自線路#2的拋光溶液，握持晶圓 11的頭現在則舉起於墊子上，並且以DI水對晶圓11施以 淸洗（方塊260)。然後可以旋轉晶圓η來移除多餘的溶液 。淸洗的水從晶圓11反彈落於墊子上，藉此淸洗之。然後 對墊子吹氣以移除多餘的溶液。一旦淸潔了墊子和晶圓11 ，則載入下一個晶圓（或一群晶圓）(方塊270)，並且過程20 從方塊200開始對新載入的晶圓重複爲之。 圖4是本發明使用分開的拋光溶液線路之至少一個具 體態樣的流程圖。過程30是使用相同的墊子和兩條分開的 拋光溶液線路之另一種拋光過程。例如晶圓11的晶圓（或 一群晶圓）加以定位以便拋光（方塊300)。然後打開兩條拋光 22 200308007 溶液線路（拋光溶液線路#1和拋光溶液線路#2)，以便供應 拋光溶液至拋光墊（方塊310)，同時參看圖6a、6b。拋光溶 液線路#1和#2所供應的成分會用於拋光晶圓11上的銅層 12。拋光溶液線路#1供應氧化劑（例如過氧化氫）、錯合試 劑和抑制劑。拋光溶液線路#2供應錯合試劑和抑制劑，但 沒有氧化劑。 錯合試劑包括例如有機酸和胺的化學品，而抑制劑典 型爲苯並三唑（benzotriazQle，BTA)。錯合試劑作用在於增 加蝕刻/拋光速率，而抑制劑降低此速率。抑制劑沉積於 特徵16的區域中。抑制劑保護特徵16中的銅表面，所以 錯合試劑不會過度地拋光到這些區域裡。此確保拋光溶液 有低的靜態鈾刻速率，而幫助避免發生碟狀情形，即使沒 有墊子的機械作用也是如此。雖然兩條拋光溶液線路都是 開啓的，但是拋光溶液線路#2所供應的成分不會對銅的拋 光造成不利的衝擊，因爲每一線路的成分共享許多共通的 成分。因此兩條線路的拋光溶液之間發生交互作用的機會 有限。銅的移除（拋光）速率隨著拋光溶液中的氧化劑濃度而 增加，並且達到一高峰。然而，例如鉬之阻障層材料的移 除與氧化劑濃度較無關，而與機械硏磨較有關。 上述同一晶圓的銅和鉬拋光之間的淸洗步驟，乃確保 兩種拋光溶液之間的交互作用爲最小。然而，如果兩種拋 光溶液是相容的，則銅和鉬拋光之間就不需要淸洗或淸潔 ，也就是說，除了拋光溶液線路從銅拋光溶液切換到鉬拋 光溶液以外，同一晶圓從銅到鉬一直在拋光，當中沒有淸 23 200308007 洗步驟。在當使用單一拋光步驟來拋光銅和鉬兩者的另一 種選擇中，兩種拋光溶液可以簡化成單一拋光溶液線路。 拋光溶液線路#1和#2會一直保持打開的，直到抵達銅 的終點爲止（在方塊320檢查）。一旦抵達銅的終點，則關掉 拋光溶液線路#1(方塊330)。由於拋光溶液線路#1和#2中的 拋光溶液是有點相容的，DI水淸洗然後旋轉晶圓11或吹送 空氣於墊子上來移除前述溶液和DI水洗液則是可選擇的， 但是可能不需要。拋光溶液線路#2因此保持打開的。拋光 溶液線路#2所供應的拋光溶液會用於拋光晶圓11上的阻障 層（鉅）15。一旦抵達鉬的終點，則關掉拋光溶液線路#2(方 塊355)。爲了淸除晶圓11上來自線路#2的拋光溶液，以 DI水施以淸洗，然後旋轉以移除多餘的溶液（方塊360)。一 旦淸潔了晶圓11和墊子，則載入下一個晶圓（或一群晶圓）( 方塊370)，並且過程30從方塊300開始對新載入的晶圓重 複爲之。 圖5是本發明使用成分線路和氧化劑線路之至少一個 具體態樣的流程圖。過程40是使用相同的墊子和兩條分開 線路（其一包含拋光溶液而另一包含氧化劑）的另一種拋光過 程。晶圓（或一群晶圓）加以定位以便拋光（方塊400)。然後 打開兩條線路（拋光溶液線路和氧化劑線路），以便供應拋光 溶液和氧化劑至拋光墊（方塊410)。拋光溶液線路和氧化劑 線路所供應的成分會用於拋光晶圓11上的銅層12。拋光溶 液線路供應錯合試劑和抑制劑。氧化劑線路供應氧化劑， 例如過氧化氫。銅的移除（拋光）速率隨著氧化劑濃度增加而 24 200308007 增加i ’並且達到一高峰。然而，鉬的移除與氧化劑濃度較 無關’而與機械硏磨較有關。 抛光溶液線路和氧化劑線路會一直保持打開的，直到 抵達銅的終點爲止（在方塊420檢查）。一旦抵達銅的終點， 則關掉氧化劑線路（方塊430)。由於拋光溶液線路和氧化劑 線路中的溶液是有點相容的，DI水淸洗然後旋轉晶圓11和 口人达空热於墊子上可以不需要。拋光溶液線路仍保持打開 的°抛光溶液線路所供應的拋光溶液然後會用於拋光晶圓 11上的鉬層15到其終點（區域Η的頂端17)。一旦抵達鉅 的終點’則關掉拋光溶液線路（方塊455)。可以使用一些超 過終點的過度拋光，以淸除可能的殘餘物。爲了淸潔晶圓 11 ’以DI水對晶圓η施以淸洗，同時旋轉晶圓u(方塊 460)。此亦衝擊於墊子上並淸潔之。一旦淸潔了墊子和晶 圓Η ’則載入下一個晶圓（或一群晶圓）(方塊470)，並且過 程40從方塊400開始對新載入的晶圓重複爲之。 圖6a、6b圖解說明根據本發明的一或多個具體態樣所 建構之拋光站的側視圖和平面視圖。晶圓拋光站50包括多 個拋光構件和晶圓外罩540或晶圓載運頭。晶圓外罩540 穩固地定位晶圓550，所以晶圓550的正面560完全暴露出 來。晶圓拋光站50包括拋光正面560的拋光墊510、以雙 向線性或往復（前後）運動來驅動拋光墊510的機構（未顯示) 、以及隨著墊子510拋光暴露的晶圓表面560時供應流體 支承至墊子510背面的支承板520。雙向的線性運動也稱爲 相反的線性運動。拋光墊510的底面可以額外附著於彈性 25 200308007 但穩固的材料（未顯示），以支持墊子510。拋光墊510乃用 於拋光表面560的銅和阻障層(例如钽）兩者。使用單一墊子 於暴露之晶圓表面560的兩層，則不再須要分別使用多個 墊子，並且也可能不再須要分別使用多個拋光站。拋光墊 510可以是無硏磨劑者，例如聚合墊，或者是固定硏磨劑的 墊子。由於鉅和銅層具有不同的特性，如果要用相同的墊 子來拋光兩者，則必須使用不同的拋光溶液。要注意到： 所述的雙向線性拋光器最好用爲拋光站50，例如美國專利 第6，103,628號和美國專利申請案第09/684,059號所述，此 二者皆明確地倂於此以爲參考。當如此使用時，拋光墊510 最好是帶子，其有一部份在處理區域裡做雙向移動，其上 可以包含或不包含固定的硏磨劑，並且在拋光區域中最好 是漂浮於平台支承520上。此外，帶子可以是漸進地移動 ，如此在不同的時間使用相同帶子的不同部份（不同的部份 可以重疊或不重疊於處理區域中先前所用的部份），而不同 的時間可以是或不是由所使用的處理溶液來區分的。 雖然目前偏好上述類型的拋光站，但是本發明並不限 於使用此種拋光站。反而是說，在此所述之過程可以與其 他CMP拋光站一起使用，包括那些使用線性旋轉帶、靜止 拋光墊與移動的晶圓、抵住靜止或旋轉之晶圓而移動的旋 轉拋光墊、或他者。此外，可以使用薄而少剛性的墊子和 較厚而更有剛性的墊子，此視所要的效果而定。墊子後面 可以有或沒有支承板。 拋光期間所用的拋光溶液和淸洗溶液，最好是以兩條 26 200308007 或更多條拋光溶液線路（例如線路#1和線路#2)而供應至使 用雙向線性拋光器的拋光站50。在本發明的至少一個具體 態樣中，拋光溶液線路#1包括左側供應線路512和右側供 應線路511。類似地，拋光溶液線路#2包括左側供應線路 514和右側供應線路513。供應線路511和513供應拋光站 50的右側，而供應線路512和514供應拋光站50的左側。 雖然未顯示於圖6a、6b、7a、7b中，但是將會體會到：拋 光站50可以具有多於兩條的拋光溶液線路（例如線路#3，未 顯示），其如同其他線路#1和#2做類似的建構並配備有個別 的供應線路。具有線路#3的這種組態可以用於根據圖If所 述的具體態樣。另外可以選擇的是噴嘴的數目保持相同， 但是可以使用閥以經過相同的噴嘴而帶來不同的拋光溶液 。多種達成此的方式對於熟於此技藝者而言乃顯而易見的 〇 現在要根據本發明的多種具體態樣來描述晶圓550的 拋光。在一具體態樣中，晶圓550載入外罩540中並且定 位於拋光站50上方之後，打開拋光溶液線路#1以供應拋光 溶液至墊子510的左側和右側。打開拋光溶液線路#1時， 右側供應線路511和左側供應線路512會主動供應拋光溶 液至墊子510。右側供應線路513和左側供應線路514將會 是關閉的。墊子510由機構530所驅動，並且此運動結合 了拋光溶液線路#1之拋光溶液在晶圓550表面560上的化 學反應性，用以拋光表面560上的銅。應該注意到：對於 圖6a、6b的系統而言，拋光溶液的傳遞也可以與墊子510 27 200308007 的運動相結合。舉例而言，當墊子510移到左側時，拋光 溶液從噴嘴511傳出，而當墊子510移到右側時，拋光溶 液從噴嘴512傳出。以此方式，拋光溶液總是被移動的墊 子510所移向晶圓550。拋光溶液的浪費便降到最低。一旦 抵達銅的終點，則關掉拋光溶液線路#1。此須要切斷供應 線路511和512或使之不作用。 爲了移除晶圓550之正面560和墊子510上的剩餘拋 光溶液，當晶圓550舉起於墊子510上方時，去離子水噴 嘴把水射向晶圓表面560。水從晶圓550反彈落於墊子510 表面上，並且淸潔了晶圓550和墊子510表面兩者。在此 淸潔步驟期間，晶圓550最好可以旋轉。噴水之後，吹風 機580把空氣吹到墊子510上，以移除多餘的溶液。其次 ，打開拋光溶液線路#2,因此右側供應線路513和左側供 應線路514會分別主動供應拋光溶液至墊子510的右側和 左側。拋光溶液線路#2供應的拋光溶液乃設計用於阻障層（ 例如鉅）的拋光。對於表面560的墊子510運動以及拋光溶 液線路#2的拋光溶液，用以拋光晶圓550之表面560上的 鉬。一旦抵達鉬的終點，則關掉拋光溶液線路#2(使供應線 路513和514不作用），淸潔墊子510(使用淸洗器570)，以 及移除多餘的溶液（使用吹風機580)，然後載入下一晶圓至 外罩540中供拋光。淸洗器570和吹風機580可以多種方 式實施，包括使用高壓噴嘴。 上面已經討論了適合此種拋光之拋光溶液和墊子的範 例性類型。在本發明的某些具體態樣中，拋光溶液線路#1 28 200308007 供應錯合試劑、抑制劑和氧化劑。拋光溶液線路#2供應錯 合試劑和抑制劑，但沒有氧化劑或者供應極低濃度的氧化 劑。在此種具體態樣中，在銅的拋光期間，拋光溶液線路 #1和#2可能都會打開（因此所有四條供應線路511、512、 513和514都會打開）。銅拋光之後，可能關掉拋光溶液線 路#1，祇留下拋光溶液線路#2的供應線路513和514有作 用（是打開的）。而在其他具體態樣中，拋光溶液線路#2會 傳遞錯合試劑和抑制劑，而拋光溶液線路#1祇傳遞氧化劑 。再次地，在銅的拋光期間，線路#1和#2可能都會打開， 然後可能關掉拋光溶液線路#1以供鉅拋光。 圖7a、7b圖解說明如上述具體態樣中使用墊子來拋光 晶圓的詳細視圖。回去參見圖lb，所要拋光的晶圓11具有 多層，包括銅層12和阻障層15。在拋光之前，暴露的正面 645會先暴露出銅層12做拋光。銅層12拋光之後，所得的 晶圓11會暴露出底下的阻障層15(見圖lc)。定位晶圓11， 如此使其正面645緊靠著拋光墊640的表面。 參考圖7a，其顯示在拋光模式的拋光站。拋光溶液由 兩條拋光溶液線路（線路#1和線路#2)供應於拋光墊640的 兩側。在本發明的至少一個具體態樣中，拋光溶液線路#1 包括左側供應線路612和右側供應線路611。類似地，拋光 溶液線路#2包括左側供應線路614和右側供應線路613。 供應線路611和613供應拋光墊640的右側，而供應線路 612和614供應拋光墊640的的左側。 在一具體態樣中，來自線路#1的拋光溶液包含了氧化 29 200308007 和化學機械地移除表面645之銅層12的化學品，乃供應於 晶圓11和拋光墊640之間。銅層12拋光以後，則關掉拋 光溶液線路#1。晶圓11升起於墊子640上方，如圖7b所 示。當晶圓11是在如圖7b所示的位置時，來自淸洗器670 的去離子水淸洗劑（包含〇〜〇.〇1 %的腐蝕抑制劑）淸除了晶圓 11上的拋光溶液，然後其從晶圓11(的正面645上）反彈落 於墊子640上，而淸除了墊子640上的拋光溶液。淸洗墊 子640的水可能保持在墊子640上，此可能不利地稀釋了 下一拋光溶液。吹風機680把空氣吹送到墊子640上，以 使下一拋光溶液的稀釋達到最小。 淸洗之後，晶圓11回到圖7a所示的位置。然後打開 拋光溶液線路#2,供應拋光溶液以拋光阻障層15,阻障層 15在銅層12拋光移除後就暴露出來。墊子640的作用與來 自拋光溶液線路#2的拋光溶液一起拋光晶圓11上的層15 。然後晶圓Π可以回到圖7b的位置，以對晶圓11和墊子 640做最後淸洗。在本發明的其他具體態樣中，拋光溶液線 路#1和拋光溶液線路#2 —開始可以都打開。在此情形下， 拋光溶液線路#1會包含與拋光溶液線路#2所傳送之相同的 成分，但是也會傳送額外的氧化劑成分。拋光溶液線路#1 和拋光溶液線路#2都會拋光銅層12。銅層12拋光以後， 關掉拋光溶液線路#1，留下拋光溶液線路#2是打開的。拋 光溶液線路#2沒有傳送或傳送極低濃度的氧化劑，則會拋 光阻障層15。在本發明另外的具體態樣中，拋光溶液線路 #2會傳送拋光成分（例如錯合試劑和抑制劑），而拋光溶液 200308007 線路#1僅傳送氧化劑。再次地，在此情形下，在銅層12的 拋光期間，拋光溶液線路#1和#2會打開，然後在之後的阻 障層15拋光期間，氧化劑線路（拋光溶液線路#1)會關掉。 當以此方式打開兩條線路時，來自拋光溶液線路#1的氧化 劑和來自線路#2的成分在墊子640上會需要良好的混合， 以便確保整個溶液在墊子640上有均勻的分布。 在本發明的一或多個具體態樣中，拋光墊乃描述由一 種所組成，不是固定硏磨劑型就是聚合型。在本發明另外 可以選擇的具體態樣中，也有可能將單一墊子分隔或區分 成一或多個固定硏磨劑的區段以及一或多個聚合區段。當 需要墊子的每一區段以使晶圓上之特定層的化學機械拋光 有最好的處理功效時，墊子可以前進或後退，以將墊子的 適當區段置於拋光晶圓的位置。因此，固定硏磨劑的區段 可能用於拋光銅層的時候，而較軟的聚合區段可能用於拋 光阻障層的時候。圖6a之較佳系統的往復運動和特定設計 乃允許此種彈性。 如之前所述，在此所敘述的拋光技術可以在單一 CMP 站中使用單一拋光墊來進行，或者在多個CMP站中使用多 個拋光墊來進行。如上所述，在一具體態樣中，銅層和阻 障層的移除可以在相同的CMP站中進行。在此具體態樣中 ，銅層的移除可以在阻障層的移除之前進行。根據此過程 順序，在第一步驟裡，整個銅可以使用固定硏磨劑的拋光 墊而往下移除到達阻障層。在此銅移除的步驟中，拋光溶 液可以包含或不包含粒子。在第二步驟裡，固定硏磨劑的 31 200308007 拋光墊可以與具有固體粒子的拋光溶液結合使用，以移除 阻障層表面的剩餘銅層，同時對工件施以向下的力。此向 下的力可以是比較低之向下的力。這些步驟之後，便要移 除阻障層。阻障層的移除可以利用拋光墊上由軟聚合物做 成的部份。也就是說，拋光墊可以具有固定硏磨劑的一部 份以及由軟聚合物做成的第二部份。選擇性拋光鉬的溶液 可以傳送到拋光墊以移除阻障層，同時對工件施以低向下 的力。 在另一具體態樣中，銅和阻障層的移除可以使用整合 的CMP系統（整合的CMP工具）而在個別的拋光墊上進行。 在本發明的具體態樣中，不同的墊子係位於同一工具中的 個別CMP站裡。適合用於整合之CMP系統的範例性CMP 站乃參考圖6a而描述如上，並且也可參考2003年1月17 日申請的美國專利申請案第10/346,425號（NT-278-US)，其 標題爲「靈敏偵測終點之先進的化學機械拋光系統」 (Advanced Chemical Mechanical Polishing System with Smart Endpoint Detection)，其倂於此以爲參考。把多個CMP站倂 入一個整合的工具裡，有可能改善銅和阻障層的不同拋光 〇 圖8顯示根據本發明的具體態樣而具有多個CMP站之 整合CMP系統800的方塊圖。在所示的具體態樣中，整合 的CMP系統800具有第一 CMP站810和第二CMP站820。 在第一 CMP站810中，在第一拋光程序裡，銅層使用第一 拋光墊（未顯示）和第一拋光溶液來移除。就本發明某一方面 32 200308007 而言，第一拋光墊是固定硏磨劑的拋光墊，並且第一拋光 溶液包含硏磨及/或潤滑粒子。在此方面，硏磨粒子與固 定硏磨劑的拋光墊結合時，該粒子可以做爲拋光的潤滑劑 。硏磨粒子是漿液中的固體粒子。在第一拋光程序期間， 晶圓乃降低到第一拋光墊上，並且第一拋光溶液乃傳送到 第一拋光墊上。第一拋光墊在支承板上方移動（見圖6a)， 同時在第一拋光墊底下施以流體壓力。一旦銅層往下移除 到達晶圓表面上的阻障層（見圖lc)，則在第二CMP站820 進行阻障層的移除過程（第二拋光程序）。第二CMP站820 具有第二拋光墊（未顯示）以及使用第二拋光溶液。第二拋光 墊可以是聚合的/非固定硏磨劑的拋光墊。舉例來說，第 二拋光墊可以由例如聚氨酯的軟聚合材料所做成。就本發 明某一方面而言，在阻障層移除的過程中，使用選擇性拋 光溶液做爲第二拋光溶液。在此方面，選擇性拋光溶液乃 傳送到適合移除阻障材料的聚合拋光墊上，並且移動墊子 來拋光。流體壓力可以施加於第二拋光墊底下。使用這些 技術可以使晶圓上的應力以及所造成的脫層降到最低。這 些技術也可以使碟狀情形和刮痕降到最低。在整合的CMP 系統中使用兩個CMP站祇是舉例而已。也可構想出具有額 外CMP站的整合CMP系統。 圖9是拋光半導體晶圓之銅和阻障層的方法之具體態 樣的流程圖，其乃使用具有多個CMP站之整合CMP系統 ，例如參考圖8所描述的CMP系統。在步驟910，在拋光 墊的第一部份上使用拋光溶液來拋光半導體晶圓的第一層 33 200308007 。在一具體態樣中，第一層包括銅。在步驟920，在拋光墊 的第二部份上使用拋光溶液來拋光半導體晶圓的第二層。 在一具體態樣中，第二層包括鉬。將會理解到：可以拋光 多於兩層，並且可以使用多於兩部份的拋光墊。用於拋光 不同層的拋光溶液可以是相同的拋光溶液或是不同的拋光 溶液。拋光墊的不同部份可以位於相同的拋光墊上或是位 於不同的拋光墊上。個別的拋光溶液和拋光墊最好設計及 /或適合於拋光晶圓的特定層。舉例而言，溶液和墊子可 以適於拋光銅或適於拋光阻障層（例如鉬）。 根據本發明，一次通常祇拋光一片晶圓。雖然本發明 適合一次拋光單一晶圓，但是熟於此技藝者可以修改本發 明的較佳具體態樣，以便一次拋光多片晶圓。要了解到： 在則述討論和所附申請專利範圍中，「晶圓表面」（wafer surface)和「晶圓的表面」（surface of the wafer)等詞包括但 不限於處理之前的晶圓表面以及任何形成於晶圓上之層的 表面，包括氧化的金屬、氧化物、旋塗玻璃、陶瓷…等等 。此外，雖然上面主要在討論兩層的拋光，即一金屬層（例 如銅）和阻障層（例如Ta)，但可以使用在此所述技術來拋光 任何數量和種類的層，例如以固定硏磨劑的墊子而供應多 種適合各層的拋光溶液。將會了解到：從半導體晶圓表面 移除一層與拋光半導體晶圓表面上的一層同義。在此所述 的多種方法中，「方塊」（block)和「步驟」（step)都是指處 理步驟。 雖然爲了舉例說明而揭示了本發明的多種較佳具體態 34 200308007 樣，但是熟於此技藝者將體會到：在不偏離本發明如揭示 於申請專利範圍的範疇和精神下，各種的修改、添加及/ 或取代是有可能的。 【圖式簡單說明】 (一）圖式部分 圖la圖解說明半導體晶圓在沉積銅層於其上之前的剖 面圖； 圖lb圖解說明圖la所示之半導體晶圓的剖面圖，其 中平面狀導電層已經沉積在晶圓的頂端上； 圖lc圖解說明圖lb所示之半導體晶圓的剖面圖，其 係在根據本發明的一或多個具體態樣來拋光銅層之後的情 形； 圖Id圖解說明圖lc所示之半導體晶圓諸層的剖面圖 ，其係在根據本發明的一或多個具體態樣來拋光阻障層之 後的情形； 圖le是本發明在相同墊子上使用兩種不同拋光溶液之 一或多個具體態樣的流程圖； 圖If是本發明在相同墊子上使用三種不同拋光溶液之 一或多個具體態樣的流程圖； 圖2圖解說明圖la所示之半導體晶圓的剖面圖，其中 厚導電層已經沉積在晶圓的頂端上； 圖3是本發明使用分開的拋光溶液線路之至少一個具 體態樣的流程圖； 圖4是本發明使用分開的拋光溶液線路之至少一個具 35 200308007 體態樣的流程圖； 圖5是本發明使用成分線路和氧化劑線路之至少一個 具體態樣的流程圖； 圖6a、6b圖解說明根據本發明的一或多個具體態樣所 建構之拋光站的側視圖和平面視圖； 圖7a、7b圖解說明根據本發明的一或多個具體態樣而 使用單一墊子來拋光晶圓的詳細視圖；200308007 发明 Description of the invention [Related applications] This case is US Patent Application No. 10 / 346,425 (NT-278-US) filed on January 17, 2003 and US Patent Application No. 10 filed on July 19, 2002 / 199,471 (NT-258-US) of some continuation cases, all of which are here for reference. This case is based on US Patent Provisional Application No. 60 / 417,544 (NT-278-P2) filed on October 10, 2002 and US Patent Provisional Application No. 60 / 365,001 (NT- 237-P), all of which are hereby incorporated by reference. [Technical Field to which the Invention belongs] The present invention relates to the field of chemical mechanical polishing. In particular, the present invention relates to a method and apparatus for integrated polishing of both copper and barrier layers. [Previous Technology] Traditional semiconductor devices generally include a semiconductor substrate (usually a silicon substrate), and multiple conductive layers (such as silicon dioxide) formed in sequence and conductive paths or interconnected conductive materials. Due to the excellent electron mobility and low resistance characteristics of copper and copper alloys, they have recently received considerable attention as conductors of an interconnect junction. Interconnections are typically formed by metallizing copper into features or holes etched into a dielectric interposer. The preferred method of copper metallization is electroplating. In the integrated circuit, the multi-layered interconnection network extends laterally with respect to the substrate surface. Interconnections formed in the sequence interposer can be electrically connected using vias or contacts. In a typical process, an insulating 200308007 interposer is first formed on a semiconductor substrate. A patterning and etching process is performed to form features such as trenches, vias, or dual damascene structures in the insulating layer. Copper is then electroplated to fill all the features. However, the plating process results in a copper layer in the features and a copper layer on the substrate surface. Then remove excess copper from the surface before subsequent processing steps. Traditionally, after patterning and etching, the insulating layer is first covered with a barrier layer, which is typically a giant or tantalum / molybdenum nitride composite layer. The barrier layer covers the top surfaces of the vias and trenches and the insulating layer to ensure good adhesion, and acts as a barrier material to prevent copper from diffusing into the semiconductor element and passing through the insulating layer. Secondly, a seed (conductive) layer is deposited on the barrier layer, which is usually a copper layer. The seed layer forms a substrate of conductive material for copper film growth during subsequent copper deposition. As the copper film is plated, the copper layer quickly fills the vias, but covers the wide trenches and surfaces in a conformal manner. When this deposition process is continued to ensure that the trenches are also full, a thick copper layer or unnecessary burden is formed on the substrate. Traditionally, after copper plating, a CMP (chemical mechanical polishing) process is used to comprehensively planarize and reduce the thickness of the copper layer to the height of the surface of the barrier layer. In order to electrically isolate the copper-filled features, the barrier layer is removed by another CMP step. In the semiconductor industry, chemical mechanical polishing (CMP) of semiconductor wafers for VLSI (Very Large Scale Integration) and ULSI (Ultra Large Scale Integration) applications has important and widespread uses. . CMP is the process of planarizing and polishing semiconductor wafers, which combines the chemical removal of layers such as insulators and metals with mechanical impact on the wafer surface. CMP is also used for wafer planarization / polishing after crystal growth and during wafer processing 200308007, and is a process that provides overall planarization of the wafer surface. For example, during integrated circuit manufacturing, CMP is often used to planarize / polish the contours that accumulate in multi-layer metal interconnect systems. The desired flatness of the wafer surface must be achieved without contaminating the desired surface. At the same time, the CMP process must avoid polishing to remove the active circuit parts. Now, the conventional system of chemical mechanical polishing of semiconductor wafers will be described. A traditional CMP process requires a wafer to be positioned on a grip, which rotates around a first axis and descends onto a polishing pad that rotates in a reverse direction about a second axis. During the planarization process, the wafer holder presses the wafer against the polishing pad. During wafer polishing, a polishing solution such as a polishing agent or slurry is typically applied to the polishing pad. The contents of the polishing solution depend on the characteristics of the material to be removed during CMP. For example, if the material is metallic, the polishing solution may be composed of any one or more of a honing agent, an oxidizing agent, a complexing agent (etching chemical), an inhibitor, and / or a surfactant. The oxidizing agent in the polishing solution oxidizes the surface of the metal material, while the oxidized metal material is chemically and mechanically removed due to honing caused by friction with the mat or honing powder or both. Etching chemicals can be used to increase the polishing rate of metallic materials. In another conventional CMP process, a wafer holder positions a wafer and presses the wafer against a belt-shaped polishing pad while the pad is continuously moved in the same linear direction relative to the wafer. During this polishing process, a so-called belt-shaped polishing pad can be moved on a continuous path. These traditional polishing processes may further include a conditioning station positioned in the path of polishing, 200308007 to condition the mat during polishing. The factors that need to be controlled to achieve the desired flatness and flatness may include polishing time, pressure between the wafer and the pad, the speed of rotation, the particle size of the slurry, the feed rate of the polishing solution, the chemical properties of the polishing solution, and the material. Although the above-mentioned CMP process is widely used and accepted by the semiconductor industry, there are still challenges. Due to the nature of the materials used to accept polished copper, barriers, and other layers, traditional systems often include different polishing solutions and different types of polishing pads for different layers. This often means that the copper layer must be polished with a certain pad, and the barrier layer must be removed with a completely different pad. At the same time, differences in the composition of the mat material and the polishing solution may cause unintended side effects such as erosion or dishing in other layers than currently polished. This adds time, cost, defect rate, and complexity during the polishing process. In particular, polishing techniques have attempted to solve the problem of polishing copper layers on molybdenum barrier layers. It should be noted that all references referring to Ta barriers are also applicable to TaN barriers and Ta / TaN stacks. Prior art CMP tools were complex and expensive machines. Integrated polishing methods and equipment are needed to efficiently polish molybdenum and copper simultaneously, reducing cost and complexity, and reducing the time required to polish semiconductor wafers. SUMMARY OF THE INVENTION The present invention overcomes the limitations of the traditional chemical mechanical polishing listed, and provides a technique for polishing multilayer workpieces. In one or more embodiments of the invention, the same pad is used to polish multiple layers of a semiconductor wafer. This is achieved by supplying different polishing solutions when polishing one layer of 200308007 of different composition. In a specific aspect, the copper layer is polished first using the first polishing solution delivered to the pad. After that, the second polishing solution transferred to the same pad is used to polish the barrier layer of the same wafer. After each layer is polished, a rinse agent can be used to clean the mat and / or wafer, followed by or without a blow or spin process to remove excess solution. In alternative embodiments, copper and barrier layers can be removed in an integrated CMP system using multiple polishing pads or multiple portions of a single polishing pad. In addition, multiple polishing solutions can be combined with multiple polishing pads to optimize polishing efficiency. In other specific aspects of the invention, different layers of the semiconductor wafer are polished using different polishing solutions in different CMP stations. In a specific aspect, the copper layer is first polished using the first polishing solution transferred to the mat of the first CMP station. Thereafter, a second polishing solution is used in a second CMP station to polish the barrier layer of the same wafer. [Embodiment] The present invention relates to a method and apparatus for chemical mechanical polishing of multiple layers of a workpiece such as a semiconductor wafer. The various techniques described herein may involve a single polishing pad or multiple polishing pads. In addition, these technologies may involve a single polishing solution or multiple polishing solutions. Furthermore, a single part of the polishing pad or multiple parts of a single polishing pad (each part having a different composition) can be used. "Polishing pad" — The term can be interchanged with the terms "polishing member" and "polishing belt". The terms "wafer", "semiconductor wafer", "workpiece" and "substrate" are interchangeable 200308007. In a specific aspect, a first polishing solution is supplied to polish a first layer such as a copper layer. Once the end of the copper layer is reached, the supply of the first polishing solution is stopped and the wafers and pads are rinsed. In the context of this application, when a given layer is removed from the top of the bottom layer and the bottom layer is exposed, it can be described as having reached the end point. A second polishing solution is then supplied to polish a second layer, such as a barrier layer, on the same mat. In another embodiment, the first polishing solution is supplied on the pad, and the copper layer is partially polished at high speed. A second polishing solution is then supplied to remove the remaining copper layer. Next, a third polishing solution is used to remove the barrier layer. Regarding the polishing solution used, the polishing solution may be a variety of polishing agents without honing particles, or a slurry with honing particles, depending on the type of mat used for polishing and the type of polishing desired. For example, the polishing pad may contain a honing agent embedded in the front of the pad, and a polishing agent containing no honing particles is introduced; or a polishing pad without such embedded honing agent may be used, and a slurry is used instead ; Or some other combination of tape, slurry, and / or polish can be used. The polishing solution may include a chemical that oxidizes the material, and the material is then mechanically removed from the wafer, which will be further described later. It may also include colloidal silica or fumed silica. Grind particles. A polishing agent or slurry typically grows a thin layer of silicon dioxide or silicon oxide on the front side of the wafer, and the impact of the pad mechanically removes the oxide. As a result, the high profile on the wafer surface is removed until an extremely flat surface is reached. Referring back to the first specific aspect, after reaching the polishing end of the copper layer 200308007, the supply of the first polishing solution was interrupted, so that the polishing of the barrier layer was started with the second polishing solution. These and other specific aspects all use the same pads to polish both copper and barrier layers. The equipment for performing these and other specific aspects is to couple and control the necessary polishing solution lines one after the other. In one aspect of the invention, the polishing solution circuit is embodied in a polishing solution distribution system. In discussing the present invention, various references will be directed to specific copper layers, barrier layers, polishing solutions, pads, and other ingredients. Such references are merely examples, as it should be readily understood that any form, manner, and type of layer, polishing solution, pad, and other ingredients may be appropriately replaced depending on the intended use, polishing system, and / or wafer. For example, in the description, both the deposited copper layer and the underlying seed layer are often referred to as the copper layer, and the barrier layer is referred to as the molybdenum layer. This description depends on the wafer composition used and the layers being processed at the time, and should not be considered as limiting the invention in any way. At the same time, when describing the present invention, references to "same pads" may also include different parts of a pad, and in all examples, "same type of pad" refers to the pad Each different part (if any) has a similarly composed cushion. When describing different patterns, 'similar reference numbers are used to indicate similar components and similar structures. Figure la illustrates a portion of an exemplary substrate n, which typically includes a silicon wafer. The illustrated portion of the substrate 11 includes a patterned insulating layer 14 or region, which includes a dielectric material. For example, holes 16 or features 12 of trenches and vias are formed in the insulating layer 14 by using a well-known technique to etch away a part of the insulating layer 14. Feature 16 may expose a portion of the substrate surface. A barrier layer 15 such as Ta or TaN or a Ta / TaN stacked layer is formed in the cavity 16 and on the top surface 17 of the insulating layer 14 or the surface of the region. The thickness of the barrier layer 15 may be on the order of 200 to 300A. Although not shown in Figures la to Id, the barrier layer 15 is lined with a thin copper seed layer to start the growth of copper on the barrier layer 15. For example, the planar conductive layer 12 of the copper layer is formed on the copper seed layer using an ECMD (electrochemical mechanical deposition) method. For example, the thickness of the copper layer 12 is about 1,000 people. Figure lb illustrates a starting substrate with a planar copper layer manufactured using the ECMD method. An example of the ECMD method is disclosed in U.S. Patent No. 6,176,992, issued on January 23, 2001, and entitled "Method and Apparatus for Electro-Chemical Mechanical Deposition". The assignee of this case has it. The use of a substrate with a planar copper layer as the starting substrate is for illustrative purposes only. The method of the present invention (shown in FIG. 2) can also use a starting substrate with a thick conformal copper layer, which is a conventional electrode such as ECD (electrochemical deposition). The seven produced are also within the scope of the present invention. Figures lc and Id illustrate later stages of the polishing process for such a starting sample as shown in Figures lb and 2. The polishing process of the present invention uses a single polishing tape or pad (honed or non-honed) throughout the entire polishing process. ° According to the present invention, the barrier layer 15 and the copper layer 12 use the same polishing 13 200308007 pad Or polished by a belt (not shown). The pad first polishes and removes the copper layer 12 on the wafer 11 until it reaches its "end point", and then removes the barrier layer 15 until its "end point". For the purpose of describing various specific aspects of the present invention, the end point of the copper layer 12 may be defined as the first case along the barrier layer 15 when it reaches the barrier layer 15 during polishing. Similarly, the end point of the barrier layer 15 may be defined as the first case when the top end 17 of the area 14 is reached during polishing. It should be noted that after the end of copper and barrier removal, a predetermined amount of over-polishing may be performed in either or both cases to eliminate any possible residue on the surface of the wafer 11. The copper layer 12 is polished with a mat (not shown) by transferring a first polishing solution (described below) to the mat. The chemical reaction in the first polishing solution combined with the mechanical honing of the pads on the copper layer 12 removed the copper layer 12. Removal of the copper layer 12 occurs to its end point, which is defined as the beginning of its lower barrier layer 15. The obtained wafer 11 is shown in Fig. 1c. Although the copper layer 12 has been removed to the height of the barrier layer 15, the barrier layer 15 and the features 16 remain. After the copper is polished, the surface of the wafer 11 and the surface of the mat are simply cleaned using a cleaning fluid such as water. When cleaning, the surface of the wafer 11 and the surface of the mat may or may not be separated, but if they are separated, the surface of the wafer 11 and the surface of the mat may be separately cleaned, and this cleaning can be performed after reference In progress. After cleaning, although the surface of the wafer 11 can be rotated or not rotated to remove excess solution, it is best to blow off the excess solution on the mat so that its surface is ready to accept different chemicals. At this time, the second polishing solution can be disposed on the same pad. The second polishing solution is then used to polish the barrier layer 15 until the top surface Π of the area 14 is 14 200308007. This polishing action produces a planarized wafer 11 surface, as shown in Figure Id. Each feature 16 is now electrically isolated from each other, and the top surface 17 is flat and planar 'for further processing. FIG. Le is a flowchart of one or more specific aspects of the present invention. In the process of chemical mechanical polishing of semiconductor wafers 10, individual wafers (or even a group of wafers if a parallel polishing system is used) must first be positioned for polishing on a pad (block 100). Positioning can be achieved by a carrier head or housing, which positions the wafer very close to the polishing pad (see Figure 6a). Next in process 10, a first polishing solution is supplied for polishing the copper layer 12 (block 110). During this process, the first chemical polishing solution is disposed between the copper layer 12 and the polishing pad, thereby chemically and mechanically polishing the copper, while the wafer 11 is pressed against the pad. As the wafer 11 is pressed against the polishing pad, the movement of the polishing pad relative to the wafer 11 provides a mechanical effect on the copper surface 12. This mechanical action, combined with the chemical reaction of the polishing solution, polishes the copper surface. The rotation of the carrier head facilitates the transfer of the polishing solution and also helps to obtain a uniform polishing rate across the copper layer 12. Chemical mechanical polishing with the first polishing solution, which is particularly suitable for copper polishing, continues until the end of the copper layer 12 is reached (checked at block 120). Once the end of the copper layer 12 has been reached (once the barrier layer 15 has been exposed) and optional over-polishing has been performed, the first polishing solution is eliminated (block 130). The first polishing solution on the pad can be achieved by high-pressure scrubbing with de-ionized (DI) water and / or by blowing air (see below). At the same time, the wafer 11 itself can be cleaned by deionized water, and then the wafer 11 is rotated to remove the deionized water, and can be cleaned separately; the wafer 11 is typically still wet, but there is no 15 200308007 above Deionized water. Once the first polishing solution is eliminated, a second polishing solution (which is more suitable for polishing the barrier layer 15 than the first polishing solution) is supplied for polishing the barrier layer 15 (block 140). The second polishing solution is disposed on a polishing pad 'and polishing the barrier layer 15 is performed. The polishing of the barrier layer 15 using the second polishing solution continues until the end of the barrier layer 15 is reached (checked at block 150). Once the end of the barrier layer 15 is reached (once the top surface 17 of the area 14 is reached), the second polishing solution is turned off (block 160). The removal of the polishing solution from the pad can be achieved by a high pressure scrubbing and / or air blowing method similar to or the same as that used to wipe out the first polishing solution. The wafer 11 is then rinsed and rotated to remove excess solution. The chemical mechanical polishing of wafer 11 is considered complete, and wafer 11 is ready for the next processing step. The next wafer (or group of wafers) can then be loaded (block 170). Process 10 is then repeated with new wafers (or clusters) according to blocks 100 through 160. In a specific aspect, the novel feature of the present invention is that the same pad is used for both the copper layer 12 and the barrier layer 15. In addition, a cleaning step is performed between to avoid the incompatibility between the first polishing solution and the second polishing solution. The types of mats that can be used for such polishing vary widely. Such mats include a mat for fixing an abrasive and a non-abrasive mat, depending on the desired polishing effect and the chemical solution used. Either of the two types of pads can be used to polish both copper and barrier layers, but the composition of the polishing solution used may or may not be the same in each case. In the example of process 10, the copper layer 12 may be a planar copper film. Note 16 200308007 In this context, a "planarized thin" copper film may refer to a film having a thickness of less than 3000 angstroms and being planar. The polishing pad may be a fixed honing type pad, such as the MWR66 pad available from 3M Company. For such a mat with a fixed abrasive, the polishing solution for polishing copper can be a solution without an abrasive, for example, a CPS-08 solution also available from 3M Company, although a solution containing an abrasive can also be used. To polish molybdenum on the same mat, a modified polishing solution (9030 polishing solution) from EKC can be used, while the honing agent (from typical 5%) is reduced to 2% or less, although it is also possible to use Or other polishing solutions without honing agents. The modification of the EKC 5 solution included a pH of the solution from 4. 0 to 5. 5. For example, increasing the pH can be achieved by adding ammonium hydroxide or hydroxylamine. If the mat used is a general polymeric mat, such as Thomas West 711, the same polishing solution (CPS-08 solution and modified EKC with 2% honing agent) can still be used for copper and macro, respectively. One advantage of using a small amount of honing agent (2% instead of 5%) is that the by-products left on the mat can be easily removed. Judging from the slurry remaining on the mat, very high levels of honing agent can cause handling problems. Failure to properly remove particles and chemicals from the mat may affect the barrier polishing step following the copper polishing step. In addition, in the case where the polishing solution is highly active, a polishing solution without honing particles can also be used with a non-honing polymer pad. The above process can also be performed using more than two polishing solutions. For example, copper polishing uses two different polishing solutions, and barrier layer polishing uses one polishing solution. This process can also be implemented using the CMP equipment shown in Figures 6a, 6b. Figure If is a flowchart 70 describing a specific aspect of a CMP process using three polishing solvents on the same mat. During the chemical mechanical polishing process 70 of a semiconductor wafer, individual wafers (or even a group of wafers if parallel polishing systems are used) must first be positioned for polishing on the pad (block 700), as described above. Next in process 70, a first copper polishing solution is supplied for rapid polishing of the copper layer 12 (block 710). Chemical mechanical polishing with the first copper polishing solution, which rapidly polishes copper, continues until the end of copper layer 12 is reached (checked at block 720). The first copper polishing solution is turned off, followed by cleaning of wafer 11 and pad (block 730). Degreasing the polishing solution on the mat is achieved by high pressure washing with deionized water and / or air blowing. At the same time, the wafer 11 itself can be cleaned by washing with deionized water and then rotating the wafer 11. After using the first copper polishing solution, the second copper polishing solution is transferred to a pad to remove remaining copper residue on the barrier layer 15 remaining on the top surface 17 of the area 14 (block 740). Alternatively, the first polishing step can be timed to use the first copper polishing solution to remove most of the copper, leaving only a layer of 500 to 2000 Angstroms thick, which is then polished using the second copper Solution to polish remove. The polishing rate of the second copper polishing solution is typically lower than that of the first copper polishing solution, leaving a smoother copper surface with a smaller number of defects. Once the second copper polishing solution is turned off and rubbed off (block 750), a third polishing solution for polishing the barrier layer 15 is transferred to the pad (block 760), and the barrier layer 15 is polished. The polishing of the barrier layer 15 using the third polishing solution continues until the end of the barrier layer 15 is reached (checked at block 770). Once the end of the barrier layer 15 is reached (once the top surface 17 of the area 14 is reached), the third polishing solution is turned off and the pad and wafer are cleaned 18 200308007 11 (block 780). Removal of the polishing solution remaining on the mat can be achieved by high pressure rinsing with deionized water similar to or the same as that used to remove the copper polishing solution followed by air blowing. The wafer 11 can also be cleaned and rotated. After the barrier is removed, the chemical mechanical polishing of wafer 11 is considered complete, and wafer 11 is ready for the next processing step. The next wafer (or group of wafers) can then be loaded (block 790). The process 70 is then repeated with new wafers (or clusters) according to blocks 700 to 790, as shown in If. As can be seen from the description, both the copper layer 12 and the barrier layer 15 are removed using the same pad and multiple polishing solutions in this procedure. As before, for this purpose, a mat for fixing an abrasive, a general mat or a polymer mat may be used. Either pad can be used to polish both the copper and the barrier layer, but in each case the composition of the polishing solution used may or may not be the same. In the example of process 70, the polishing pad may be a fixed honing agent type Mat, such as the MWR66 mat from 3M Company. The first copper polishing solution can be a honing agent-free solution with a high removal rate, such as the CPS-11 solution also available from 3M Company. With a pad applying approximately 1 psi of pressure to the surface of wafer 11, the copper removal rate of the CPS-11 solution was approximately 4000 A per minute. After polishing with CPS-11, some copper residue may remain on the barrier layer 15, or a certain thickness of copper may be intentionally left on the surface. This residue can be removed by polishing using a second copper polishing solution, which should primarily target the remaining residue and should have minimal etching effects on the copper in feature 16. This will minimize dishing. 19 200308007 The second copper polishing solution can be a honing agent-free solution with a low copper removal rate, such as the CPS-12 solution from 3M Company. The CPS-12 solution has a copper removal rate of about 1000 A per minute and removes copper residue from the top end of the barrier layer 15. To polish the giant on the same mat, a modified polishing solution from EKC can be used while the honing agent is reduced to 2% or less, as discussed above. As before, the modification of the EKC solution included a solution pH from 4. 0 to 5. 5. For example, increasing the pH can be achieved by adding ammonium hydroxide or hydroxylamine. Again, if the mat used is a general polymeric mat, such as Thomas West 711, the same polishing solution (CPS-11, CPS-12 and modified EKC with 2% honing agent) can still be used separately for copper And tantalum. Figure 2 illustrates another starting substrate to demonstrate the method of the present invention. Fig. 2 illustrates a starting substrate 11 'having a conformal copper layer, which can be manufactured using a conventional electrodeposition process such as ECD (electro-chemical deposition, electrochemical deposition). FIG. 2 illustrates a portion of an exemplary substrate 11 ', which typically includes a silicon wafer. The illustrated portion of the substrate 11 'includes a patterned insulating layer 14' or a dielectric material. For example, the holes 16 'or features of the trenches and vias are formed in the insulating layer 14, by using a well-known technique to etch away part of the insulating layer 14'. For example, a barrier layer 15 'of Ta or TaN or a Ta / TaN stacked layer is formed on the hole 16, the top surface 17' of the insulating layer 14 '. The thickness of the barrier layer 15 'may be on the order of 100 to 300 A or less. Although not shown, the barrier layer 15 'is lined with a thin copper seed layer to initiate copper growth on the barrier layer 15'. The copper layer 12 'is formed on the copper seed layer using a conventional conformal deposition process. For example, in a typical semiconductor device, the conductive layer 12 is deposited by 20 200308007 to a thickness of approximately 16 ′ and a thickness of 1.5 to 2. 00 times of copper. According to the principles of the present invention, as in the case of polishing a wafer 11 having a planar copper layer 12, the copper layer 12 'and the barrier layer 15' of the wafer 11 'can be polished and removed using the above-mentioned and the following specific aspects . The various stages of the polishing process are also performed as exemplified in Figures 1c and 1d above. For the sake of clarity, the following specific aspects will be described in conjunction with the figures la ~ Id for the case of polishing the planar copper layer and the underlying Ta barrier layer. However, the same specific aspect can be applied to the copper layer 12 'and the underlying Ta barrier layer 15' described with reference to FIG. The only difference is the thickness of the latter copper layer 12 ', where the process described may take more time than polishing the thin planar layer 12. Considering the difference in the thickness of the copper layers in Figures lb and 2, you will appreciate that the processing method shown in Figure 3 using two different polishing solutions will be more suitable for processing the copper layer 12 and the barrier layer 15 in Figure lb. The polishing solution chemicals are more suitable for removing the thick copper layer 12 'and the barrier layer 15' of FIG. Another option is to use two polishing solutions on the thicker copper 12 ', but the pressure on the wafer 11 can be increased to increase the removal rate of the first solution until a certain thickness of copper is removed (for example, three minutes) Bis) so far. The pressure can then be reduced while still using the first solution to remove the remaining copper. The second solution is then used to polish the barrier layer 15 '. Figure 3 is a flow chart of at least one specific aspect of the present invention using separate polishing solution circuits. Process 20 is a way to implement process 10 of FIG. 1e using two separate polished barley fluid lines. A wafer (or group of wafers) is positioned for polishing (block 200). The first polishing solution circuit (polishing solution circuit # 1) is then opened to supply the polishing solution to the polishing pad (block 210), while referring to Figures 6a, 6b. The polishing solution (such as 21 200308007 CPS-08) supplied by polishing solution line # 1 will be used to polish the copper layer 12 to its end point. The polishing solution line # 1 will remain open until the end of the copper is reached (checked at block 220). Once the end of the copper is reached, the polishing solution line # 1 is turned off (block 23). In order to remove the polishing solution from the line # 1 on the pad, the head holding the wafer 11 may be lifted on the pad, and the wafer n may be rinsed with deionized (DI) water, and then removed from the wafer 11 The surface bounces on the mat (block 235). The wafer 11 'is rotated at the same time and, if desired, the excess solution is removed by blowing a fluid such as air (block 235). Once the pad and wafer 11 have been cleaned, the polishing solution line # 2 is opened (block 240). The polishing solution supplied by the polishing solution line # 2 is used to polish the barrier layer 15 (for example, molybdenum) on the wafer 11. Polishing solution line # 2 will remain open until the end of barrier layer 15 is reached (checked at block 250). Once the end point is reached, the polishing solution line # 2 is turned off (block 255). To remove the polishing solution from line # 2 on the pad and wafer 11, the head holding wafer 11 is now raised on the pad and wafer 11 is rinsed with DI water (block 260). The wafer η can then be rotated to remove excess solution. The rinsed water bounces off the wafer 11 and falls on the mat, thereby being rinsed. Then blow on the pad to remove excess solution. Once the mat and wafer 11 have been cleaned, the next wafer (or group of wafers) is loaded (block 270), and process 20 repeats from block 200 for newly loaded wafers. Figure 4 is a flow chart of at least one specific aspect of the present invention using a separate polishing solution circuit. Process 30 is another polishing process using the same pad and two separate polishing solution lines. A wafer (or a group of wafers) such as wafer 11 is positioned for polishing (block 300). Then open two polishing 22 200308007 solution lines (polishing solution line # 1 and polishing solution line # 2) to supply the polishing solution to the polishing pad (block 310), while referring to Figures 6a, 6b. The components supplied by the polishing solution lines # 1 and # 2 are used to polish the copper layer 12 on the wafer 11. Polishing Solution Line # 1 supplies oxidants (such as hydrogen peroxide), complex reagents, and inhibitors. Polishing solution line # 2 supplies complex reagents and inhibitors but no oxidant. Complex reagents include chemicals such as organic acids and amines, while inhibitors are typically benzotriazQle (BTA). The complex reagent acts to increase the etch / polishing rate, while the inhibitor reduces this rate. Inhibitors are deposited in the area of feature 16. The inhibitor protects the copper surface in feature 16, so the complexing agent will not be excessively polished into these areas. This ensures that the polishing solution has a low static uranium engraving rate and helps to avoid dishing, even without the mechanical action of the pad. Although both polishing solution lines are open, the components supplied by polishing solution line # 2 will not adversely impact the polishing of copper because the components of each line share many common components. Therefore, the opportunities for interaction between the polishing solutions of the two lines are limited. The copper removal (polishing) rate increases with the oxidant concentration in the polishing solution and reaches a peak. However, the removal of barrier material such as molybdenum is less related to oxidant concentration and more to mechanical honing. The rinsing step between copper and molybdenum polishing on the same wafer described above ensures that the interaction between the two polishing solutions is minimized. However, if the two polishing solutions are compatible, no scrubbing or cleaning is required between copper and molybdenum polishing, that is, the same wafer is used except that the polishing solution circuit is switched from copper polishing solution to molybdenum polishing solution. From copper to molybdenum has been polished, there is no 淸 23 200308007 washing step. In another option when using a single polishing step to polish both copper and molybdenum, the two polishing solutions can be simplified to a single polishing solution circuit. The polishing solution lines # 1 and # 2 will remain open until the end point of the copper is reached (check at block 320). Once the end of copper is reached, the polishing solution line # 1 is turned off (block 330). Since polishing solutions in polishing solution lines # 1 and # 2 are somewhat compatible, DI water rinse and then spin wafer 11 or blow air on the mat to remove the aforementioned solution and DI water washing solution are optional, but it is possible No need. Polishing solution line # 2 therefore remains open. The polishing solution supplied by the polishing solution line # 2 is used to polish the barrier layer (giant) 15 on the wafer 11. Once the end of the molybdenum is reached, the polishing solution line # 2 is turned off (block 355). To remove the polishing solution from line # 2 on wafer 11, rinse with DI water, then spin to remove excess solution (block 360). Once wafer 11 and mat are cleaned, the next wafer (or group of wafers) is loaded (block 370), and process 30 repeats from block 300 for the newly loaded wafer. Fig. 5 is a flow chart showing a specific aspect of at least one of a component circuit and an oxidant circuit according to the present invention. Process 40 is another polishing process using the same pad and two separate lines, one containing a polishing solution and the other containing an oxidant. The wafer (or group of wafers) is positioned for polishing (block 400). Then open two lines (polishing solution line and oxidant line) to supply the polishing solution and oxidant to the polishing pad (block 410). The components supplied by the polishing solution circuit and the oxidizing circuit are used to polish the copper layer 12 on the wafer 11. The polishing solution circuit supplies mismatched reagents and inhibitors. The oxidant line supplies an oxidant, such as hydrogen peroxide. The rate of copper removal (polishing) increased with increasing oxidant concentration 24 200308007 i 'and reached a peak. However, the removal of molybdenum is more independent of oxidant concentration 'and more related to mechanical honing. The polishing solution circuit and oxidant circuit will remain open until the end point of the copper is reached (checked at block 420). Once the copper end point is reached, the oxidant line is turned off (block 430). Since the polishing solution circuit and the oxidant circuit solution are somewhat compatible, DI water washing and then rotating the wafer 11 and the mouth heating can be unnecessary on the mat. The polishing solution provided by the polishing solution circuit remains open. The polishing solution supplied by the polishing solution circuit is then used to polish the molybdenum layer 15 on the wafer 11 to its end point (the top 17 of the region Η). Once the giant end point is reached, the polishing solution circuit is turned off (block 455). You can use over-polishing beyond the end point to get rid of possible residues. To clean wafer 11 ', wafer n is rinsed with DI water, and wafer u is rotated at the same time (block 460). This also hits the mat and cleans it. Once the mats and wafers have been cleaned, the next wafer (or group of wafers) is loaded (block 470), and process 40 repeats from block 400 for newly loaded wafers. Figures 6a, 6b illustrate side and plan views of a polishing station constructed in accordance with one or more embodiments of the present invention. The wafer polishing station 50 includes a plurality of polishing members and a wafer housing 540 or a wafer carrier. The wafer cover 540 firmly positions the wafer 550 so that the front side 560 of the wafer 550 is completely exposed. The wafer polishing station 50 includes a polishing pad 510 that polishes the front surface 560, a mechanism (not shown) that drives the polishing pad 510 in a bi-directional linear or reciprocating (back-and-forth) motion, and supplies fluid as the exposed surface 560 is polished by the pad 510 The support plate 520 is supported to the back of the mat 510. Bidirectional linear motion is also called opposite linear motion. The bottom surface of the polishing pad 510 can be additionally attached to the elastic 25 200308007 but strong material (not shown) to support the pad 510. The polishing pad 510 is used to polish both the copper of the surface 560 and a barrier layer (e.g., tantalum). The use of a single pad on the two layers of the exposed wafer surface 560 eliminates the need for separate pads, and may also eliminate the need for separate polishing stations. The polishing pad 510 may be a hob-free agent, such as a polymeric pad, or a honing agent-fixing pad. Since the macro and copper layers have different characteristics, if they are to be polished with the same pad, different polishing solutions must be used. It should be noted that the two-way linear polisher is preferably used as a polishing station 50, for example, as described in US Patent No. 6,103,628 and US Patent Application No. 09 / 684,059, both of which are explicitly considered here as reference. When used in this way, the polishing pad 510 is preferably a belt, a part of which moves bidirectionally in the processing area, which may or may not contain a fixed honing agent, and preferably floats on the platform support in the polishing area 520 on. In addition, the straps can be moved gradually, so that different parts of the same strap are used at different times (different parts can overlap or not overlap with previously used parts in the processing area), and different times can be or not It is distinguished by the processing solution used. Although polishing stations of the type described above are currently preferred, the invention is not limited to the use of such polishing stations. Instead, the process described here can be used with other CMP polishing stations, including those that use linear rotating belts, stationary polishing pads and moving wafers, rotating polishing pads that move against stationary or rotating wafers, Or the other. In addition, thin and less rigid mats and thicker and more rigid mats can be used, depending on the desired effect. The back of the mat can be with or without a support plate. The polishing solution and washing solution used during polishing are preferably supplied to the polishing station 50 using a bidirectional linear polisher in two 26 200308007 or more polishing solution lines (for example, line # 1 and line # 2). In at least one specific aspect of the present invention, the polishing solution line # 1 includes a left supply line 512 and a right supply line 511. Similarly, the polishing solution line # 2 includes a left supply line 514 and a right supply line 513. Supply lines 511 and 513 supply the right side of the polishing station 50, and supply lines 512 and 514 supply the left side of the polishing station 50. Although not shown in Figs. 6a, 6b, 7a, 7b, it will be appreciated that the polishing station 50 may have more than two polishing solution lines (eg, line # 3, not shown), which is the same as other lines # 1 and # 2 Do a similar build and have individual supply lines. This configuration with line # 3 can be used for the specific aspect described in Figure If. Another option is to keep the number of nozzles the same, but you can use a valve to bring different polishing solutions through the same nozzle. Many ways to achieve this will be apparent to those skilled in the art. Now, the polishing of the wafer 550 will be described in accordance with various specific aspects of the present invention. In a specific aspect, after the wafer 550 is loaded into the housing 540 and positioned above the polishing station 50, the polishing solution line # 1 is opened to supply the polishing solution to the left and right sides of the pad 510. When the polishing solution line # 1 is opened, the right supply line 511 and the left supply line 512 actively supply the polishing solution to the mat 510. The right supply line 513 and the left supply line 514 will be closed. The pad 510 is driven by the mechanism 530, and this movement combines the chemical reactivity of the polishing solution of the polishing solution line # 1 on the surface 560 of the wafer 550 to polish the copper on the surface 560. It should be noted that for the system of Figures 6a, 6b, the transfer of the polishing solution can also be combined with the movement of the pad 510 27 200308007. For example, when the pad 510 is moved to the left, the polishing solution is discharged from the nozzle 511, and when the pad 510 is moved to the right, the polishing solution is discharged from the nozzle 512. In this manner, the polishing solution is always moved toward the wafer 550 by the moving pad 510. Waste of polishing solution is minimized. Once the copper end point is reached, switch off polishing solution line # 1. This requires the supply lines 511 and 512 to be cut or rendered inoperative. In order to remove the front surface 560 of the wafer 550 and the remaining polishing solution on the pad 510, when the wafer 550 is lifted over the pad 510, the deionized water nozzle sprays water toward the wafer surface 560. Water bounces off the wafer 550 and falls on the surface of the mat 510, and cleans both the wafer 550 and the surface of the mat 510. During this cleaning step, the wafer 550 is preferably rotatable. After spraying water, a blower 580 blows air onto the mat 510 to remove excess solution. Second, the polishing solution line # 2 is opened, so the right supply line 513 and the left supply line 514 will actively supply the polishing solution to the right and left sides of the pad 510, respectively. The polishing solution supplied by the polishing solution line # 2 is designed for polishing a barrier layer (eg, giant). For the movement of the pad 510 on the surface 560 and the polishing solution of the polishing solution line # 2, the molybdenum on the surface 560 of the wafer 550 is polished. Once the end of the molybdenum is reached, turn off polishing solution line # 2 (making supply lines 513 and 514 inoperative), clean pad 510 (using decanter 570), and remove excess solution (using blower 580), then The next wafer is loaded into the cover 540 for polishing. The scrubber 570 and the hair dryer 580 can be implemented in a variety of ways, including the use of high pressure nozzles. Exemplary types of polishing solutions and pads suitable for such polishing have been discussed above. In some specific aspects of the invention, polishing solution line # 1 28 200308007 supplies complex reagents, inhibitors, and oxidants. Polishing solution line # 2 supplies the wrong reagents and inhibitors, but does not have oxidants or supplies very low concentrations of oxidants. In this particular aspect, during copper polishing, both polishing solution lines # 1 and # 2 may be open (hence all four supply lines 511, 512, 513, and 514 are open). After copper polishing, the polishing solution line # 1 may be turned off, leaving only the supply lines 513 and 514 of the polishing solution line # 2 functioning (open). In other specific aspects, polishing solution line # 2 will pass complex reagents and inhibitors, while polishing solution line # 1 will only pass oxidants. Again, during polishing of copper, both lines # 1 and # 2 may be turned on, and then polishing solution line # 1 may be turned off for giant polishing. Figures 7a, 7b illustrate detailed views of polishing a wafer using a pad as in the specific aspect described above. Referring back to FIG. 1b, the wafer 11 to be polished has multiple layers, including a copper layer 12 and a barrier layer 15. Before polishing, the exposed front side 645 will first expose the copper layer 12 for polishing. After the copper layer 12 is polished, the resulting wafer 11 will expose the underlying barrier layer 15 (see Fig. Lc). The wafer 11 is positioned so that its front side 645 abuts the surface of the polishing pad 640. Reference is made to Fig. 7a, which shows a polishing station in polishing mode. The polishing solution is supplied to both sides of the polishing pad 640 by two polishing solution lines (line # 1 and line # 2). In at least one specific aspect of the present invention, the polishing solution line # 1 includes a left supply line 612 and a right supply line 611. Similarly, polishing solution line # 2 includes a left supply line 614 and a right supply line 613. Supply lines 611 and 613 supply the right side of polishing pad 640, and supply lines 612 and 614 supply the left side of polishing pad 640. In a specific aspect, the polishing solution from line # 1 contains chemicals that oxidize 29 200308007 and chemically remove the copper layer 12 on the surface 645 and is supplied between the wafer 11 and the polishing pad 640. After the copper layer 12 is polished, the polishing solution line # 1 is turned off. The wafer 11 is raised above the mat 640, as shown in Fig. 7b. When the wafer 11 is in the position shown in FIG. 7b, the deionized water cleaning agent (containing 0 ~ 〇. 〇1% corrosion inhibitor) removes the polishing solution on the wafer 11, and then bounces off the wafer 11 (on the front side 645) onto the pad 640, and removes the polishing solution on the pad 640. The water used to wash the pad 640 may remain on the pad 640, which may adversely dilute the next polishing solution. A blower 680 blows air onto the mat 640 to minimize dilution of the next polishing solution. After the rinsing, the wafer 11 returns to the position shown in FIG. 7a. Then, the polishing solution line # 2 is opened, and a polishing solution is supplied to polish the barrier layer 15. The barrier layer 15 is exposed after the copper layer 12 is polished and removed. The function of the pad 640 is to polish the layer 15 on the wafer 11 together with the polishing solution from the polishing solution line # 2. The wafer Π can then return to the position of FIG. 7b to perform final cleaning of the wafer 11 and the pad 640. In other specific aspects of the invention, both polishing solution line # 1 and polishing solution line # 2 may be opened at the beginning. In this case, polishing solution line # 1 will contain the same ingredients as polishing solution line # 2, but additional oxidant ingredients will also be transmitted. Both the polishing solution line # 1 and the polishing solution line # 2 polish the copper layer 12. After the copper layer 12 is polished, the polishing solution line # 1 is turned off, leaving the polishing solution line # 2 open. The polishing solution line # 2 does not transfer or transfer an extremely low concentration of an oxidizing agent, and the polishing barrier layer 15 is polished. In another embodiment of the present invention, polishing solution circuit # 2 transmits polishing components (such as complex reagents and inhibitors), while polishing solution 200308007 circuit # 1 transmits only oxidants. Again, in this case, during the polishing of the copper layer 12, the polishing solution lines # 1 and # 2 are turned on, and then during the subsequent polishing of the barrier layer 15, the oxidant line (polishing solution line # 1) is turned off . When the two circuits are opened in this way, the oxidant from polishing solution circuit # 1 and the components from circuit # 2 will need to be well mixed on the mat 640 to ensure that the entire solution is evenly distributed on the mat 640. In one or more embodiments of the present invention, the polishing pad is described as being composed of one type, either a fixed honing agent type or a polymer type. In another aspect of the present invention that can be selected, it is also possible to separate or distinguish a single mat into one or more fixed honing agent sections and one or more polymerizing sections. When each segment of the pad is needed to provide the best processing power for the chemical mechanical polishing of a particular layer on the wafer, the pad can be advanced or retracted to place the appropriate section of the pad in the position of the polished wafer. Therefore, the section where the honing agent is fixed may be used when polishing the copper layer, and the softer polymer section may be used when polishing the barrier layer. The reciprocating motion and specific design of the preferred system of Figure 6a allow this flexibility. As mentioned previously, the polishing techniques described herein can be performed using a single polishing pad in a single CMP station, or using multiple polishing pads in multiple CMP stations. As described above, in a specific aspect, the removal of the copper layer and the barrier layer can be performed in the same CMP station. In this specific aspect, the removal of the copper layer may be performed before the removal of the barrier layer. According to this process sequence, in the first step, the entire copper can be removed down to the barrier layer using a polishing pad with a fixed abrasive. In this copper removal step, the polishing solution may or may not contain particles. In the second step, the 31 200308007 polishing pad holding the honing agent can be used in combination with a polishing solution with solid particles to remove the remaining copper layer on the surface of the barrier layer while exerting a downward force on the workpiece. This downward force may be a relatively low downward force. After these steps, the barrier is removed. Removal of the barrier layer can be performed using a soft polymer portion of the polishing pad. That is, the polishing pad may have a portion where the honing agent is fixed and a second portion made of a soft polymer. The solution for selective polishing of molybdenum can be transferred to a polishing pad to remove the barrier layer while applying a low downward force to the workpiece. In another embodiment, the removal of copper and barrier layers can be performed on individual polishing pads using an integrated CMP system (integrated CMP tool). In a specific aspect of the invention, different pads are located in individual CMP stations in the same tool. An exemplary CMP station suitable for an integrated CMP system is described above with reference to FIG. 6a, and can also refer to U.S. Patent Application No. 10 / 346,425 (NT-278-US) filed on January 17, 2003, which The title is "Advanced Chemical Mechanical Polishing System with Smart Endpoint Detection", which is hereby incorporated by reference. By incorporating multiple CMP stations into one integrated tool, it is possible to improve different polishing of copper and barrier layers. Figure 8 shows a block diagram of an integrated CMP system 800 with multiple CMP stations according to a specific aspect of the present invention. In the specific aspect shown, the integrated CMP system 800 has a first CMP station 810 and a second CMP station 820. In the first CMP station 810, during the first polishing process, the copper layer is removed using a first polishing pad (not shown) and a first polishing solution. In a certain aspect of the invention 32 200308007, the first polishing pad is a polishing pad to which a honing agent is fixed, and the first polishing solution contains honing and / or lubricating particles. In this regard, when the honing particles are combined with a polishing pad with a fixed honing agent, the particles can be used as a polishing lubricant. Honed particles are solid particles in a slurry. During the first polishing process, the wafer is lowered onto the first polishing pad, and the first polishing solution is transferred onto the first polishing pad. The first polishing pad is moved above the support plate (see Fig. 6a), while applying fluid pressure under the first polishing pad. Once the copper layer is removed downward to reach the barrier layer on the wafer surface (see FIG. 1c), the barrier layer removal process is performed at the second CMP station 820 (second polishing process). The second CMP station 820 has a second polishing pad (not shown) and uses a second polishing solution. The second polishing pad may be a polishing pad of a polymeric / non-fixed honing agent. For example, the second polishing pad may be made of a soft polymeric material such as polyurethane. In one aspect of the invention, a selective polishing solution is used as the second polishing solution during the removal of the barrier layer. In this regard, the selective polishing solution is transferred to a polymeric polishing pad suitable for removing the barrier material, and the pad is moved for polishing. Fluid pressure may be applied under the second polishing pad. Using these techniques minimizes stress on the wafer and the resulting delamination. These techniques also minimize dish-like conditions and scratches. The use of two CMP stations in an integrated CMP system is just an example. An integrated CMP system with additional CMP stations is also conceivable. FIG. 9 is a flowchart of a specific aspect of a method for polishing copper and barrier layers of a semiconductor wafer using an integrated CMP system having multiple CMP stations, such as the CMP system described with reference to FIG. 8. In step 910, the first layer of the semiconductor wafer is polished using a polishing solution on the first portion of the polishing pad 33 200308007. In a specific aspect, the first layer includes copper. At step 920, a second layer of the semiconductor wafer is polished using a polishing solution on the second portion of the polishing pad. In a specific aspect, the second layer includes molybdenum. It will be understood that more than two layers can be polished and more than two parts of the polishing pad can be used. The polishing solution used to polish different layers can be the same polishing solution or different polishing solutions. Different parts of the polishing pad can be located on the same polishing pad or on different polishing pads. Individual polishing solutions and pads are preferably designed and / or suitable for polishing specific layers of a wafer. For example, the solution and pad may be suitable for polishing copper or a barrier layer (e.g., molybdenum). According to the invention, typically only one wafer is polished at a time. Although the present invention is suitable for polishing a single wafer at a time, those skilled in the art can modify the preferred embodiment of the present invention to polish multiple wafers at one time. It should be understood that: In the discussion and the scope of the attached patent application, the terms "wafer surface" and "surface of the wafer" include, but are not limited to, the surface of the wafer before processing And the surface of any layer formed on the wafer, including oxidized metals, oxides, spin-on glass, ceramics, etc. In addition, although the two layers of polishing are mainly discussed above, namely a metal layer (such as copper) and a barrier layer (such as Ta), the techniques described herein can be used to polish any number and kind of layers, such as to fix Abrasive pads provide a variety of polishing solutions suitable for each layer. It will be understood that removing a layer from the surface of a semiconductor wafer is synonymous with a layer on the surface of a polished semiconductor wafer. In the various methods described herein, "block" and "step" both refer to processing steps. Although various preferred embodiments of the present invention have been disclosed for the sake of illustration, 34 200308007, those skilled in the art will appreciate that, without departing from the scope and spirit of the present invention as disclosed in the scope of patent application, various modifications, Additions and / or substitutions are possible. [Brief Description of the Drawings] (1) Partial drawing of the drawing illustrates a cross-sectional view of a semiconductor wafer before a copper layer is deposited thereon; FIG. 1b illustrates a cross-sectional view of the semiconductor wafer shown in FIG. A conductive layer has been deposited on the top of the wafer; FIG. 1c illustrates a cross-sectional view of the semiconductor wafer shown in FIG. 1b after the copper layer is polished according to one or more specific aspects of the present invention; Id illustrates a cross-sectional view of the layers of the semiconductor wafer shown in FIG. 1c, which is after polishing the barrier layer according to one or more specific aspects of the present invention; FIG. Flowchart of one or more specific aspects of two different polishing solutions; FIG. If is a flowchart of one or more specific aspects of three different polishing solutions on the same mat according to the present invention; A cross-sectional view of a semiconductor wafer is shown, in which a thick conductive layer has been deposited on the top of the wafer; FIG. 3 is a flowchart of at least one specific aspect of the present invention using separate polishing solution lines; FIG. 4 is a flowchart of the present invention At least one of the separate polishing solution circuits has a flow chart of 35 200308007. Figure 5 is a flowchart of at least one specific aspect of the composition circuit and oxidant circuit of the present invention. Figures 6a and 6b illustrate one or A side view and a plan view of a polishing station constructed by a plurality of specific aspects; Figures 7a, 7b illustrate detailed views of polishing a wafer using a single pad according to one or more specific aspects of the present invention;
圖8顯示根據本發明的一或多個具體態樣而具有多個 CMP站之整合CMP系統的方塊圖；以及 圖9是拋光半導體晶圓之銅和阻障層的方法之具體態 樣的流程圖，其乃使用具有多個CMP站之整合CMP系統FIG. 8 shows a block diagram of an integrated CMP system having a plurality of CMP stations according to one or more specific aspects of the present invention; and FIG. 9 is a specific aspect flow of a method for polishing copper and barrier layers of a semiconductor wafer Figure, which uses an integrated CMP system with multiple CMP stations
如參考圖8所描述的CMP系統。 )元件代表符號 10 化學機械拋光的過程 11 > 1Γ 基板 12 、 12， 平面狀導電層 14 、 14， 絕緣層或區域 15 、 15， 阻障層 16 、 16， 空穴或特徵 17 、 17， 頂面 20 化學機械拋光的過程 30 化學機械拋光的過程 40 化學機械拋光的過程 50 晶圓拋光站 36 200308007 70 510 511 512 513 514 520 540 550 560 570 580 611 612 613 614 640 645 670 680 800 810 820 化學機械拋光的過程 拋光墊 右側供應線路 左側供應線路 右側供應線路 左側供應線路 支承板 晶圓外罩 晶圓 晶圓的正面 淸洗器 吹風機 右側供應線路 左側供應線路 右側供應線路 左側供應線路 拋光墊 晶圓的正面 淸洗器 吹風機 整合的CMP系統 第一CMP站 第二CMP站 37A CMP system as described with reference to FIG. 8. ) Element representative symbol 10 Process of chemical mechanical polishing 11 > 1Γ substrate 12, 12, planar conductive layer 14, 14, insulating layer or region 15, 15, barrier layer 16, 16, cavity or feature 17, 17, Top surface 20 Chemical mechanical polishing process 30 Chemical mechanical polishing process 40 Chemical mechanical polishing process 50 Wafer polishing station 36 200308007 70 510 511 512 513 514 520 540 550 560 570 580 611 612 613 614 640 645 670 680 800 810 820 Chemical mechanical polishing process polishing pads right supply line left supply line right supply line left supply line support plate wafer cover wafer wafer front scrubber blower right supply line left supply line right supply line left supply line polishing pad wafer Front scrubber blower integrated CMP system first CMP station second CMP station 37