CN1653600A

CN1653600A - Method and apparatus for integrated chemical mechanical polishing of copper and barrier layers

Info

Publication number: CN1653600A
Application number: CNA038109743A
Authority: CN
Inventors: 哈马洋·达理; 布兰特·巴萨尔; 德格拉斯·杨; 王育诚; 图安·杜安鲁
Original assignee: ASM Nutool Inc
Current assignee: ASM Nutool Inc
Priority date: 2002-03-13
Filing date: 2003-03-13
Publication date: 2005-08-10
Also published as: WO2003079428A1; US20040023607A1; EP1483785A1; TW200308007A; AU2003224233A1

Abstract

The invention relates to a polishing method for a plurality of layers on the semiconductor wafer surface, comprising the following steps: the first part of the polishing pad is polished by polishing solution, such as the first layer of copper and the other part of the polishing pad is polished by polishing solution to form another layer of the barrier layer; wherein, each layer can use same or different polishing solution; similarly, different parts of the polishing pad had better polish a corresponding wafer layer and the different parts of the polishing pad can sit in the same pad or different pads; simultaneously, the patent of two different supplying lines sending polishing solution to a single polishing pad is applied.

Description

The method and apparatus of the integrated chemical mechanical polishing of copper and barrier layer

Related application

This case is the U.S. patent application case sequence number of submitting on January 17th, 2,003 10/346, the U.S. patent application case sequence number 10/199 that 425 (NT-278-US) and on July 19th, 2002 submit to, the continuous application case of the part of 471 (NT-258-US), it all and in this thinks reference.

The claims of this case is based on the U.S. Provisional Patent Application case of submitting on October 10th, 2002 the 60/417th, the U.S. Provisional Patent Application case the 60/365th that No. 544 (NT-278-P2) and on March 13rd, 2002 submit to, the priority of No. 001 (NT-237-P), it all and in this thinks reference.

Invention field

The present invention is relevant with the field of chemico-mechanical polishing.Especially the invention relates to the integration finishing method and the equipment of copper and barrier layer.

Background of invention

Traditional semiconductor element generally comprises conductive path or the interconnects that semiconductor substrate (normally silicon substrate) and a plurality of dielectric intermediary layer (for example silicon dioxide) that forms in regular turn and electric conducting material are done.Because copper and copper alloy has excellent electron transfer and low resistance characteristic, they are recently in the attention that is subjected to certain degree aspect the conductor of interconnects.Interconnects is normally inserted the feature that is etched in the dielectric intermediary layer partly or hole and forming with metallized process with copper.The method for optimizing of copper metallization process is to electroplate.In integrated circuit, laterally extend with respect to substrate surface at multi-level interconnects networking.The interconnects that forms in the sequence intermediary layer can be used via or contact and be electrically connected.

In a typical process, at first on semiconductor substrate, form the insulation intermediary layer.Carry out sample preparation and etching process for example in insulating barrier, to form feature such as groove, via or dual-metal inserting (dual damascene) structure partly.Electro-coppering is to fill all features then.Yet the plating process can form the copper layer simultaneously in the feature part and on the substrate surface.Surperficial then unnecessary copper capping layer can be removed before subsequent processing steps.

After sample preparation and etching, insulating barrier can cover with barrier layer earlier traditionally, and it is typically tantalum or tantalum/tantalum nitride composite bed.The end face that barrier layer covers via and groove and insulating barrier to be guaranteeing that good adhering to arranged, and passes insulating barrier as resistance barrier material to avoid copper to be diffused into the semiconductor device neutralization.Secondly deposition kind of brilliant (conduction) layer on barrier layer it typically is the copper layer.Plant crystal layer and formed the electric conducting material substrate, between follow-up copper depositional stage, to grow up for copper film.Along with copper film is electroplated, the copper layer has been filled via apace, but with groove and surface along the mode covering wide of shape.When this deposition process continues just to have formed thick copper layer or unnecessary cover layer when guaranteeing that groove also is filled on substrate.After copper facing, adopt CMP (chemicalmechanical polishing, chemico-mechanical polishing) process to come comprehensive equating traditionally, and the thickness of copper layer is reduced to the height on barrier layer surface.In order to fill the feature part electrical isolation of copper, remove this barrier layer with another CMP step thereafter.

In semiconductor industry, VLSI (Very Large Scale Integration, greatly type is integrated) and the semiconductor crystal wafer chemico-mechanical polishing (CMP) of ULSI (Ultra Large Scale Integration, ultra-large type is integrated) application program have important and purposes widely.CMP is the process of semiconductor crystal wafer equating and polishing, and it combines, and for example the chemistry of layer such as insulator and metal is removed and the mechanical damping of crystal column surface.CMP also is used for after the crystal growth and the wafer equating/polishing during the wafer manufacture process, and provides the process of the comprehensive equating of crystal column surface.For example, in ic manufacturing process, CMP is usually used in equating/polishing and tires out the profile that increases in multi-level metal interconnects system.In order to reach the desired flatness of crystal column surface, desired surface must be not contaminated.Get rid of effective circuit when simultaneously, the CMP process must be avoided polishing partly.

The legacy system of semiconductor crystal wafer chemico-mechanical polishing will be described now.A kind of traditional CMP process need is positioned wafer on the support bracket, and it is around first rotation, and drops to around on second polishing pad of doing reverse rotation.In the equating process, the wafer support bracket is depressed into wafer and props up polishing pad.During polishing wafer, the polishing solution that can apply polishing agent for example or slurries on the typical case is to polishing pad.The material behavior that the inclusion of polishing solution will be removed during according to CMP is decided.For instance, if this material is metallic, then polishing solution can be made up of any one or many persons in the middle of grinding agent, oxidant, complex reagent (etch chemistries), inhibitor and/or the surfactant.Oxidant oxidation in the polishing solution surface of metal material, simultaneously already oxidised metal material is owing to chemically and mechanically removed with mat or abrasive flour or grinding that both frictions caused.Etch chemistries can be used for increasing the polishing speed of metal material.

In the traditional CMP process of another kind, the wafer support bracket is the wafer location and be depressed into the polishing pad that props up band shape, and mat moves on respect to the identical linear direction of wafer continuously simultaneously.In this polishing process, so-called banded polishing pad can move on a continuous path.These traditional polishing process may further include one and regulate the station, and it is positioned on the path of polishing pad, to regulate mat during polishing.The factor of being wanted flatness and flatness to reach need be controlled and the pressure between polishing time, wafer and the mat, the speed of rotation, the particle size of slurries, the feed rate of polishing solution, the chemical property of polishing solution and the material of mat can be comprised.

Though above-mentioned CMP process is extensive use of and accepts by semiconductor industry, still also has challenge.Owing to the material that copper layer, barrier layer and other layers that need accept to polish be used is variant in nature, so that traditional system generally includes different polishing solutions and the dissimilar polishing pad that is used for different layers.This usually means that the copper layer must use a certain mat to polish, and barrier layer must use diverse mat to remove.Simultaneously, the difference that pad material and polishing solution are formed can cause unexpected side effect, for example causes in other non-layers that polishing and corrodes or depression.This has increased the time in the polishing process, cost, defect rate and complexity.

Specific, polishing technology has attempted solving the problem of the polish copper layer on the tantalum barrier layer.It should be noted, also pile up applicable to tantalum nitride resistance barrier thing and tantalum/tantalum nitride all about the narration of tantalum resistance barrier thing.

The CMP instrument of prior art is complicated and expensive machine.The finishing method and the equipment that need a cover integration are arranged now, be used for simultaneously effectively polishing tantalum and copper, to reduce cost and complexity and shortening required time of polished semiconductor wafer.

Summary of the invention

The present invention has overcome the restriction of listed traditional chemical mechanical polishing, and the technology of polishing multilayer workpiece is provided.

In one or more embodiment of the present invention, use identical mat to come a plurality of layers of polished semiconductor wafer.The different polishing solution of supply when this is different each layer formed of mat polishing and reaching.In one embodiment, at first use first polishing solution that is sent to mat to come the polish copper layer.Afterwards, use second polishing solution that is sent on the identical mat to polish the barrier layer of same wafer.After each layer polishing, can use irrigation to clean mat and/or wafer, next can use or not use air blowing or rotary course to remove excessive solution.In other alternate embodiments, the removal of copper and barrier layer can utilize the integration CMP system that uses more than a plurality of polishing pads or the single polishing pad partly to carry out.In addition, multiple polishing solution can combine with a plurality of polishing pads, causes best polishing efficiency to reach.

In other embodiments of the invention, in different CMP stations, use different polishing solutions to come a plurality of layers of polished semiconductor wafer.In one embodiment, at first use first polishing solution of the mat that is sent to a CMP station to come the polish copper layer.Afterwards, in the 2nd CMP station, use second polishing solution to polish the barrier layer of same wafer.

Brief description of drawingsfig

Figure 1A graphic extension semiconductor crystal wafer is at the profile of copper layer before thereon;

The profile of the semiconductor crystal wafer shown in Figure 1B graphic extension Figure 1A, wherein plane conductive layer has been deposited on the top of wafer;

The profile of the semiconductor crystal wafer shown in Fig. 1 C graphic extension Figure 1B, it ties up to one or more embodiment according to the present invention and comes polish copper layer situation afterwards;

The profile of each layer of semiconductor crystal wafer shown in Fig. 1 D graphic extension Fig. 1 C, it ties up to one or more embodiment according to the present invention and polishes barrier layer situation afterwards;

Fig. 1 E is the present invention uses one or more embodiment of two kinds of different polishing solutions on identical mat a flow chart;

Fig. 1 F is the present invention uses one or more embodiment of three kinds of different polishing solutions on identical mat a flow chart;

The profile of the semiconductor crystal wafer shown in Fig. 2 graphic extension Figure 1A, wherein thick conductive layer has been deposited on the top of wafer;

Fig. 3 is the flow chart that the present invention uses at least one embodiment of polishing solution circuit separately;

Fig. 4 is the flow chart that the present invention uses at least one embodiment of polishing solution circuit separately;

Fig. 5 is the flow chart that the present invention uses at least one embodiment of composition circuit and oxidant circuit;

Fig. 6 A-B graphic extension is according to the end view and the plan view of the polishing station of one or more embodiment institute construction of the present invention;

Fig. 7 A-B graphic extension one or more embodiment according to the present invention uses single mat to come the detailed view of wafer polishing;

Fig. 8 shows that one or more embodiment according to the present invention has the calcspar of integrating the CMP system at a plurality of CMP station; And

Fig. 9 is the flow chart of the embodiment of the copper of semiconductor crystal wafer and barrier layer finishing method, and it is to use the integration CMP system with a plurality of CMP station, for example with reference to the described CMP of figure 8 system.

Accompanying drawing describes in detail

The multilayer workpiece that The present invention be directed to semiconductor crystal wafer for example is the method and apparatus of chemico-mechanical polishing in addition.Multiple technologies described herein can involve single polishing pad or a plurality of polishing pad.In addition, these technology can involve single polishing solution or multiple polishing solution.Moreover, can utilize the single part of polishing pad or a plurality of parts of single polishing pad (each partly has different compositions)." polishing pad " speech can exchange with " polishing member " and speech such as " sand belts "." wafer ", " semiconductor crystal wafer ", " workpiece " and speech such as " substrates " can exchange.

In one embodiment, first kind of polishing solution of supply is to polish for example ground floor of copper layer.Once the terminal point that reaches the copper layer, first kind of polishing solution of stop supplies then, and cleaning wafer and mat.Use, when certain one deck is removed from the top of beneath layer and under exposing during layer, then can be described as having reached this terminal point at this point.Supply second kind of polishing solution then, on identical mat, to polish for example second layer of barrier layer.In another embodiment, first kind of polishing solution of supply on mat with high speed polishing part copper layer, supplied second kind of polishing solution then, to remove remaining copper layer, next re-uses the third polishing solution to remove barrier layer.

About used polishing solution, polishing solution can be the multiple polishing agent that does not have polishing particles, or has the slurries of polishing particles, and this depends on the mat type that is used to polish and desired polishing type and decides.For example, polishing pad can comprise the grinding agent that is built in the mat front, and introduces the polishing agent that does not contain polishing particles; Perhaps can use the polishing pad that does not contain the built-in grinding agent of this kind, and transfer to use slurries; Perhaps can use some other combinations of belt, slurries and/or polishing agent.Polishing solution can comprise the chemicals with material oxidation, and this material is mechanically removed from wafer then, and this can further describe hereinafter; Polishing solution also can comprise the polishing particles of being made by glue-like silica or smoked silicon.Polishing agent or slurries generally grow the thin layer of silicon dioxide or silica on the front of wafer, and the cushioning effect of mat is mechanically removed this oxide.The result has removed the high profile on the crystal column surface, till reaching extremely flat surface.

Return and state first embodiment, arrive after the polishing end point of copper layer, the supply discontinuity of first kind of polishing solution so begins to carry out the polishing of barrier layer with second kind of polishing solution.The embodiment of these and other all uses identical mat to come polish copper and barrier layer.The equipment that carries out these and other embodiment is to connect in tandem and control essential polishing solution circuit.For the present invention, the polishing solution circuit is to be embodied in the polishing solution delivery system.

When discussion is of the present invention, will divides and state specific copper layer, barrier layer, polishing solution, mat and other component part indescribably.These are carried stating to venerate and illustrate, because should be expressly understood that layer, polishing solution, mat and other component parts of any form, mode and kind, all can comply with the purposes of wanting, polishing system and/or wafer and suitably replacement.For instance, in description, the copper layer of deposition and beneath kind crystal layer all are commonly referred to the copper layer, and barrier layer then is called tantalum layer.These descriptions are to depend on used wafer to form and each layer of just handling at that time and deciding, and should not be considered as limiting by any way the present invention.

Simultaneously, describing when of the present invention, " the identical mat " stated carried by institute also can comprise the partly different of a mat, and in all examples, " mat of identical type " be meant each of mat different partly (if any) in similar combination ingredient.When describing each diagram, identical reference number can be used to refer to identical member and identical structure.

Figure 1A graphic extension generally includes the some of the exemplary substrate 11 of Silicon Wafer.The graphic extension of substrate 11 partly comprises the insulating barrier 14 of sample preparation or comprises the zone of dielectric material.For example the hole 16 of groove and via or feature partly are that mat uses the technology of knowing, and insulating barrier 14 etching offs are partly formed in insulating barrier 14.Feature 16 can expose substrate surface partly.For example the barrier layer 15 of tantalum or tantalum nitride or tantalum/tantalum nitride stack layer is in hole 16 and the end face 17 of insulating barrier or region surface on form.The thickness of barrier layer can be the grade at 200-300 .Though Figure 1A-1E does not show that barrier layer 15 is that lining approaches copper kind crystal layer with one, grows on barrier layer to cause copper.For example the plane conductive layer 12 of copper layer is to use ECMD (electrochemical mechanical deposition, electrochemical mechanical deposition) method and form on copper kind crystal layer.For instance, the thickness of copper layer 12 is approximately 1000 .

Figure 1B has demonstrated and has had the beginning substrate of the made plane copper layer of ECMD method.The United States Patent (USP) the 6th that the example of ECMD method was issued January 23 calendar year 2001,176, disclose for No. 992, its title is " method and apparatus of electrochemical mechanical deposition " (Method and apparatus for electro-chemical mechanicaldeposITion), and the assignee who is similarly the application has.The substrate that use has plane copper layer substrate is to start with venerated and is based on illustrational purpose.Method of the present invention (will show in Fig. 2) also can be used has thick beginning substrate along shape copper layer, this copper layer is to use for example ECD (Electro Chemical Deposition, electrochemical deposition) traditional electrical sedimentation manufacturing, and also be within the scope of the present invention.

The demonstrated later phases of polishing process of Figure 1B and 2 shown this kind beginning samples of Fig. 1 C and 1D.Polishing process of the present invention uses single sand belt or pad (polishing property or non-polishing property) in whole polishing process.

According to the present invention, barrier layer 15 is to use identical polishing pad or band (not shown) to polish with copper layer 12.Mat at first polishes and removes the copper layer 12 on the wafer 11, till reaching its " terminal point ", removes barrier layer 15 then till its " terminal point ".Based on the purpose of the various embodiment that describe the present invention, the terminal point of copper layer 12 can be defined as when reaching to barrier layer 15 at first the situation along this layer 12 during it is polishing.Similarly, the terminal point of barrier layer 15 can be defined as the situation when reaching to 14 top 17, zone at first during it is polishing.It should be noted, after the terminal point that copper and resistance barrier thing are removed, can under above-mentioned any one or two situations, carry out the excessive polishing of scheduled volume, to eliminate any presumable residue on the crystal column surface.Copper layer 12 is that first kind of polishing solution of mat transmission (describing hereinafter) polished to mat and with the mat (not shown).Chemical reaction in first kind of polishing solution cooperates the mechanical abrasive action of mat on copper layer 12 to remove copper layer 12.The removal of copper layer 12 is performed until and reaches till its terminal point, and terminal point is the starting point that is defined as its following barrier layer 15.The wafer 11 of gained shows in Fig. 1 C.Copper layer 12 has been removed to the height of barrier layer 15, and the partly 16 still reservations of barrier layer 15 and feature.

After the polish copper, for example using, the cleaning fluid of water comes clean wafer surface and mat surface simply.During cleaning, crystal column surface and mat surface can be separately or not separated.But if separate, then crystal column surface and mat surface can separate cleaning individually, and this kind cleaning can be carried out in the described hereinafter cleaning.After the cleaning, crystal column surface is rotatable or do not rotate removing excessive solution, but the redundant solution on the mat preferably blows off, so that different chemicals can be accepted in its surface.At this moment, second kind of polishing solution can be disposed on the identical mat, uses second kind of polishing solution to polish barrier layer 15 then, till the end face 17 that reaches zone 14.This polishing action has produced wafer 11 surfaces of complanation, shown in Fig. 1 D.Each feature 16 is an electrical isolation each other now partly, and end face is smooth and plane for further processing.Fig. 1 E is the flow chart of one or more embodiment of the present invention.In the process 10 of the chemico-mechanical polishing of semiconductor crystal wafer, individual other wafer (if or adopt the polishing system of balance, then or even a group wafer) must be located earlier so that on mat, polish (square 100).Locate mode can be used carrying termination or outer cover, and it is positioned to be in close proximity to polishing pad (seeing Fig. 6 A) with wafer.Next in process 10, supply first kind of polishing solution for copper layer polishing (square 110).During this process, this first kind of chemical polishing soln is to be disposed between copper layer 12 and the polishing pad, like this chemical and mechanically copper being polished, and the while wafer is depressed into to mat.Along with wafer is depressed into to polishing pad, polishing pad is with respect to the mobile mechanism that provides on the copper surface 12 of wafer.

This mechanism has been polished the copper surface in conjunction with the chemical reaction of polishing solution.The rotation of carrying termination helps the transmission of polishing solution, also helps to obtain uniform polishing speed on whole copper layer.The chemico-mechanical polishing of carrying out with first kind of polishing solution (it is particularly suitable for the polishing of copper) continues to arrive till the terminal point of copper layer 12 (checking at square 120) always.When the terminal point (when barrier layer 15 has come out) that reaches to copper layer 12, and do optionally excessive polishing, promptly removed first kind of polishing solution (square 130).First kind of polishing solution on the removing mat can use deionization, and (de-ionized, DI) high-pressure wash of water and/or blow air method (seeing below) are reached.Simultaneously, wafer 11 can independently clean with deionized water itself, cleans back rotation wafer and removes deionized water; Wafer is still wet usually, but above do not have unnecessary deionized water.

After removing first kind of polishing solution, promptly supply second kind of polishing solution (it is more suitable for the polishing of barrier layer than first kind of polishing solution) for barrier layer 15 polishings (square 140).Second kind of polishing solution is to be disposed on the polishing pad, and carries out the polishing of barrier layer.Use the barrier layer polishing of second kind of polishing solution to continue to arrive till the terminal point of barrier layer 15 (checking) at square 150 always.When the terminal point (when reaching) that reaches to barrier layer, promptly turn off second kind of polishing solution (square 160) to the end face 17 in zone 14.Can use similar or be same as the high-pressure wash that is used for removing first kind of polishing solution and/or blow air method and remove polishing solution on the mat, clean then and rotate wafer 11 to remove excessive solution.

The chemico-mechanical polishing of wafer 11 is considered as finishing, and wafer can be done next treatment step.Can be written into next wafer (or a group wafer) (square 170) this moment, repeats process 10 according to square 100 to 160 with new wafer (or group) then.

In one embodiment, novel characteristic of the present invention be identical mat be respectively applied for copper layer 12 and barrier layer 15 both.In addition, between carry out cleaning, to avoid inconsistent complexity between first polishing solution and second polishing solution.The mat kind that can be used for this kind polishing changes very wide.This kind mat comprises the fixedly mat of polishing property and the mat of non-polishing property, depends on desired polishing effect and used chemical solution and decides.Any mat all can be used to polish copper and barrier layer in above-mentioned two classes, but in each situation, the yes or no of the composition of used polishing solution possibility is identical.

In the example of process 10, copper layer 12 can be plane copper film.Attention is under this background, and " complanation approaches " copper film can be meant that thickness is being plane film less than the grade of 3000 dusts.Polishing pad can be the fixing mat of polishing property, for example derives from the MWR66 mat of 3M company.For this kind fixedly for the polishing property mat, can be the solution of abrasive-free as the polishing solution of polish copper, for example derive from the CPS-08 solution of 3M company equally, though the solution of grinding agent is arranged in the middle of also can using.In order on identical mat, to polish tantalum, can use derive from EKC through revising polishing solution (9030 polishing solution), use (from typical 5%) to be reduced to 2% or grinding agent still less simultaneously, though also can use other to be with or without the polishing solution of grinding agent.The modification of EKC 5 solution comprises that the pH with solution is increased to 5.5 from 4.0.For example, increasing pH can mat add aqua ammonia or azanol and reaches.If used mat is general polymeric pad, for example Thomas West 711, then still can be respectively copper be used identical polishing solution with tantalum, and promptly CPS-08 solution and EKC with 2% grinding agent are through revising solution.An advantage using a spot of grinding agent (2% but not 5%) is that the accessory substance of staying on the mat can be removed than being easier to.From staying the slurries on the mat, very high abrasive levels can cause the problem of processing.If can't from mat, remove particle and chemicals validly, then may influence the resistance barrier thing polishing step that is connected on copper polishing step back.In addition, under the very big situation of the activity of polishing solution, there is not the polishing solution of polishing particles can use with the polymeric pad of non-polishing property yet.

Said process also can use more than two kinds of polishing solutions and carry out, and for example, two kinds of different polishing solutions are used in the copper polishing, and a kind of polishing solution is used in the barrier layer polishing.This process also can use the CMP equipment shown in Fig. 6 A-B to implement.Flow process Figure 20 of Fig. 1 F is described in the CMP process embodiment that uses three kinds of polishing solutions on the identical mat.In the CMP (Chemical Mechanical Polishing) process 70 of semiconductor crystal wafer, individual other wafer (if or adopt the polishing system of balance, then or even a group wafer) must locate earlier as mentioned above so that on mat, polish (square 700).Next in process 70, supply first kind of copper polishing solution for copper layer fast polishing (square 710).The chemico-mechanical polishing of carrying out with first kind of copper polishing solution (its fast polishing copper) continues to arrive till the terminal point of copper layer 12 (checking at square 720) always.Turn off first kind of copper polishing solution, then carry out the cleaning (square 730) of wafer and mat.The high-pressure wash of use deionized water and/or blow air method are removed the polishing solution on the mat.Simultaneously, wafer 11 itself can the mat washed with de-ionized water rotates wafer then and cleans.Use after first kind of copper polishing solution, second kind of copper polishing solution is sent on the mat, stay residual copper residue (square 740) on the barrier layer 15 on 14 the end face 17 of zone with removing.What can select in addition is that the first polishing step timing is removed most copper to use first kind of copper polishing solution, and only stays the thick layer of 500-2000 dust, and it uses second kind of copper polishing solution to polish removal then.The polishing speed of second kind of copper polishing solution is usually less than first kind of copper polishing solution, and stays smoother copper surface, and has less defective.

After turning off and removing second kind of copper polishing solution (square 750), the third polishing solution that then will be used for barrier layer 15 polishings is sent to mat (square 760), and carries out the polishing of barrier layer.Use the barrier layer polishing of the third polishing solution to continue to arrive till the terminal point of barrier layer 15 (checking) at square 770 always.When the terminal point that reaches to barrier layer 15 is worked as the end face 17 that reaches to zone 14), promptly turn off the third polishing solution, and cleaning mat and wafer (square 780).Remaining polishing solution on the mat, can mat similar or be same as be used for removing the deionized water high-pressure wash of copper polishing solution and then the method for blow air remove.Wafer 11 also can be cleaned and be rotated.After having removed resistance barrier thing, the chemico-mechanical polishing of wafer 11 is considered as finishing, and wafer can be done next treatment step.Can be written into next wafer (or a group wafer) (square 790) this moment, repeats process 70 according to square 700 to 790 with new wafer (or group) then, shown in Fig. 1 F.By doing description as can be seen, in this way, use identical mat and multiple polishing solution make a return journey copper removal layer 12 and barrier layer 15 both.As way before, fixedly polishing property mat and general mat or all available used as said purpose of polymeric pad.Any mat all can be used to polish copper and barrier layer in above-mentioned two classes, but in each situation, the yes or no of the composition of used polishing solution possibility is identical.

In the example of process 70, polishing pad can be fixing polishing property mat, for example derives from the MWR66 mat of 3M company.First kind of copper polishing solution can be to have the high solution of removing the abrasive-free of speed, for example also is the CPS-11 solution that derives from 3M company.Apply about 1psi pressure to the situation of crystal column surface at mat, it is about 4000 of per minute that the copper of CPS-11 solution is removed speed.After the CPS-11 polishing, may leave some copper residues on the barrier layer, perhaps can deliberately leave certain thickness copper on the surface.This kind residue can use second kind of copper polishing solution to polish removal, and second kind of copper polishing solution should be primarily aimed at remaining residue and work, but should have minimum etch effects to the copper in the feature.So can make the depression situation drop to minimum.

Second kind of copper polishing solution can be to have the solution that low copper is removed the abrasive-free of speed, for example derives from the CPS-12 solution of 3M company.It is about 1000 of per minute that the copper of CPS-12 solution is removed speed, and removes the copper residue from the top of barrier layer.In order on identical mat, to polish tantalum, can discuss as mentioned use derive from EKC through revising polishing solution, grinding agent is reduced to 2% or still less simultaneously.As situation before, the modification of EKC solution comprises that the pH with solution is increased to about 5.5 from 4.0.For example and, increase pH and can mat add aqua ammonia or azanol and reach.Again, if used mat is general polymeric pad, Thomas West711 for example then still can use identical polishing solution to copper with tantalum respectively, and promptly CPS-11, CPS-12 and EKC with 2% grinding agent are through revising solution.The another kind of beginning of Fig. 2 graphic extension substrate is with the method for the present invention of demonstrating.Fig. 2 demonstration has the beginning substrate 11 ' of suitable shape copper layer, and this copper layer can use for example traditional electrical deposition process manufacturing of ECD (ElectroChemical Deposition, electrochemical deposition).Fig. 2 graphic extension generally includes the some of the exemplary substrate 11 ' of Silicon Wafer.The graphic extension of substrate 11 ' partly comprises the insulating barrier 14 ' or the dielectric material of sample preparation.For example the hole 16 ' of groove and via or feature partly are that mat uses the technology of knowing, and insulating barrier etching off is partly formed in insulating barrier 14 '.For example the barrier layer 15 ' of tantalum or tantalum nitride or tantalum/tantalum nitride stack layer is in hole 16 ' and the end face of insulating barrier 14 ' 17 ' is gone up formation.The thickness of barrier layer can be in the grade of 100-300 or littler.Though show, barrier layer 15 ' is that lining approaches copper kind crystal layer with one, grows on barrier layer to cause copper.

Copper layer 12 ' is to use traditional suitable shape deposition process and form on copper kind crystal layer.For instance, in typical semiconductor element, conductive layer 12 ' be the mat deposit thickness be approximately feature partly 16 ' thickness 1.5-2.00 doubly copper and form.According to principle of the present invention, as the situation of the wafer 11 that has plane copper layer 12 in polishing, the copper layer 12 ' and the barrier layer 15 ' of wafer 11 ' can use above-mentioned or following embodiment to polish removal.Each stage of polishing process also is Fig. 1 C and 1D carrying out of being demonstrated as mentioned.For the sake of clarity, following embodiment describes Figure 1A ~ 1D that cooperation is used for the situation of surface polishing shape copper layer and beneath tantalum barrier layer.Yet identical embodiment can be applied to cooperate described copper layer 12 ' of Fig. 2 and beneath tantalum barrier layer 15 '.Unique difference is the thickness of the latter's copper layer, and the polishing of the plane layer that wherein said process may relatively approach will spend more time.The difference of copper layer thickness among consideration and Figure 1B and 2, just the processing way that will realize two kinds of different polishing solutions of use shown in Figure 3 can be more suitable for handling thin copper layer and the barrier layer of Figure 1B, and use the processing way of three kinds of polishing solution chemicals can be more suitable for removing Fig. 2 than thick copper layer and barrier layer.That can select in addition is to use two kinds of polishing solutions in thicker copper, but can increase pressure on the wafer, increasing the removal speed of first kind of solution, till having removed certain thickness copper (for example 2/3rds).Can reduce pressure then, and still use first kind of solution to remove remaining copper, continue after use second kind of solution to polish barrier layer.

The flow chart of Fig. 3 is at least one embodiment that the present invention uses polishing solution circuit separately.Process 20 is to use two polishing solution circuits that separate to implement a kind of mode of the process 10 of Fig. 1 E.So that the first polishing solution circuit (polishing solution circuit #1) is started in polishing (square 200) then, so that supply polishing solution to polishing pad (square 210), the while is referring to Fig. 6 A-B with a wafer (or a group wafer) location.The polishing solution (for example CPS-08) that polishing solution circuit #1 is supplied is used in polish copper layer 12 up to its terminal point.Polishing solution circuit #1 can keep starting always, (checks at square 220) up to reaching till the terminal point of copper.When the terminal point that reaches to copper, promptly turn off polishing solution circuit #1 (square 230).In order to remove on the mat polishing solution from circuit #1, the termination of support wafer can be promoted to the mat top, and with deionization (DI) water wafer is imposed cleaning, and it falls within (square 235) on the mat from the crystal column surface bounce-back then.Rotate wafer 11 simultaneously, and if suitable, mat for example blows that the fluid of air removes excessive solution (square 235).

Behind cleaning mat and wafer 11, promptly start polishing solution circuit #2 (square 240).The polishing solution that polishing solution circuit #2 is supplied is used in the barrier layer 15 (for example tantalum) on the wafer polishing.Polishing solution circuit #2 can keep starting always, (checks at square 250) up to reaching till the terminal point of barrier layer 15.Promptly turn off polishing solution circuit #2 (square 255) after reaching to terminal.In order to remove on mat and the wafer 11 polishing solution from circuit #2, the termination of support wafer is promoted to the mat top at this moment, and with deionization (DI) water wafer 11 is imposed cleaning (square 260).Can rotate wafer then and remove excessive solution.The water that cleans falls within on the mat from wafer 11 bounce-backs, cleans mat by this.Then mat is blown to remove excessive solution.After having cleaned mat and wafer 11, promptly be written into next wafer (or a group wafer) (square 270), and begin wafer repetitive process 20 newly being written into from square 200.

The flow chart of Fig. 4 is at least one embodiment that the present invention uses polishing solution circuit separately.Process 30 is to use the another kind of polishing process of identical mat and two polishing solution circuits that separate.The for example wafer of wafer 11 (or a group wafer) is located so that polishing (square 300), start two polishing solution circuits (polishing solution circuit #1 and polishing solution circuit #2) then, so that the supply polishing solution is to polishing pad (square 310), simultaneously referring to Fig. 6 A-B.The composition that polishing solution circuit #1 and #2 are supplied is used in the copper layer 12 on the wafer polishing 11.Polishing solution circuit #1 supplies oxidant (for example hydrogen peroxide), complex reagent and inhibitor.Polishing solution circuit #2 supply complex reagent and inhibitor, but do not have oxidant.

Complex reagent comprises for example chemicals of organic acid and amine, and inhibitor be typically BTA (benzotriazole, BTA).The complex reagent effect is to increase etching/polishing speed, and inhibitor reduces this speed.Inhibitor is deposited in the zone of feature part 16.Copper surface in the inhibitor protection feature part is not so complex reagent can exceedingly be polished in these zones.This guarantees that polishing solution has low static etch rate, thereby helps to avoid to take place the depression situation, even without the mechanism of mat also in this way.Though two the polishing solution circuit all starts, the composition that polishing solution circuit #2 is supplied can not cause disadvantageous impact to the polishing of copper, because the composition of each circuit is shared many common compositions.Therefore, the interactive chance of generation is limited between the polishing solution of two circuits.The removal of copper (polishing) speed increases along with the oxidant concentration in the polishing solution, and reaches a peak value.Yet, for example removal of the barrier layer materials of tantalum, less dependence oxidant concentration, and more dependence mechanical lapping.

Cleaning step between the copper of above-mentioned same wafer and the tantalum polishing is to guarantee that two kinds of reciprocations between the polishing solution are for minimum.Yet,, just do not need to clean or cleaning between copper and the tantalum polishing if two kinds of polishing solutions are compatible, that is to say, except the polishing solution circuit switches to the tantalum polishing solution from the copper polishing solution, the whole section polishing process of same wafer from copper to the tantalum, in the middle of do not have cleaning step.Use single polishing step to come in the selection of polish copper and tantalum at another kind, two kinds of polishing solutions can be simplified to single polishing solution circuit.

Polishing solution circuit #1 and #2 can keep starting always, (check at square 320) up to reaching till the terminal point of copper.When the terminal point that reaches to copper, promptly turn off polishing solution circuit #1 (square 330).Because the polishing solution among polishing solution circuit #1 and the #2 is compatible on certain degree, deionization (DI) water clean rotate wafer then or on mat blow air remove aforementioned solution and deionization (DI) water lotion then is selectable, but may not need.Therefore polishing solution circuit #2 keeps starting.The polishing solution that polishing solution circuit #2 is supplied is used in the barrier layer (tantalum) 15 on the wafer polishing 11.When the terminal point that reaches to tantalum, promptly turn off polishing solution circuit #2 (square 355).In order to remove on the wafer from the polishing solution of circuit #2, impose cleaning with deionization (DI) water, rotate then to remove excessive solution (square 360).When having cleaned wafer and mat, promptly be written into next wafer (or a group wafer) (square 370), and begin wafer repetitive process 30 newly being written into from square 300.

The flow chart of Fig. 5 is at least one embodiment that the present invention uses composition circuit and oxidant circuit.Process 40 is to use the separately another kind of polishing process of circuit (one comprise polishing solution and another comprises oxidant) of identical mat and two.Two circuits (polishing solution circuit and oxidant circuit) so that polish (square 400), are started then in wafer (or a group wafer) location, so that supply polishing solution and oxidant are to polishing pad (square 410).The composition that polishing solution circuit and oxidant circuit are supplied is used in the copper layer 12 on the wafer polishing.Polishing solution line feed complex reagent and inhibitor.The supply of oxidant circuit oxidant, for example hydrogen peroxide.The removal of copper (polishing) speed increases and increases along with oxidant concentration, and reaches a peak value.Yet, the less dependence oxidant concentration of the removal of tantalum, and more dependence mechanical lapping.

Polishing solution circuit and oxidant circuit can keep starting always, (check at square 420) up to reaching till the terminal point of copper.When the terminal point that reaches to copper, promptly turn off oxidant circuit (square 430).Because the solution in polishing solution circuit and the oxidant circuit is compatible on certain degree, so can not need deionization (DI) water to clean to rotate wafer then and the step of blow air on mat.The polishing solution circuit still keeps starting.The polishing solution that the polishing solution circuit is supplied is used in the polishing tantalum layer then up to its terminal point (top in zone).When the terminal point that reaches to tantalum, promptly turn off polishing solution circuit (square 455).Can use the excessive polishing of some overstep of end point, to remove presumable residue.In order to clean wafer, with deionization (DI) water wafer is imposed cleaning, rotate wafer (square 460) simultaneously, this also impacts and cleans mat.When having cleaned mat and wafer, promptly be written into next wafer (or a group wafer) (square 470), and begin wafer repetitive process 40 newly being written into from square 400.

Fig. 6 A-B graphic extension is according to the end view and the plan view of the polishing station of one or more embodiment institute construction of the present invention.Polishing wafer station 50 comprises the termination of a plurality of polishing members and wafer outer cover 540 or carrying wafer.Wafer outer cover 540 is firmly wafer 550 location, so come out fully in the front 560 of wafer.Polishing station 50 comprise as the polishing pad 510 of polishing positive 560, with bidirectional linear or back and forth (front and back) motion drive the machine-processed (not shown) of polishing pad 510, and accommodating fluid is supported to the support plate 520 at mat 510 back sides when crystal column surface 560 that mat 510 polishings have exposed.Two-way linear movement is also referred to as opposite linear movement.The bottom surface of polishing pad 510 can additionally adhere to tool elasticity but firm material (not shown) to support mat 510.Polishing pad 510 be used for the copper of polished surface 560 and barrier layer (for example tantalum) both.Two-layer crystal column surface 560 in exposure uses single mat, promptly no longer need use a plurality of mats respectively, and also may no longer need use a plurality of polishing stations respectively.Polishing pad 510 can be abrasive-free person, polymeric pad for example, or the fixing mat of polishing property.Because tantalum has different characteristics with the copper layer,, then must use different polishing solutions if polish both with identical mat.Be noted that described bidirectional linear polisher preferably as polishing station 50, for example United States Patent (USP) the 6th, 103, and No. the 09/684th, 059, No. 628 and U.S. patent application case are described, this two include within this paper to put forward the mode of stating all clearly.When so employed, polishing pad is belt preferably, its some in processing region, do two-way moving, can comprise on it or not comprise fixing grinding agent, and in polishing area, preferably float on the platform supports.In addition, belt can be mobile progressively, so use different partly (different parts can be overlapping or not overlapping with previous used part in processing region) of identical belt, and can be distinguished in yes or no the different time by employed Treatment Solution kind in the different time.

Though the polishing station of at present preferred the above-mentioned type, but the present invention is not limited to use this kind polishing station, but said process can use with other CMP polishing stations, comprises that those use linear rotating band, cooperate the static polishing pad of the wafer that moves, the rotating polishing pad that moves relative to the wafer of static or rotation or other.In addition, can use the mat of thin and few rigidity and thicker or the mat of rigidity is more arranged, this depends on desired effect and decides.The mat back can be with or without support plate.

Used polishing solution and cleaning solution during the polishing preferably is supplied to the both sides of the polishing station 50 that uses the bidirectional linear polisher with two or more polishing solution circuits (for example circuit #1 and circuit #2).In at least one embodiment of the present invention, polishing solution circuit #1 comprises left side supply circuit 512 and right side supply circuit 511.Similarly, polishing solution circuit #2 comprises left side supply circuit 514 and right side supply circuit 513.The right side of supply circuit 511 and 513 supply polishing stations 50, and the left side of supply circuit 512 and 514 supply polishing stations 50.Though be not shown among Fig. 6 A-B and the 7A-B, will be understood that polishing station can have the polishing solution circuit (for example circuit #3 does not show) more than two, it has similar construction and is equipped with other supply line road as All other routes #1 and #2.This construction with circuit #3 can be used to cooperate the described embodiment of Fig. 1 F.In addition, the number of nozzle can remain unchanged, but can use valve to bring different polishing solutions through identical nozzle.The multiple mode of reaching this for ripe for this operator, be conspicuous.

The polishing of wafer 550 now will various embodiments according to the present invention be described.In one embodiment, wafer 550 is written in the outer cover 540 and is positioned after polishing station 50 tops, starts polishing solution circuit #1 with left side and the right side of supply polishing solution to mat 510.When starting polishing solution circuit #1, right side supply circuit 511 and left side supply circuit 512 can come into operation, and the supply polishing solution is to mat 510.Right side supply circuit 513 and left side supply circuit 514 will be closed.Mat 510 is by 530 drivings of mechanism, and this motion combines the chemical reactivity of polishing solution on wafer 550 surfaces 560 of polishing solution circuit #1, in order to the copper on the polished surface 560.It should be noted that for the system of Fig. 6 A and 6B, the transmission of polishing solution also can combine with the motion of mat.For example, when mat moved on to the left side, polishing solution was sent from nozzle 511, and when mat moved on to the right side, polishing solution was sent from nozzle 512.In this way, the mat that always is moved of polishing solution is shifted to wafer.The waste of polishing solution just drops to minimum.When the terminal point that reaches to copper, promptly turn off polishing solution circuit #1.This need cut off supply circuit 511 and 512 or make it not act on.

For the front 560 of removing wafer 550 and the residue polishing solution on the mat 510, when wafer is promoted to the mat top, the deionized water nozzle water-jet to crystal column surface.Water falls within on the mat surface from the wafer bounce-back, and has cleaned the surface of wafer and mat.During this cleaning, wafer preferably can rotate.After the water spray, hair-dryer 580 blows to air on the mat 510, to remove excessive solution.Then, start polishing solution circuit #2, so circuit 513 is supplied on the right side and left side supply circuit 514 can come into operation respectively, the supply polishing solution is to the right side and the left side of mat 510.The polishing solution of polishing solution circuit #2 supply is the polishing that is designed for barrier layer (for example tantalum).Put on mat 510 motions on surface 560 and the polishing solution of polishing solution circuit #2, in order to the tantalum on wafer polishing 550 surfaces 560.When the terminal point that reaches to tantalum, promptly turn off polishing solution circuit #2 (supply circuit 513 and 514 is not acted on), cleaning mat 510 (using washer 570), and remove excessive solution (using hair-dryer 580), be written into next wafer then and to outer cover 540, supply polishing.Washer 570 and hair-dryer 580 can be implemented in many ways, comprise the use high pressure nozzle.

Discussed above and be fit to the polishing solution of this kind polishing and the exemplary type of mat.In certain embodiments of the present invention, polishing solution circuit #1 supply complex reagent, inhibitor and oxidant.Polishing solution circuit #2 supplies complex reagent and inhibitor, but does not have the oxidant of oxidant or supply extremely low concentration.In this kind embodiment, polishing solution circuit #1 and #2 both may start (therefore whole four supply circuits 511,512,513 and 514 all can start) during the polishing of copper.After the copper polishing, can turn off polishing solution circuit #1, venerating the supply circuit 513 and 514 that stays polishing solution circuit #2 has effect (starting).In other embodiments, polishing solution circuit #2 can transmit complex reagent and inhibitor, and polishing solution circuit #1 venerates the transmission oxidant.Again, during the polishing of copper, circuit #1 and #2 may can start, and may turn off polishing solution circuit #1 then and polish for tantalum.

Use mat to come the detailed view of wafer polishing in Fig. 7 A-B graphic extension the foregoing description.Return and state Figure 1B, the wafer 11 that polish has multilayer, comprises copper layer 12 and barrier layer 15.Before polishing, the front 645 of exposure can expose copper layer 12 earlier and do polishing.After 12 polishing of copper layer, the barrier layer 15 (seeing Fig. 1 C) under the wafer 11 of gained can expose.Wafer 11 location, so make its front 645 nestle up the surface of polishing pad 640.

With reference to figure 7A, it is presented at the polishing station of polishing pattern.Polishing solution is supplied in the both sides of polishing pad 640 by two polishing solution circuits (circuit #1 and circuit #2).In at least one embodiment of the present invention, polishing solution circuit #1 comprises left side supply circuit 612 and right side supply circuit 611.Similarly, polishing solution circuit #2 comprises left side supply circuit 614 and right side supply circuit 613.The

supply circuit

611 and 613 the supply polishing pads 640 the right side, and the

supply circuit

612 and 614 the supply polishing pads 640 the left side.

In one embodiment, having comprised oxidation and chemical machinery ground from the polishing solution of circuit #1 removes the chemicals of the copper layer 12 on surface 645 and is supplied between wafer 11 and the polishing pad 640.After 12 polishing of copper layer, promptly turn off polishing solution circuit #1.Wafer 11 is promoted to mat 640 tops, shown in Fig. 7 B.When wafer 11 is during in the position shown in Fig. 7 B, from the polishing solution on washed with de-ionized water agent (corrosion inhibitor that comprises 0-0.01%) the removing wafer 11 of washer 670, it falls within on the mat 640 from wafer 11 (front 645 on) bounce-back then, and removes the polishing solution on the mat 640.The water that cleans mat may be deposited on the mat, and this may dilute next polishing solution unfriendly.Hair-dryer 680 is blown into air on the mat, so that the dilution of next polishing solution reaches minimum.

After the cleaning, wafer 11 is got back to the position shown in Fig. 7 A.Start polishing solution circuit #2 then, the supply polishing solution is with polishing barrier layer 15, and barrier layer 15 just comes out after 12 polishing of copper layer are removed.The effect of mat 640 with from the polishing solution wafer polishing 11 of polishing solution circuit #2 the layer 15.Wafer can be got back to the position of Fig. 7 A then, so that wafer 11 and mat 640 are done last cleaning.In other embodiments of the invention, can all start polishing solution circuit #1 and polishing solution circuit #2 during beginning.In this case, polishing solution circuit #1 can comprise the identical composition that is transmitted with polishing solution circuit #2, but also can transmit extra oxidant composition.Polishing solution circuit #1 and polishing solution circuit #2 can polish copper layers 12.After 12 polishing of copper layer, turn off polishing solution circuit #1, only remaining polishing solution circuit #2 starts.There is not the polishing solution circuit #2 of the oxidant of transmission or carry electrode low concentration can polish barrier layer 15.In additional embodiments of the present invention, polishing solution circuit #2 can transmit polishing composition (for example complex reagent and inhibitor), and polishing solution circuit #1 only transmits oxidant.Again, in this case, during the polishing of copper layer 12, polishing solution circuit #1 and #2 can start, then after barrier layer 15 polishing during, oxidant circuit (polishing solution circuit #1) can be turned off.When starting two circuits in this way, on mat, can need good mixing from the oxidant of polishing solution circuit #1 with from the composition of circuit #2, to guarantee whole solution uniform distribution is arranged on mat.

In one or more embodiment of the present invention, described by fixing wherein a kind of polishing pad of forming of polishing property or aggretion type pad.In the embodiment that the present invention can select in addition, also single mat might be separated or is distinguished into one or more fixedly polishing property section and one or more polymerisation zone.So that the chemico-mechanical polishing of the certain layer on wafer when best processing effect is arranged, mat can advance or retreat, the suitable section of mat is placed the position of wafer polishing when each section that needs mat.Therefore, fixedly the polishing property section can be used for the polish copper layer, and softer polymerisation zone can be used for polishing barrier layer.The reciprocating motion of the optimum decision system of Fig. 6 A and particular design allow this kind flexibility.

As described above, can in single CMP station, use single polishing pad to carry out, perhaps in a plurality of CMP station, use a plurality of polishing pads to carry out at this polishing technology of narrating.As mentioned above, in one embodiment, the removal of copper layer and barrier layer can be carried out in identical CMP station.In this embodiment, the removal of copper layer can be carried out before removing barrier layer.According to this procedural order, in first step, can use the polishing pad of fixing polishing property that a large amount of copper are removed up to barrier layer.In the step that this copper is removed, polishing solution can comprise or not comprise particle.In second step, fixedly the polishing pad of polishing property can be used in combination with the polishing solution with solids, to remove the residual copper layer on barrier layer surface, simultaneously workpiece is imposed downward power.This downward power can be smaller downward force.Just can remove barrier layer according to these steps.The removal of barrier layer can utilize the part of being made by flexible polymer on the polishing pad.That is to say, polishing pad can have one fixedly polishing property part and by flexible polymer make second partly.The solution of selectivity polishing tantalum can be sent to polishing pad to remove barrier layer, simultaneously workpiece is imposed slight downward power.

In another embodiment, the removal of copper and barrier layer can use the CMP system (the CMP instrument of integration) of integration to carry out on individual other polishing pad.In one embodiment of the invention, different mats are to be arranged in indivedual CMP station of same instrument.The exemplary CMP station that is suitable for the CMP system that integrates is in above describing with reference to figure 6A, and also can be with reference to the U.S. patent application case of submitting on January 17th, 2003 the 10/346th, No. 425 (NT-278-US), its title is " advanced person's of sensitive detection endpoint chemical-mechanical polishing system " (AdvancedChemical Mechanical Polishing System with Smart Endpoint Detection), and it includes this paper in to put forward the mode of stating.A plurality of CMP station is incorporated in the instrument of an integration, might improve the polishing difference of copper and barrier layer.

Fig. 8 shows the calcspar of integrating CMP system 800 with a plurality of CMP station according to embodiments of the invention.In an illustrated embodiment, the CMP system 800 of integration has the 810 and the 2nd CMP station, CMP station 820.In CMP station 810, in the first polishing program, use the first polishing pad (not shown) and first polishing solution copper removal layer of making a return journey.For the present invention, first polishing pad is the fixing polishing pad of polishing property, and first polishing solution comprises and grinds and/or lubricated particle.In this regard, polishing particles is when the lubricant that can be used as polishing when fixedly the polishing pad of polishing property combines.Polishing particles is the solids in the slurries.During the first polishing program, wafer is dropped on first polishing pad, and first polishing solution is sent on first polishing pad.First polishing pad moves (seeing Fig. 6 A) above support plate, impose fluid pressure simultaneously under first polishing pad.When the copper layer is removed barrier layer (seeing Fig. 1 C) on crystal column surface, promptly carry out the removal process (the second polishing program) of barrier layer at the 2nd CMP station 820.The 2nd CMP station 820 has the second polishing pad (not shown) and uses second polishing solution.Second polishing pad can be the polishing pad of polymerization/on-fixed polishing property.For instance, second polishing pad can be made by the soft polymeric material of for example polyurethane.For the present invention, in the process that barrier layer is removed, use the selectivity polishing solution as second polishing solution.In this regard, this selectivity polishing solution is sent to and is fit to remove on the polymerization polishing pad of resistance barrier material, and mobile mat polishes.Can apply fluid pressure under second polishing pad.The delamination of using these technology can make the pressure on the wafer and being caused minimizes.These technology also can make depression situation and scratch minimize.Using two CMP stations to venerate in the CMP system that integrates is for example, also can envision the integration CMP system with extra CMP station.

The flow chart of Fig. 9 is one of the copper of polished semiconductor wafer and method of barrier layer embodiment, and its use has the integration CMP system at a plurality of CMP station, for example with reference to the described CMP of figure 8 system.In step 910, on first part of polishing pad, use polishing solution to come the ground floor of polished semiconductor wafer.In one embodiment, ground floor comprises copper.In step 920, on second part of polishing pad, use polishing solution to come the second layer of polished semiconductor wafer.In one embodiment, the second layer comprises tantalum.It should be understood that and to polish, and can use more than two partly polishing pads more than two-layer.The polishing solution that is used to polish different layers can be identical polishing solution or different polishing solutions.The different parts of polishing pad can be positioned on the identical polishing pad or be positioned on the different polishing pads.Individual other polishing solution and polishing pad preferably design and/or are suitable as the certain layer of wafer polishing.For example, solution and mat can be suitable for polish copper or be suitable for polishing barrier layer (for example tantalum).

According to the present invention, once venerate polishing one wafer usually.Though the present invention is fit to the single wafer of stock removal polishing, ripely can revise the preferred embodiments of the present invention, so that stock removal polishing multi-disc wafer in this operator.Be appreciated that, in aforementioned discussion and claims, crystal column surface and any surface that is formed at the layer on the wafer before speech such as " crystal column surface " and " surface of wafer " includes but not limited to handle comprise the metal, oxide, glass fibre, pottery of oxidation etc.In addition, though it is top mainly in the two-layer polishing of discussion, i.e. a metal level (for example copper) and barrier layer (for example tantalum), but can use said technology to polish the layer of any amount and kind, for example with the mat of fixing polishing property in response to the multiple polishing solution of each layer supply in each layer.Will be appreciated that, remove one deck and the lip-deep one deck synonym of polished semiconductor wafer from semiconductor wafer surface.In the several different methods described herein, " square " and " step " all is meant treatment step.

Disclosed multiple preferred embodiment of the present invention though illustrate for example, but ripely will realize in this operator, under the category of the present invention and spirit that is disclosed in not deviating from the claim scope, various modifications, interpolation and/or replacement are possible.

Claims

1. the last a plurality of layers method in polished semiconductor wafer surface, the method comprises the following steps:

On first part of polishing pad, use polishing solution to polish ground floor; And

On another part of polishing pad, use polishing solution to polish another layer.

2. according to the process of claim 1 wherein that the used polishing solution of the polishing solution that is used to polish ground floor and another layer of polishing is different.

3. according to the method for claim 2, wherein ground floor is a copper, and is used to polish the suitable polish copper of polishing solution of ground floor; And wherein another layer is a barrier layer, is fit to the polishing barrier layer and polish the used polishing solution of this another layer.

According to the process of claim 1 wherein polishing pad first partly and another of polishing pad partly be to be positioned at the part of two on the different polishing pads.

5. according to the method for claim 2, wherein another of first of the polishing pad part and polishing pad partly is to be positioned at two on the different polishing pads partly.

6. according to the process of claim 1 wherein that ground floor is a copper, and polishing pad first partly be fit to polish copper, and wherein another layer is a barrier layer, and another of polishing pad partly is fit to polishing barrier layer.

7. according to the method for claim 3, wherein ground floor is a copper, and the first partly suitable polish copper of polishing pad, and wherein another layer is a barrier layer, and another partly suitable polishing barrier layer of polishing pad.

8. according to the method for claim 2, it further may further comprise the steps: before another layer of polishing, partly remove the polishing solution that is used to polish ground floor from first of wafer and polishing pad.

9. method according to Claim 8, it further may further comprise the steps:

Supply is used to polish first part of the polishing solution of ground floor to polishing pad; And

Removing is used to polish after the polishing solution of ground floor, and supply is used to polish the polishing solution of another layer another part to polishing pad.

10. according to the method for claim 1, wherein the polishing of the polishing of ground floor and another layer is to use opposite linear planarization and with respect to support platform and the part of mobile polishing pad is carried out, this support platform is to be used for accommodating fluid to the part of the polishing pad back side partly with support of polishing pad.

11. according to the method for claim 1, it further may further comprise the steps: use another polishing solution to polish this ground floor.

12. the last first and second layers method in polished semiconductor wafer surface, the method comprises the following steps:

On mat, use first polishing solution to polish this ground floor; And

On this identical mat, use second polishing solution to polish this second layer.

13. according to the method for claim 12, it further may further comprise the steps: before this second layer of polishing, remove this first polishing solution from this wafer and this mat.

14. according to the method for claim 13, wherein reach to the terminal point of this ground floor, remove first polishing solution.

15. according to the method for claim 13, it further may further comprise the steps:

Supply this first polishing solution to this mat; And

Remove after this first polishing solution, supply this second polishing solution to this mat.

16. according to the method for claim 13, wherein reach to the terminal point of this second layer, remove this second polishing solution.

17. according to the method for claim 13, wherein this first polishing solution of this removing comprises:

Rise this wafer from this mat;

Clean this surface of this wafer with cleaning solution;

Remove unnecessary cleaning solution after cleaning; And

Reduce this wafer to this mat.

18. according to the method for claim 12, wherein this polishing of first and second layers is to use opposite linear planarization to carry out.

19. according to the method for claim 12, wherein use this polishing of this ground floor of this first polishing solution to continue to carry out, up to reaching till the terminal point of ground floor; And

Wherein use this polishing of this second layer of this second polishing solution to continue to carry out, up to reaching till the terminal point of the second layer.

20. according to the method for claim 12, it comprises that further another polishing solution of use polishes this ground floor.

21. a semiconductor wafer processing system that comprises the integration of a plurality for the treatment of stations, it comprises:

First polishing pad of the ground floor of polished semiconductor wafer; And

Another polishing pad of another layer of polished semiconductor wafer.

22. according to the semiconductor wafer processing system of the integration of claim 21, it further comprises:

Transmit the first polishing solution circuit of polishing solution to the first polishing pad; And

Transmit polishing solution another polishing solution circuit to another polishing pad.

23. according to the semiconductor wafer processing system of the integration of claim 22, the polishing solution that wherein is sent to first polishing pad is different with the polishing solution that is sent to another polishing pad.

24. according to the semiconductor wafer processing system of the integration of claim 23, wherein first polishing pad is the fixing polishing pad of polishing property, and the polishing solution that is sent to first polishing pad comprises polishing particles.

25. according to the semiconductor wafer processing system of the integration of claim 21, wherein another polishing pad is the fixing polymerization polishing pad of polishing property not.

26. according to the semiconductor wafer processing system of the integration of claim 23, the polishing solution that wherein is sent to another polishing pad is slurries of removing barrier layer, it comprises:

About 0.1% to about 5% polishing particles;

Remove the chemicals of barrier layer; And

Regulate the composition of pH-value,

Wherein the pH-value of solution is between 7 and 12.

27. according to the semiconductor wafer processing system of the integration of claim 23, the polishing solution that wherein is sent to another polishing pad is a kind of slurries, it comprises:

About 1% to about 2% abrasive particle concentration, wherein polishing particles is to be selected from a group that comprises smoked silicon, glue-like silica and cerium oxide; Azanol; Corrosion inhibitor; And

Regulate the composition of pH-value, it is selected from a group that comprises potassium hydroxide, NaOH, ammonium hydroxide and tetramethylammonium hydroxide,

Wherein the pH-value of solution is between about 9 and about 10.

28. according to the semiconductor wafer processing system of the integration of claim 21, it further comprises:

The one CMP station is comprising first polishing pad; And

Another CMP station is comprising another polishing pad.

29. according to the semiconductor wafer processing system of the integration of claim 21, wherein first polishing pad and another polishing pad are to use opposite linear movement to come wafer polishing.

30. the chemical mechanical polishing apparatus as the polished semiconductor wafer surface, it comprises:

Polisher, it comprises the ground floor on wafer polishing surface and the single mat of the second layer; And

The polishing solution delivery system, its in first period provide first polishing solution to this single mat polishing this ground floor, and in second period provide second polishing solution extremely this single mat to polish this second layer.

31. according to the chemical mechanical polishing apparatus of claim 30, wherein this mat is the fixing mat of polishing property.

32. according to the chemical mechanical polishing apparatus of claim 31, wherein this first and second polishing solution does not contain any polishing particles.

33. according to the chemical mechanical polishing apparatus of claim 31, wherein this first and second polishing solution comprises and is less than 5% polishing particles.

34. according to the chemical mechanical polishing apparatus of claim 30, wherein chemical mechanical means is mutually antilinear chemico-mechanical polishing device.

35. according to the chemical mechanical polishing apparatus of claim 30, it further is included in the system of cleaning mat and wafer between first and second periods.

36. according to the chemical mechanical polishing apparatus of claim 30, wherein this ground floor comprises copper, and this second layer comprises tantalum.

37. according to the chemical mechanical polishing apparatus of claim 30, wherein this first polishing solution comprises oxidant, complex reagent and corrosion inhibitor, and this second polishing solution comprises complex reagent and corrosion inhibitor.

38. according to the chemical mechanical polishing apparatus of claim 30, wherein second polishing solution is slurries of removing barrier layer, it comprises:

About 0.1% to about 5% polishing particles;

Remove the chemicals of barrier layer; And

Regulate the composition of pH-value,

Wherein the pH-value of solution is between 7 and 12.

39. according to the chemical mechanical polishing apparatus of claim 30, wherein second polishing solution is a kind of slurries, it comprises:

Wherein the pH-value of solution is between about 9 and about 10.

40. according to the chemical mechanical polishing apparatus of claim 30, wherein said single mat comprises first part and second partly, this first partly suitable this ground floor of polishing, and this second part is fit to this second layer of polishing.